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GET /api/patches/124111/?format=api
{ "id": 124111, "url": "http://patchwork.dpdk.org/api/patches/124111/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230217073228.340815-5-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230217073228.340815-5-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230217073228.340815-5-junfeng.guo@intel.com", "date": "2023-02-17T07:32:22", "name": "[RFC,v3,04/10] net/gve: support queue release and stop for DQO", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c7cc13542cea2a529f42a1c93e3d0a0812707c3f", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230217073228.340815-5-junfeng.guo@intel.com/mbox/", "series": [ { "id": 27056, "url": "http://patchwork.dpdk.org/api/series/27056/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27056", "date": "2023-02-17T07:32:18", "name": "gve PMD enhancement", "version": 3, "mbox": "http://patchwork.dpdk.org/series/27056/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/124111/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/124111/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ED08041CBC;\n\tFri, 17 Feb 2023 08:39:23 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C70BF42D17;\n\tFri, 17 Feb 2023 08:39:12 +0100 (CET)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 9F45842D1A\n for <dev@dpdk.org>; Fri, 17 Feb 2023 08:39:11 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Feb 2023 23:39:11 -0800", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by orsmga002.jf.intel.com with ESMTP; 16 Feb 2023 23:39:07 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1676619551; x=1708155551;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=AhWCJEmWSRMwNO17L2Cb9F25sU/UFhb9a83uAFdBhM4=;\n b=ikyiu2JPV9P7GLV85YT1X3n4xaWw3xoysAcW4MHPoUU60ur+A75/wLrJ\n wbnElMSWrARQdXziqz4LPGfxZDAIR77G7URKfPnJQdf8iJ68eMFbarC3+\n QySXyMMxTJ5WfFNs3sMftsQKb5pkjj6Vsx2gAQ/VO6/R9P0cKzBmQqLUH\n 4SZNdLJdD1T0NsequOn1jiKQQSb/eQXggZvN39XQpR0NbQN64M0ikt5es\n +vjGXB1iuL1iJUKSo4M+oAHd3iT21n0f1G47TciK8DvRubgfLHSnENKl+\n NB5E/BioPr5ESQAPXPAf4fisw/YQ4UXtiOpKdaQ3E/mRsVgpPWWJB5tKJ g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10623\"; a=\"418153035\"", "E=Sophos;i=\"5.97,304,1669104000\"; d=\"scan'208\";a=\"418153035\"", "E=McAfee;i=\"6500,9779,10623\"; a=\"670458672\"", "E=Sophos;i=\"5.97,304,1669104000\"; d=\"scan'208\";a=\"670458672\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, xiaoyun.li@intel.com, helin.zhang@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>, Rushil Gupta <rushilg@google.com>,\n Jordan Kimbrough <jrkim@google.com>, Jeroen de Borst <jeroendb@google.com>", "Subject": "[RFC v3 04/10] net/gve: support queue release and stop for DQO", "Date": "Fri, 17 Feb 2023 15:32:22 +0800", "Message-Id": "<20230217073228.340815-5-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230217073228.340815-1-junfeng.guo@intel.com>", "References": "<20230130062642.3337239-1-junfeng.guo@intel.com>\n <20230217073228.340815-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for queue operations:\n - gve_tx_queue_release_dqo\n - gve_rx_queue_release_dqo\n - gve_stop_tx_queues_dqo\n - gve_stop_rx_queues_dqo\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Jordan Kimbrough <jrkim@google.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.c | 18 +++++++++---\n drivers/net/gve/gve_ethdev.h | 12 ++++++++\n drivers/net/gve/gve_rx.c | 5 +++-\n drivers/net/gve/gve_rx_dqo.c | 57 ++++++++++++++++++++++++++++++++++++\n drivers/net/gve/gve_tx.c | 5 +++-\n drivers/net/gve/gve_tx_dqo.c | 55 ++++++++++++++++++++++++++++++++++\n 6 files changed, 146 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex 413696890f..efa121ca4d 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -292,11 +292,19 @@ gve_dev_close(struct rte_eth_dev *dev)\n \t\t\tPMD_DRV_LOG(ERR, \"Failed to stop dev.\");\n \t}\n \n-\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n-\t\tgve_tx_queue_release(dev, i);\n+\tif (gve_is_gqi(priv)) {\n+\t\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n+\t\t\tgve_tx_queue_release(dev, i);\n+\n+\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\t\t\tgve_rx_queue_release(dev, i);\n+\t} else {\n+\t\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n+\t\t\tgve_tx_queue_release_dqo(dev, i);\n \n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n-\t\tgve_rx_queue_release(dev, i);\n+\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\t\t\tgve_rx_queue_release_dqo(dev, i);\n+\t}\n \n \tgve_free_qpls(priv);\n \trte_free(priv->adminq);\n@@ -470,6 +478,8 @@ static const struct eth_dev_ops gve_eth_dev_ops_dqo = {\n \t.dev_infos_get = gve_dev_info_get,\n \t.rx_queue_setup = gve_rx_queue_setup_dqo,\n \t.tx_queue_setup = gve_tx_queue_setup_dqo,\n+\t.rx_queue_release = gve_rx_queue_release_dqo,\n+\t.tx_queue_release = gve_tx_queue_release_dqo,\n \t.link_update = gve_link_update,\n \t.mtu_set = gve_dev_mtu_set,\n };\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex c4e5b8cb43..5cc57afdb9 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -364,4 +364,16 @@ gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n \t\t uint16_t nb_desc, unsigned int socket_id,\n \t\t const struct rte_eth_txconf *conf);\n \n+void\n+gve_tx_queue_release_dqo(struct rte_eth_dev *dev, uint16_t qid);\n+\n+void\n+gve_rx_queue_release_dqo(struct rte_eth_dev *dev, uint16_t qid);\n+\n+void\n+gve_stop_tx_queues_dqo(struct rte_eth_dev *dev);\n+\n+void\n+gve_stop_rx_queues_dqo(struct rte_eth_dev *dev);\n+\n #endif /* _GVE_ETHDEV_H_ */\ndiff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c\nindex 66fbcf3930..e264bcadad 100644\n--- a/drivers/net/gve/gve_rx.c\n+++ b/drivers/net/gve/gve_rx.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2022 Intel Corporation\n+ * Copyright(C) 2022-2023 Intel Corporation\n */\n \n #include \"gve_ethdev.h\"\n@@ -354,6 +354,9 @@ gve_stop_rx_queues(struct rte_eth_dev *dev)\n \tuint16_t i;\n \tint err;\n \n+\tif (!gve_is_gqi(hw))\n+\t\treturn gve_stop_rx_queues_dqo(dev);\n+\n \terr = gve_adminq_destroy_rx_queues(hw, dev->data->nb_rx_queues);\n \tif (err != 0)\n \t\tPMD_DRV_LOG(WARNING, \"failed to destroy rxqs\");\ndiff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c\nindex 9c412c1481..8236cd7b50 100644\n--- a/drivers/net/gve/gve_rx_dqo.c\n+++ b/drivers/net/gve/gve_rx_dqo.c\n@@ -5,6 +5,38 @@\n #include \"gve_ethdev.h\"\n #include \"base/gve_adminq.h\"\n \n+static inline void\n+gve_release_rxq_mbufs_dqo(struct gve_rx_queue *rxq)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\tif (rxq->sw_ring[i]) {\n+\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i]);\n+\t\t\trxq->sw_ring[i] = NULL;\n+\t\t}\n+\t}\n+\n+\trxq->nb_avail = rxq->nb_rx_desc;\n+}\n+\n+void\n+gve_rx_queue_release_dqo(struct rte_eth_dev *dev, uint16_t qid)\n+{\n+\tstruct gve_rx_queue *q = dev->data->rx_queues[qid];\n+\n+\tif (q == NULL)\n+\t\treturn;\n+\n+\tgve_release_rxq_mbufs_dqo(q);\n+\trte_free(q->sw_ring);\n+\trte_memzone_free(q->compl_ring_mz);\n+\trte_memzone_free(q->mz);\n+\trte_memzone_free(q->qres_mz);\n+\tq->qres = NULL;\n+\trte_free(q);\n+}\n+\n static void\n gve_reset_rxq_dqo(struct gve_rx_queue *rxq)\n {\n@@ -54,6 +86,12 @@ gve_rx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n \t}\n \tnb_desc = hw->rx_desc_cnt;\n \n+\t/* Free memory if needed */\n+\tif (dev->data->rx_queues[queue_id]) {\n+\t\tgve_rx_queue_release_dqo(dev, queue_id);\n+\t\tdev->data->rx_queues[queue_id] = NULL;\n+\t}\n+\n \t/* Allocate the RX queue data structure. */\n \trxq = rte_zmalloc_socket(\"gve rxq\",\n \t\t\t\t sizeof(struct gve_rx_queue),\n@@ -152,3 +190,22 @@ gve_rx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n \trte_free(rxq);\n \treturn err;\n }\n+\n+void\n+gve_stop_rx_queues_dqo(struct rte_eth_dev *dev)\n+{\n+\tstruct gve_priv *hw = dev->data->dev_private;\n+\tstruct gve_rx_queue *rxq;\n+\tuint16_t i;\n+\tint err;\n+\n+\terr = gve_adminq_destroy_rx_queues(hw, dev->data->nb_rx_queues);\n+\tif (err != 0)\n+\t\tPMD_DRV_LOG(WARNING, \"failed to destroy rxqs\");\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\trxq = dev->data->rx_queues[i];\n+\t\tgve_release_rxq_mbufs_dqo(rxq);\n+\t\tgve_reset_rxq_dqo(rxq);\n+\t}\n+}\ndiff --git a/drivers/net/gve/gve_tx.c b/drivers/net/gve/gve_tx.c\nindex 9b41c59358..86f558d7a0 100644\n--- a/drivers/net/gve/gve_tx.c\n+++ b/drivers/net/gve/gve_tx.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2022 Intel Corporation\n+ * Copyright(C) 2022-2023 Intel Corporation\n */\n \n #include \"gve_ethdev.h\"\n@@ -671,6 +671,9 @@ gve_stop_tx_queues(struct rte_eth_dev *dev)\n \tuint16_t i;\n \tint err;\n \n+\tif (!gve_is_gqi(hw))\n+\t\treturn gve_stop_tx_queues_dqo(dev);\n+\n \terr = gve_adminq_destroy_tx_queues(hw, dev->data->nb_tx_queues);\n \tif (err != 0)\n \t\tPMD_DRV_LOG(WARNING, \"failed to destroy txqs\");\ndiff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c\nindex acf4ee2952..34f131cd7e 100644\n--- a/drivers/net/gve/gve_tx_dqo.c\n+++ b/drivers/net/gve/gve_tx_dqo.c\n@@ -5,6 +5,36 @@\n #include \"gve_ethdev.h\"\n #include \"base/gve_adminq.h\"\n \n+static inline void\n+gve_release_txq_mbufs_dqo(struct gve_tx_queue *txq)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < txq->sw_size; i++) {\n+\t\tif (txq->sw_ring[i]) {\n+\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i]);\n+\t\t\ttxq->sw_ring[i] = NULL;\n+\t\t}\n+\t}\n+}\n+\n+void\n+gve_tx_queue_release_dqo(struct rte_eth_dev *dev, uint16_t qid)\n+{\n+\tstruct gve_tx_queue *q = dev->data->tx_queues[qid];\n+\n+\tif (q == NULL)\n+\t\treturn;\n+\n+\tgve_release_txq_mbufs_dqo(q);\n+\trte_free(q->sw_ring);\n+\trte_memzone_free(q->mz);\n+\trte_memzone_free(q->compl_ring_mz);\n+\trte_memzone_free(q->qres_mz);\n+\tq->qres = NULL;\n+\trte_free(q);\n+}\n+\n static int\n check_tx_thresh_dqo(uint16_t nb_desc, uint16_t tx_rs_thresh,\n \t\t uint16_t tx_free_thresh)\n@@ -90,6 +120,12 @@ gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n \t}\n \tnb_desc = hw->tx_desc_cnt;\n \n+\t/* Free memory if needed. */\n+\tif (dev->data->tx_queues[queue_id]) {\n+\t\tgve_tx_queue_release_dqo(dev, queue_id);\n+\t\tdev->data->tx_queues[queue_id] = NULL;\n+\t}\n+\n \t/* Allocate the TX queue data structure. */\n \ttxq = rte_zmalloc_socket(\"gve txq\",\n \t\t\t\t sizeof(struct gve_tx_queue),\n@@ -182,3 +218,22 @@ gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,\n \trte_free(txq);\n \treturn err;\n }\n+\n+void\n+gve_stop_tx_queues_dqo(struct rte_eth_dev *dev)\n+{\n+\tstruct gve_priv *hw = dev->data->dev_private;\n+\tstruct gve_tx_queue *txq;\n+\tuint16_t i;\n+\tint err;\n+\n+\terr = gve_adminq_destroy_tx_queues(hw, dev->data->nb_tx_queues);\n+\tif (err != 0)\n+\t\tPMD_DRV_LOG(WARNING, \"failed to destroy txqs\");\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\t\tgve_release_txq_mbufs_dqo(txq);\n+\t\tgve_reset_txq_dqo(txq);\n+\t}\n+}\n", "prefixes": [ "RFC", "v3", "04/10" ] }