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GET /api/patches/124115/?format=api
{ "id": 124115, "url": "http://patchwork.dpdk.org/api/patches/124115/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230217073228.340815-9-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230217073228.340815-9-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230217073228.340815-9-junfeng.guo@intel.com", "date": "2023-02-17T07:32:26", "name": "[RFC,v3,08/10] net/gve: enable Tx checksum offload for DQO", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "908d9941e2ff8f27d280ec7cb860ecf8f1b33490", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230217073228.340815-9-junfeng.guo@intel.com/mbox/", "series": [ { "id": 27056, "url": "http://patchwork.dpdk.org/api/series/27056/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27056", "date": "2023-02-17T07:32:18", "name": "gve PMD enhancement", "version": 3, "mbox": "http://patchwork.dpdk.org/series/27056/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/124115/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/124115/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E4CDE41CBC;\n\tFri, 17 Feb 2023 08:39:49 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DB55C42D42;\n\tFri, 17 Feb 2023 08:39:27 +0100 (CET)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 1D09242D40\n for <dev@dpdk.org>; Fri, 17 Feb 2023 08:39:25 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Feb 2023 23:39:25 -0800", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by orsmga002.jf.intel.com with ESMTP; 16 Feb 2023 23:39:22 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1676619566; x=1708155566;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=OCFVDbREgwN0+T6KO01XQZsgsJb6U4qkLyfIevwCb6w=;\n b=Szec/tPrpiAQFwsSpfFh8bPvD4mSiLeQ1gPG02moF9/kLwpzYW0Kmd51\n yEFJoZtAD8JKJ3S3efL+3DYTTZNpsPpKajiLnahpyOX2OWlZAVYaOpfjC\n l4KcLYQ6I2ZiMlgimFFNPS4cHPhUyojjwjoofkHHcj4fbRuvSdg2an4cP\n cQy2M9Qia/WgT3ElQhbCBkt7/xmKhBkM6eDTlgZBFkn4mQ3i6Agi+DiR5\n 0Wjv0hFagbKOz/hB+h2dXn2i+3vqcU0klBF+a0tlhTVmeEO9+KAqiLp5L\n eZ/o1mOY1ezJvYh19c2W//zW4dTxZuPySdWjhc3gjqenmeCCFSF75Nwjb g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10623\"; a=\"418153103\"", "E=Sophos;i=\"5.97,304,1669104000\"; d=\"scan'208\";a=\"418153103\"", "E=McAfee;i=\"6500,9779,10623\"; a=\"670458728\"", "E=Sophos;i=\"5.97,304,1669104000\"; d=\"scan'208\";a=\"670458728\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, xiaoyun.li@intel.com, helin.zhang@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>, Rushil Gupta <rushilg@google.com>,\n Jordan Kimbrough <jrkim@google.com>, Jeroen de Borst <jeroendb@google.com>", "Subject": "[RFC v3 08/10] net/gve: enable Tx checksum offload for DQO", "Date": "Fri, 17 Feb 2023 15:32:26 +0800", "Message-Id": "<20230217073228.340815-9-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230217073228.340815-1-junfeng.guo@intel.com>", "References": "<20230130062642.3337239-1-junfeng.guo@intel.com>\n <20230217073228.340815-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enable Tx checksum offload once any flag of L4 checksum is set.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Jordan Kimbrough <jrkim@google.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.h | 4 ++++\n drivers/net/gve/gve_tx_dqo.c | 5 +++++\n 2 files changed, 9 insertions(+)", "diff": "diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex a8e0dd5f3d..bca6e86ef0 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -38,6 +38,10 @@\n #define GVE_MAX_MTU\tRTE_ETHER_MTU\n #define GVE_MIN_MTU\tRTE_ETHER_MIN_MTU\n \n+#define GVE_TX_CKSUM_OFFLOAD_MASK (\t\t\\\n+\t\tRTE_MBUF_F_TX_L4_MASK |\t\\\n+\t\tRTE_MBUF_F_TX_TCP_SEG)\n+\n /* A list of pages registered with the device during setup and used by a queue\n * as buffers\n */\ndiff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c\nindex 450cf71a6b..e925d6c3d0 100644\n--- a/drivers/net/gve/gve_tx_dqo.c\n+++ b/drivers/net/gve/gve_tx_dqo.c\n@@ -77,6 +77,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \tuint16_t mask, sw_mask;\n \tuint16_t nb_to_clean;\n \tuint16_t nb_tx = 0;\n+\tuint64_t ol_flags;\n \tuint16_t nb_used;\n \tuint16_t tx_id;\n \tuint16_t sw_id;\n@@ -103,6 +104,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\tif (txq->nb_free < tx_pkt->nb_segs)\n \t\t\tbreak;\n \n+\t\tol_flags = tx_pkt->ol_flags;\n \t\tnb_used = tx_pkt->nb_segs;\n \n \t\tdo {\n@@ -127,6 +129,9 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\t/* fill the last descriptor with End of Packet (EOP) bit */\n \t\ttxd->pkt.end_of_packet = 1;\n \n+\t\tif (ol_flags & GVE_TX_CKSUM_OFFLOAD_MASK)\n+\t\t\ttxd->pkt.checksum_offload_enable = 1;\n+\n \t\ttxq->nb_free -= nb_used;\n \t\ttxq->nb_used += nb_used;\n \t}\n", "prefixes": [ "RFC", "v3", "08/10" ] }