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GET /api/patches/124707/?format=api
{ "id": 124707, "url": "http://patchwork.dpdk.org/api/patches/124707/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230302212057.1114863-18-mingxia.liu@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230302212057.1114863-18-mingxia.liu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230302212057.1114863-18-mingxia.liu@intel.com", "date": "2023-03-02T21:20:53", "name": "[v9,17/21] net/cpfl: add AVX512 data path for split queue model", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "92f4258c8f9057c14c102f24bde20d743558d4a5", "submitter": { "id": 2514, "url": "http://patchwork.dpdk.org/api/people/2514/?format=api", "name": "Liu, Mingxia", "email": "mingxia.liu@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230302212057.1114863-18-mingxia.liu@intel.com/mbox/", "series": [ { "id": 27228, "url": "http://patchwork.dpdk.org/api/series/27228/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27228", "date": "2023-03-02T21:20:36", "name": "add support for cpfl PMD in DPDK", "version": 9, "mbox": "http://patchwork.dpdk.org/series/27228/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/124707/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/124707/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2FB2641DB5;\n\tThu, 2 Mar 2023 14:08:07 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7B83542D86;\n\tThu, 2 Mar 2023 14:06:34 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 8226A42D70\n for <dev@dpdk.org>; Thu, 2 Mar 2023 14:06:33 +0100 (CET)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Mar 2023 05:06:33 -0800", "from dpdk-mingxial-ice.sh.intel.com ([10.67.110.191])\n by orsmga001.jf.intel.com with ESMTP; 02 Mar 2023 05:06:31 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1677762393; x=1709298393;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=87jFX2p1iNfiMe47xpLc8AOwT8EjKAe++C9bUMyhBmM=;\n b=B0CwmAjxPxlb3Ot+063o20+pgmbcz2nZbnZTOpKO8R1UCr9XeV8crRMa\n 8hyNYTdDfYjDo84Ui/bLva9yMBU2nfGvMYy4pYJSFFG0amQp1FogWl6NF\n AGL7LKHGurlgOynO/dE5nw45OWopUwJlBVF/8AfVOl92Y08UWO6hIzoSh\n R9Aw0u3Wda4A1BsCYJS7hxiL3QQI7678LFp1E1tnz1Jk3WMDAb9l8b+Y1\n hOkBUG3ZXVCRkRCxd0CZBkcBxMRrRcZKTgwGf4YEQtmt8LovLdfuQ62lo\n AWYV/qx/78DkSp5Dm4s2zEzRzOjqOZT6CVlaOBTsei0bc3/5Hbe7HeZcE g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10636\"; a=\"322988324\"", "E=Sophos;i=\"5.98,227,1673942400\"; d=\"scan'208\";a=\"322988324\"", "E=McAfee;i=\"6500,9779,10636\"; a=\"707406445\"", "E=Sophos;i=\"5.98,227,1673942400\"; d=\"scan'208\";a=\"707406445\"" ], "X-ExtLoop1": "1", "From": "Mingxia Liu <mingxia.liu@intel.com>", "To": "dev@dpdk.org,\n\tbeilei.xing@intel.com,\n\tyuying.zhang@intel.com", "Cc": "Mingxia Liu <mingxia.liu@intel.com>,\n\tWenjun Wu <wenjun1.wu@intel.com>", "Subject": "[PATCH v9 17/21] net/cpfl: add AVX512 data path for split queue model", "Date": "Thu, 2 Mar 2023 21:20:53 +0000", "Message-Id": "<20230302212057.1114863-18-mingxia.liu@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230302212057.1114863-1-mingxia.liu@intel.com>", "References": "<20230302103527.931071-1-mingxia.liu@intel.com>\n <20230302212057.1114863-1-mingxia.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support of AVX512 data path for split queue model.\n\nSigned-off-by: Wenjun Wu <wenjun1.wu@intel.com>\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\n---\n drivers/net/cpfl/cpfl_rxtx.c | 56 +++++++++++++++++++++++--\n drivers/net/cpfl/cpfl_rxtx_vec_common.h | 20 ++++++++-\n drivers/net/cpfl/meson.build | 6 ++-\n 3 files changed, 75 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex ea28d3978c..dac95579f5 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -758,7 +758,8 @@ cpfl_set_rx_function(struct rte_eth_dev *dev)\n \t\tif (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)\n #ifdef CC_AVX512_SUPPORT\n \t\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&\n-\t\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)\n+\t\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&\n+\t\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512DQ))\n \t\t\t\tvport->rx_use_avx512 = true;\n #else\n \t\tPMD_DRV_LOG(NOTICE,\n@@ -771,6 +772,21 @@ cpfl_set_rx_function(struct rte_eth_dev *dev)\n \n #ifdef RTE_ARCH_X86\n \tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\tif (vport->rx_vec_allowed) {\n+\t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\t\t\trxq = dev->data->rx_queues[i];\n+\t\t\t\t(void)idpf_qc_splitq_rx_vec_setup(rxq);\n+\t\t\t}\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\tif (vport->rx_use_avx512) {\n+\t\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\t \"Using Split AVX512 Vector Rx (port %d).\",\n+\t\t\t\t\t dev->data->port_id);\n+\t\t\t\tdev->rx_pkt_burst = idpf_dp_splitq_recv_pkts_avx512;\n+\t\t\t\treturn;\n+\t\t\t}\n+#endif /* CC_AVX512_SUPPORT */\n+\t\t}\n \t\tPMD_DRV_LOG(NOTICE,\n \t\t\t \"Using Split Scalar Rx (port %d).\",\n \t\t\t dev->data->port_id);\n@@ -826,9 +842,17 @@ cpfl_set_tx_function(struct rte_eth_dev *dev)\n \t\tvport->tx_vec_allowed = true;\n \t\tif (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)\n #ifdef CC_AVX512_SUPPORT\n+\t\t{\n \t\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&\n \t\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)\n \t\t\t\tvport->tx_use_avx512 = true;\n+\t\t\tif (vport->tx_use_avx512) {\n+\t\t\t\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\t\t\t\ttxq = dev->data->tx_queues[i];\n+\t\t\t\t\tidpf_qc_tx_vec_avx512_setup(txq);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n #else\n \t\tPMD_DRV_LOG(NOTICE,\n \t\t\t \"AVX512 is not supported in build env\");\n@@ -838,14 +862,26 @@ cpfl_set_tx_function(struct rte_eth_dev *dev)\n \t}\n #endif /* RTE_ARCH_X86 */\n \n+#ifdef RTE_ARCH_X86\n \tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\tif (vport->tx_vec_allowed) {\n+#ifdef CC_AVX512_SUPPORT\n+\t\t\tif (vport->tx_use_avx512) {\n+\t\t\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t\t\t \"Using Split AVX512 Vector Tx (port %d).\",\n+\t\t\t\t\t dev->data->port_id);\n+\t\t\t\tdev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts_avx512;\n+\t\t\t\tdev->tx_pkt_prepare = idpf_dp_prep_pkts;\n+\t\t\t\treturn;\n+\t\t\t}\n+#endif /* CC_AVX512_SUPPORT */\n+\t\t}\n \t\tPMD_DRV_LOG(NOTICE,\n \t\t\t \"Using Split Scalar Tx (port %d).\",\n \t\t\t dev->data->port_id);\n \t\tdev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts;\n \t\tdev->tx_pkt_prepare = idpf_dp_prep_pkts;\n \t} else {\n-#ifdef RTE_ARCH_X86\n \t\tif (vport->tx_vec_allowed) {\n #ifdef CC_AVX512_SUPPORT\n \t\t\tif (vport->tx_use_avx512) {\n@@ -864,11 +900,25 @@ cpfl_set_tx_function(struct rte_eth_dev *dev)\n \t\t\t}\n #endif /* CC_AVX512_SUPPORT */\n \t\t}\n-#endif /* RTE_ARCH_X86 */\n \t\tPMD_DRV_LOG(NOTICE,\n \t\t\t \"Using Single Scalar Tx (port %d).\",\n \t\t\t dev->data->port_id);\n \t\tdev->tx_pkt_burst = idpf_dp_singleq_xmit_pkts;\n \t\tdev->tx_pkt_prepare = idpf_dp_prep_pkts;\n \t}\n+#else\n+\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t \"Using Split Scalar Tx (port %d).\",\n+\t\t\t dev->data->port_id);\n+\t\tdev->tx_pkt_burst = idpf_dp_splitq_xmit_pkts;\n+\t\tdev->tx_pkt_prepare = idpf_dp_prep_pkts;\n+\t} else {\n+\t\tPMD_DRV_LOG(NOTICE,\n+\t\t\t \"Using Single Scalar Tx (port %d).\",\n+\t\t\t dev->data->port_id);\n+\t\tdev->tx_pkt_burst = idpf_dp_singleq_xmit_pkts;\n+\t\tdev->tx_pkt_prepare = idpf_dp_prep_pkts;\n+\t}\n+#endif /* RTE_ARCH_X86 */\n }\ndiff --git a/drivers/net/cpfl/cpfl_rxtx_vec_common.h b/drivers/net/cpfl/cpfl_rxtx_vec_common.h\nindex 2d4c6a0ef3..665418d27d 100644\n--- a/drivers/net/cpfl/cpfl_rxtx_vec_common.h\n+++ b/drivers/net/cpfl/cpfl_rxtx_vec_common.h\n@@ -64,15 +64,31 @@ cpfl_tx_vec_queue_default(struct idpf_tx_queue *txq)\n \treturn CPFL_VECTOR_PATH;\n }\n \n+static inline int\n+cpfl_rx_splitq_vec_default(struct idpf_rx_queue *rxq)\n+{\n+\tif (rxq->bufq2->rx_buf_len < rxq->max_pkt_len)\n+\t\treturn CPFL_SCALAR_PATH;\n+\n+\treturn CPFL_VECTOR_PATH;\n+}\n+\n static inline int\n cpfl_rx_vec_dev_check_default(struct rte_eth_dev *dev)\n {\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n \tstruct idpf_rx_queue *rxq;\n-\tint i, ret = 0;\n+\tint i, default_ret, splitq_ret, ret = CPFL_SCALAR_PATH;\n \n \tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\trxq = dev->data->rx_queues[i];\n-\t\tret = (cpfl_rx_vec_queue_default(rxq));\n+\t\tdefault_ret = cpfl_rx_vec_queue_default(rxq);\n+\t\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT) {\n+\t\t\tsplitq_ret = cpfl_rx_splitq_vec_default(rxq);\n+\t\t\tret = splitq_ret && default_ret;\n+\t\t} else {\n+\t\t\tret = default_ret;\n+\t\t}\n \t\tif (ret == CPFL_SCALAR_PATH)\n \t\t\treturn CPFL_SCALAR_PATH;\n \t}\ndiff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build\nindex fbe6500826..2cf69258e2 100644\n--- a/drivers/net/cpfl/meson.build\n+++ b/drivers/net/cpfl/meson.build\n@@ -23,13 +23,15 @@ sources = files(\n if arch_subdir == 'x86'\n cpfl_avx512_cpu_support = (\n cc.get_define('__AVX512F__', args: machine_args) != '' and\n- cc.get_define('__AVX512BW__', args: machine_args) != ''\n+ cc.get_define('__AVX512BW__', args: machine_args) != '' and\n+ cc.get_define('__AVX512DQ__', args: machine_args) != ''\n )\n \n cpfl_avx512_cc_support = (\n not machine_args.contains('-mno-avx512f') and\n cc.has_argument('-mavx512f') and\n- cc.has_argument('-mavx512bw')\n+ cc.has_argument('-mavx512bw') and\n+ cc.has_argument('-mavx512dq')\n )\n \n if cpfl_avx512_cpu_support == true or cpfl_avx512_cc_support == true\n", "prefixes": [ "v9", "17/21" ] }