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GET /api/patches/124763/?format=api
{ "id": 124763, "url": "http://patchwork.dpdk.org/api/patches/124763/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230303081013.589868-6-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230303081013.589868-6-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230303081013.589868-6-ndabilpuram@marvell.com", "date": "2023-03-03T08:10:04", "name": "[06/15] common/cnxk: remove flow control config at queue setup", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fe102b5d2a9249b2a90f5e64e787c6b94033fbc0", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230303081013.589868-6-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 27237, "url": "http://patchwork.dpdk.org/api/series/27237/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27237", "date": "2023-03-03T08:09:59", "name": "[01/15] net/cnxk: resolve sefgault caused during transmit completion", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27237/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/124763/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/124763/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AC7A941DC3;\n\tFri, 3 Mar 2023 09:11:27 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DA22042D0C;\n\tFri, 3 Mar 2023 09:11:08 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id D7FDE42C76\n for <dev@dpdk.org>; Fri, 3 Mar 2023 09:11:07 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3236NeCJ006795 for <dev@dpdk.org>; Fri, 3 Mar 2023 00:11:07 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p1wr9xbj8-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 03 Mar 2023 00:11:07 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Fri, 3 Mar 2023 00:11:04 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Fri, 3 Mar 2023 00:11:04 -0800", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 735883F70BF;\n Fri, 3 Mar 2023 00:11:01 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=2DC5Jk50Jcm9GxEY0MMnOUWc8jphhkZ+jWRLNiUVAGU=;\n b=dX1iLb59bIfs/vcm6MGM2hvyh9FZMCOGrWR3LFm5/+KAjE6p5n61RJHqnuTBBAKuVO4W\n 1qvIIIie/s0FuOOZuO/1k1TIy9Nr2/bJvoY2Ytay2kDZIwJgfF8FR6GBOj4x+gBHBpWD\n 3UljGowkV4cxkEH2EzyamM9Lf3M9zzd33fAZsCNUIXC76+S/evb4c/JGBCdZfkMIMm7d\n rgsXoS91TgcXzS6ufIw7tzbGwtJn6zfnkqPrMxdQK5YIzYNEZMYrSolxp6BjEpjLgNIk\n ijyBCtRw2VkOF0SMCih1CedSts9WYHUa3lkwn3oqYVJpFLQq7gaupWzmh7fJwg8vr2ih 2Q==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 06/15] common/cnxk: remove flow control config at queue setup", "Date": "Fri, 3 Mar 2023 13:40:04 +0530", "Message-ID": "<20230303081013.589868-6-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230303081013.589868-1-ndabilpuram@marvell.com>", "References": "<20230303081013.589868-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "kYO9zHO1BbZxT6fpwG0VAAZhL2VjBhit", "X-Proofpoint-GUID": "kYO9zHO1BbZxT6fpwG0VAAZhL2VjBhit", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-03-03_01,2023-03-02_02,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Remove flow control default enable/disable from queue setup time\nand move it to explicit per queue setup after device is configured\nand as part of device start.\n\nAlso remove TM node ref count for flow control to avoid\nref count mismatch. For user tree, on user disabling flow control\nor PFC on one SQ would clear the config from corresponding TM node\nimmediately irrespective of other SQ connections.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix.c | 18 +++---\n drivers/common/cnxk/roc_nix.h | 1 +\n drivers/common/cnxk/roc_nix_debug.c | 2 +\n drivers/common/cnxk/roc_nix_fc.c | 67 +++++++--------------\n drivers/common/cnxk/roc_nix_priv.h | 7 ++-\n drivers/common/cnxk/roc_nix_queue.c | 14 ++---\n drivers/common/cnxk/roc_nix_tm.c | 81 +++++++++++---------------\n drivers/common/cnxk/roc_nix_tm_ops.c | 2 +-\n drivers/common/cnxk/roc_nix_tm_utils.c | 14 +----\n 9 files changed, 82 insertions(+), 124 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex fbf318a77d..97ef1c7133 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -214,6 +214,13 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,\n \tnix->tx_link = rsp->tx_link;\n \tnix->nb_rx_queues = nb_rxq;\n \tnix->nb_tx_queues = nb_txq;\n+\n+\tnix->rqs = plt_zmalloc(sizeof(struct roc_nix_rq *) * nb_rxq, 0);\n+\tif (!nix->rqs) {\n+\t\trc = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+\n \tnix->sqs = plt_zmalloc(sizeof(struct roc_nix_sq *) * nb_txq, 0);\n \tif (!nix->sqs) {\n \t\trc = -ENOMEM;\n@@ -235,7 +242,9 @@ roc_nix_lf_free(struct roc_nix *roc_nix)\n \tstruct ndc_sync_op *ndc_req;\n \tint rc = -ENOSPC;\n \n+\tplt_free(nix->rqs);\n \tplt_free(nix->sqs);\n+\tnix->rqs = NULL;\n \tnix->sqs = NULL;\n \n \t/* Sync NDC-NIX for LF */\n@@ -456,15 +465,6 @@ roc_nix_dev_init(struct roc_nix *roc_nix)\n \tnix->reta_sz = reta_sz;\n \tnix->mtu = ROC_NIX_DEFAULT_HW_FRS;\n \n-\t/* Always start with full FC for LBK */\n-\tif (nix->lbk_link) {\n-\t\tnix->rx_pause = 1;\n-\t\tnix->tx_pause = 1;\n-\t} else if (!roc_nix_is_vf_or_sdp(roc_nix)) {\n-\t\t/* Get the current state of flow control */\n-\t\troc_nix_fc_mode_get(roc_nix);\n-\t}\n-\n \t/* Register error and ras interrupts */\n \trc = nix_register_irqs(nix);\n \tif (rc)\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 96756b1a2b..f04dd63e27 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -328,6 +328,7 @@ struct roc_nix_rq {\n \tstruct roc_nix *roc_nix;\n \tuint64_t meta_aura_handle;\n \tuint16_t inl_dev_refs;\n+\tuint8_t tc;\n };\n \n struct roc_nix_cq {\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 2f8c595bd9..97d86f9a97 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -879,6 +879,7 @@ roc_nix_rq_dump(struct roc_nix_rq *rq, FILE *file)\n \tnix_dump(file, \" vwqe_aura_handle = %ld\", rq->vwqe_aura_handle);\n \tnix_dump(file, \" roc_nix = %p\", rq->roc_nix);\n \tnix_dump(file, \" inl_dev_refs = %d\", rq->inl_dev_refs);\n+\tnix_dump(file, \" tc = %d\", rq->tc);\n }\n \n void\n@@ -911,6 +912,7 @@ roc_nix_sq_dump(struct roc_nix_sq *sq, FILE *file)\n \tnix_dump(file, \" lmt_addr = %p\", sq->lmt_addr);\n \tnix_dump(file, \" sqe_mem = %p\", sq->sqe_mem);\n \tnix_dump(file, \" fc = %p\", sq->fc);\n+\tnix_dump(file, \" tc = %d\", sq->tc);\n };\n \n static uint8_t\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex 784e6e5416..39c16995cd 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -278,9 +278,12 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n static int\n nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct roc_nix_fc_cfg tmp;\n-\tint sso_ena = 0;\n+\tstruct roc_nix_rq *rq;\n+\tint sso_ena = 0, rc;\n \n+\trq = nix->rqs[fc_cfg->rq_cfg.rq];\n \t/* Check whether RQ is connected to SSO or not */\n \tsso_ena = roc_nix_rq_is_sso_enable(roc_nix, fc_cfg->rq_cfg.rq);\n \tif (sso_ena < 0)\n@@ -299,7 +302,14 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \ttmp.cq_cfg.cq_drop = fc_cfg->rq_cfg.cq_drop;\n \ttmp.cq_cfg.enable = fc_cfg->rq_cfg.enable;\n \n-\treturn nix_fc_cq_config_set(roc_nix, &tmp);\n+\trc = nix_fc_cq_config_set(roc_nix, &tmp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trq->tc = fc_cfg->rq_cfg.enable ? fc_cfg->rq_cfg.tc : ROC_NIX_PFC_CLASS_INVALID;\n+\tplt_nix_dbg(\"RQ %u: TC %u %s\", fc_cfg->rq_cfg.rq, fc_cfg->rq_cfg.tc,\n+\t\t fc_cfg->rq_cfg.enable ? \"enabled\" : \"disabled\");\n+\treturn 0;\n }\n \n int\n@@ -334,7 +344,7 @@ roc_nix_fc_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \telse if (fc_cfg->type == ROC_NIX_FC_TM_CFG)\n \t\treturn nix_tm_bp_config_set(roc_nix, fc_cfg->tm_cfg.sq,\n \t\t\t\t\t fc_cfg->tm_cfg.tc,\n-\t\t\t\t\t fc_cfg->tm_cfg.enable, false);\n+\t\t\t\t\t fc_cfg->tm_cfg.enable);\n \n \treturn -EINVAL;\n }\n@@ -343,50 +353,17 @@ enum roc_nix_fc_mode\n roc_nix_fc_mode_get(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n-\tstruct dev *dev = &nix->dev;\n-\tstruct mbox *mbox = mbox_get(dev->mbox);\n-\tstruct cgx_pause_frm_cfg *req, *rsp;\n \tenum roc_nix_fc_mode mode;\n-\tint rc = -ENOSPC;\n \n-\t/* Flow control on LBK link is always available */\n-\tif (roc_nix_is_lbk(roc_nix)) {\n-\t\tif (nix->tx_pause && nix->rx_pause)\n-\t\t\trc = ROC_NIX_FC_FULL;\n-\t\telse if (nix->rx_pause)\n-\t\t\trc = ROC_NIX_FC_RX;\n-\t\telse if (nix->tx_pause)\n-\t\t\trc = ROC_NIX_FC_TX;\n-\t\telse\n-\t\t\trc = ROC_NIX_FC_NONE;\n-\t\tgoto exit;\n-\t}\n-\n-\treq = mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n-\tif (req == NULL)\n-\t\tgoto exit;\n-\treq->set = 0;\n-\n-\trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\tgoto exit;\n-\n-\tif (rsp->rx_pause && rsp->tx_pause)\n+\tif (nix->tx_pause && nix->rx_pause)\n \t\tmode = ROC_NIX_FC_FULL;\n-\telse if (rsp->rx_pause)\n+\telse if (nix->rx_pause)\n \t\tmode = ROC_NIX_FC_RX;\n-\telse if (rsp->tx_pause)\n+\telse if (nix->tx_pause)\n \t\tmode = ROC_NIX_FC_TX;\n \telse\n \t\tmode = ROC_NIX_FC_NONE;\n-\n-\tnix->rx_pause = rsp->rx_pause;\n-\tnix->tx_pause = rsp->tx_pause;\n-\trc = mode;\n-\n-exit:\n-\tmbox_put(mbox);\n-\treturn rc;\n+\treturn mode;\n }\n \n int\n@@ -570,8 +547,8 @@ roc_nix_pfc_mode_set(struct roc_nix *roc_nix, struct roc_nix_pfc_cfg *pfc_cfg)\n \tif (rc)\n \t\tgoto exit;\n \n-\tnix->rx_pause = rsp->rx_pause;\n-\tnix->tx_pause = rsp->tx_pause;\n+\tnix->pfc_rx_pause = rsp->rx_pause;\n+\tnix->pfc_tx_pause = rsp->tx_pause;\n \tif (rsp->tx_pause)\n \t\tnix->cev |= BIT(pfc_cfg->tc);\n \telse\n@@ -592,11 +569,11 @@ roc_nix_pfc_mode_get(struct roc_nix *roc_nix, struct roc_nix_pfc_cfg *pfc_cfg)\n \n \tpfc_cfg->tc = nix->cev;\n \n-\tif (nix->rx_pause && nix->tx_pause)\n+\tif (nix->pfc_rx_pause && nix->pfc_tx_pause)\n \t\tpfc_cfg->mode = ROC_NIX_FC_FULL;\n-\telse if (nix->rx_pause)\n+\telse if (nix->pfc_rx_pause)\n \t\tpfc_cfg->mode = ROC_NIX_FC_RX;\n-\telse if (nix->tx_pause)\n+\telse if (nix->pfc_tx_pause)\n \t\tpfc_cfg->mode = ROC_NIX_FC_TX;\n \telse\n \t\tpfc_cfg->mode = ROC_NIX_FC_NONE;\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 7d2e3626a3..2fe9093324 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -102,7 +102,6 @@ struct nix_tm_node {\n \t/* Last stats */\n \tuint64_t last_pkts;\n \tuint64_t last_bytes;\n-\tuint32_t tc_refcnt;\n };\n \n struct nix_tm_shaper_profile {\n@@ -131,6 +130,7 @@ struct nix {\n \tstruct nix_qint *cints_mem;\n \tuint8_t configured_qints;\n \tuint8_t configured_cints;\n+\tstruct roc_nix_rq **rqs;\n \tstruct roc_nix_sq **sqs;\n \tuint16_t vwqe_interval;\n \tuint16_t tx_chan_base;\n@@ -158,6 +158,8 @@ struct nix {\n \tuint16_t msixoff;\n \tuint8_t rx_pause;\n \tuint8_t tx_pause;\n+\tuint8_t pfc_rx_pause;\n+\tuint8_t pfc_tx_pause;\n \tuint16_t cev;\n \tuint64_t rx_cfg;\n \tstruct dev dev;\n@@ -407,7 +409,7 @@ int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable);\n int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled);\n int nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n-\t\t\t bool enable, bool force_flush);\n+\t\t\t bool enable);\n void nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval);\n int nix_tm_mark_init(struct nix *nix);\n void nix_tm_sq_free_sqe_buffer(uint64_t *sqe, int head_off, int end_off, int instr_sz);\n@@ -469,6 +471,7 @@ int nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints,\n \t\t\tuint16_t cints);\n int nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid,\n \t\t __io void **ctx_p);\n+uint8_t nix_tm_lbk_relchan_get(struct nix *nix);\n \n /*\n * Telemetry\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 009c024064..07ec1270d7 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -667,6 +667,7 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \t}\n \n \trq->roc_nix = roc_nix;\n+\trq->tc = ROC_NIX_PFC_CLASS_INVALID;\n \n \tif (is_cn9k)\n \t\trc = nix_rq_cn9k_cfg(dev, rq, nix->qints, false, ena);\n@@ -695,6 +696,7 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \t\t\treturn rc;\n \t}\n \n+\tnix->rqs[rq->qid] = rq;\n \treturn nix_tel_node_add_rq(rq);\n }\n \n@@ -718,6 +720,7 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \tnix_rq_aura_buf_type_update(rq, false);\n \n \trq->roc_nix = roc_nix;\n+\trq->tc = ROC_NIX_PFC_CLASS_INVALID;\n \n \tmbox = mbox_get(m_box);\n \tif (is_cn9k)\n@@ -779,6 +782,7 @@ roc_nix_rq_cman_config(struct roc_nix *roc_nix, struct roc_nix_rq *rq)\n int\n roc_nix_rq_fini(struct roc_nix_rq *rq)\n {\n+\tstruct nix *nix = roc_nix_to_nix_priv(rq->roc_nix);\n \tint rc;\n \n \t/* Disabling RQ is sufficient */\n@@ -788,6 +792,8 @@ roc_nix_rq_fini(struct roc_nix_rq *rq)\n \n \t/* Update aura attribute to indicate its use for */\n \tnix_rq_aura_buf_type_update(rq, false);\n+\n+\tnix->rqs[rq->qid] = NULL;\n \treturn 0;\n }\n \n@@ -895,14 +901,6 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \t\t}\n \t}\n \n-\t/* TX pause frames enable flow ctrl on RX side */\n-\tif (nix->tx_pause) {\n-\t\t/* Single BPID is allocated for all rx channels for now */\n-\t\tcq_ctx->bpid = nix->bpid[0];\n-\t\tcq_ctx->bp = cq->drop_thresh;\n-\t\tcq_ctx->bp_ena = 1;\n-\t}\n-\n \trc = mbox_process(mbox);\n \tmbox_put(mbox);\n \tif (rc)\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 6d470f424d..c104611355 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -101,7 +101,6 @@ nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree)\n {\n \tstruct nix_tm_node_list *list;\n \tstruct nix_tm_node *node;\n-\tbool skip_bp = false;\n \tuint32_t hw_lvl;\n \tint rc = 0;\n \n@@ -116,11 +115,8 @@ nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree)\n \t\t\t * set per channel only for PF or lbk vf.\n \t\t\t */\n \t\t\tnode->bp_capa = 0;\n-\t\t\tif (!nix->sdp_link && !skip_bp &&\n-\t\t\t node->hw_lvl == nix->tm_link_cfg_lvl) {\n+\t\t\tif (!nix->sdp_link && node->hw_lvl == nix->tm_link_cfg_lvl)\n \t\t\t\tnode->bp_capa = 1;\n-\t\t\t\tskip_bp = false;\n-\t\t\t}\n \n \t\t\trc = nix_tm_node_reg_conf(nix, node);\n \t\t\tif (rc)\n@@ -315,7 +311,7 @@ nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node)\n \n int\n nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n-\t\t bool enable, bool force_flush)\n+\t\t bool enable)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tenum roc_nix_tm_tree tree = nix->tm_tree;\n@@ -327,9 +323,10 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \tstruct nix_tm_node *parent;\n \tstruct nix_tm_node *node;\n \tstruct roc_nix_sq *sq_s;\n+\tuint16_t rel_chan = 0;\n \tuint8_t parent_lvl;\n \tuint8_t k = 0;\n-\tint rc = 0;\n+\tint rc = 0, i;\n \n \tsq_s = nix->sqs[sq];\n \tif (!sq_s)\n@@ -354,9 +351,17 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \n \tlist = nix_tm_node_list(nix, tree);\n \n+\t/* Get relative channel if loopback */\n+\tif (roc_nix_is_lbk(roc_nix))\n+\t\trel_chan = nix_tm_lbk_relchan_get(nix);\n+\telse\n+\t\trel_chan = tc;\n+\n \t/* Enable request, parent rel chan already configured */\n \tif (enable && parent->rel_chan != NIX_TM_CHAN_INVALID &&\n-\t parent->rel_chan != tc) {\n+\t parent->rel_chan != rel_chan) {\n+\t\tplt_err(\"SQ %d: parent node TL3 id %d already has rel_chan %d set\",\n+\t\t\tsq, parent->hw_id, parent->rel_chan);\n \t\trc = -EINVAL;\n \t\tgoto err;\n \t}\n@@ -378,36 +383,21 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \t\t\tcontinue;\n \n \t\t/* Restrict sharing of TL3 across the queues */\n-\t\tif (enable && node != parent && node->rel_chan == tc) {\n-\t\t\tplt_err(\"SQ %d node TL3 id %d already has %d tc value set\",\n-\t\t\t\tsq, node->hw_id, tc);\n-\t\t\treturn -EINVAL;\n+\t\tif (enable && node != parent && node->rel_chan == rel_chan) {\n+\t\t\tplt_warn(\"SQ %d: siblng node TL3 %d already has %d(%d) tc value set\",\n+\t\t\t\t sq, node->hw_id, tc, rel_chan);\n+\t\t\treturn -EEXIST;\n \t\t}\n \t}\n \n-\t/* In case of user tree i.e. multiple SQs may share a TL3, disabling PFC\n-\t * on one of such SQ should not hamper the traffic control on other SQs.\n-\t * Maitaining a reference count scheme to account no of SQs sharing the\n-\t * TL3 before disabling PFC on it.\n-\t */\n-\tif (!force_flush && !enable &&\n-\t parent->rel_chan != NIX_TM_CHAN_INVALID) {\n-\t\tif (sq_s->tc != ROC_NIX_PFC_CLASS_INVALID)\n-\t\t\tparent->tc_refcnt--;\n-\t\tif (parent->tc_refcnt > 0)\n-\t\t\treturn 0;\n-\t}\n+\t/* Allocating TL3 request */\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n+\treq->lvl = nix->tm_link_cfg_lvl;\n+\tk = 0;\n \n-\t/* Allocating TL3 resources */\n-\tif (!req) {\n-\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox));\n-\t\treq->lvl = nix->tm_link_cfg_lvl;\n-\t\tk = 0;\n-\t}\n-\n-\t/* Enable PFC on the identified TL3 */\n+\t/* Enable PFC/pause on the identified TL3 */\n \treq->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(parent->hw_id, link);\n-\treq->regval[k] = enable ? tc : 0;\n+\treq->regval[k] = enable ? rel_chan : 0;\n \treq->regval[k] |= enable ? BIT_ULL(13) : 0;\n \treq->regval_mask[k] = ~(BIT_ULL(13) | GENMASK_ULL(7, 0));\n \tk++;\n@@ -417,12 +407,17 @@ nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,\n \tif (rc)\n \t\tgoto err;\n \n-\tparent->rel_chan = enable ? tc : NIX_TM_CHAN_INVALID;\n-\t/* Increase reference count for parent TL3 */\n-\tif (enable && sq_s->tc == ROC_NIX_PFC_CLASS_INVALID)\n-\t\tparent->tc_refcnt++;\n+\tparent->rel_chan = enable ? rel_chan : NIX_TM_CHAN_INVALID;\n+\tsq_s->tc = enable ? tc : ROC_NIX_PFC_CLASS_INVALID;\n+\t/* Clear other SQ's with same TC i.e same parent node */\n+\tfor (i = 0; !enable && i < nix->nb_tx_queues; i++) {\n+\t\tif (nix->sqs[i] && nix->sqs[i]->tc == tc)\n+\t\t\tnix->sqs[i]->tc = ROC_NIX_PFC_CLASS_INVALID;\n+\t}\n \n \trc = 0;\n+\tplt_tm_dbg(\"SQ %u: TL3 %d TC %u %s\",\n+\t\t sq, parent->hw_id, tc, enable ? \"enabled\" : \"disabled\");\n \tgoto exit;\n err:\n \tplt_err(\"Failed to %s bp on link %u, rc=%d(%s)\",\n@@ -802,7 +797,7 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \t}\n \n \t/* Disable backpressure */\n-\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false, true);\n+\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false);\n \tif (rc) {\n \t\tplt_err(\"Failed to disable backpressure for flush, rc=%d\", rc);\n \t\treturn rc;\n@@ -942,16 +937,6 @@ nix_tm_sq_flush_post(struct roc_nix_sq *sq)\n \t\t}\n \t}\n \n-\tif (!nix->rx_pause)\n-\t\treturn 0;\n-\n-\t/* Restore backpressure */\n-\trc = nix_tm_bp_config_set(roc_nix, sq->qid, sq->tc, true, false);\n-\tif (rc) {\n-\t\tplt_err(\"Failed to restore backpressure, rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n \treturn 0;\n }\n \ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nindex 8fb65be9d4..4e88ad1beb 100644\n--- a/drivers/common/cnxk/roc_nix_tm_ops.c\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -481,7 +481,7 @@ roc_nix_tm_hierarchy_disable(struct roc_nix *roc_nix)\n \t\tif (!sq)\n \t\t\tcontinue;\n \n-\t\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false, false);\n+\t\trc = nix_tm_bp_config_set(roc_nix, sq->qid, 0, false);\n \t\tif (rc && rc != -ENOENT) {\n \t\t\tplt_err(\"Failed to disable backpressure, rc=%d\", rc);\n \t\t\tgoto cleanup;\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nindex a52b897713..a7ba2bf027 100644\n--- a/drivers/common/cnxk/roc_nix_tm_utils.c\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -72,8 +72,8 @@ nix_tm_lvl2nix(struct nix *nix, uint32_t lvl)\n \t\treturn nix_tm_lvl2nix_tl2_root(lvl);\n }\n \n-static uint8_t\n-nix_tm_relchan_get(struct nix *nix)\n+uint8_t\n+nix_tm_lbk_relchan_get(struct nix *nix)\n {\n \treturn nix->tx_chan_base & 0xff;\n }\n@@ -531,7 +531,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \t\tparent = node->parent->hw_id;\n \n \tlink = nix->tx_link;\n-\trelchan = nix_tm_relchan_get(nix);\n+\trelchan = roc_nix_is_lbk(roc_nix) ? nix_tm_lbk_relchan_get(nix) : 0;\n \n \tif (hw_lvl != NIX_TXSCH_LVL_SMQ)\n \t\tchild = nix_tm_find_prio_anchor(nix, node->id, tree);\n@@ -602,10 +602,6 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \t\t nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL3) {\n \t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n \t\t\tregval[k] = BIT_ULL(12) | relchan;\n-\t\t\t/* Enable BP if node is BP capable and rx_pause is set\n-\t\t\t */\n-\t\t\tif (nix->rx_pause && node->bp_capa)\n-\t\t\t\tregval[k] |= BIT_ULL(13);\n \t\t\tk++;\n \t\t}\n \n@@ -625,10 +621,6 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,\n \t\t nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL2) {\n \t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n \t\t\tregval[k] = BIT_ULL(12) | relchan;\n-\t\t\t/* Enable BP if node is BP capable and rx_pause is set\n-\t\t\t */\n-\t\t\tif (nix->rx_pause && node->bp_capa)\n-\t\t\t\tregval[k] |= BIT_ULL(13);\n \t\t\tk++;\n \t\t}\n \n", "prefixes": [ "06/15" ] }