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GET /api/patches/125906/?format=api
{ "id": 125906, "url": "http://patchwork.dpdk.org/api/patches/125906/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230411091144.1087887-1-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230411091144.1087887-1-ndabilpuram@marvell.com", "date": "2023-04-11T09:11:24", "name": "[01/21] common/cnxk: allocate dynamic BPIDs", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "8ddb9b38d963c11a84637eda1e347c033ef5e021", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230411091144.1087887-1-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 27660, "url": "http://patchwork.dpdk.org/api/series/27660/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27660", "date": "2023-04-11T09:11:24", "name": "[01/21] common/cnxk: allocate dynamic BPIDs", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27660/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/125906/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/125906/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 490764291B;\n\tTue, 11 Apr 2023 11:12:07 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 33F2240DFD;\n\tTue, 11 Apr 2023 11:12:07 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6375840A8B\n for <dev@dpdk.org>; Tue, 11 Apr 2023 11:12:05 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33B8g53q014916 for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:04 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3purfs94e3-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:04 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 11 Apr 2023 02:12:02 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 11 Apr 2023 02:12:02 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id C76033F706A;\n Tue, 11 Apr 2023 02:12:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=Y1hLE5YjSxzj9Hh+jJ301m516oo1oLIPCmNBYns3tV4=;\n b=AeM56L29lqfZxdj0vTJVa57yyV7L2MeNXOBbvyIdmYUfB8ItiS5fdxd37BYv73S1RWg9\n pWCC616RMn+7pPAJOshiga7irrkEzH8yDsr9RvSJAuMYLhdcj6NtHDrnhRKKRVm7p+/K\n 33czqeJ+yxC1l18dVocNcfQy2mghnzr+FxJAPmJAoc8zV25mDQSObKENzCqmt78i90Sv\n sg0LLWyLa9Dq8191BCX4//0xYEtzmDvLhUOagP4FxbaDnfW215b0sMo1aYzvLxW2MkZg\n A7K6Lx0XnRtVmXm5gjIq7R6tO0gbYJAAtqp9jybeZRd6mPSwWuY/Qbxih5+w1vKUrZ8v RQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 01/21] common/cnxk: allocate dynamic BPIDs", "Date": "Tue, 11 Apr 2023 14:41:24 +0530", "Message-ID": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "DgSclimjK56d7J1GN-p8HZ84LtrJMGbn", "X-Proofpoint-GUID": "DgSclimjK56d7J1GN-p8HZ84LtrJMGbn", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nNew mail box to allocate/free dynamic BPIDs based on NIX type.\nAdded to new mail box APIs to get/set RX channel config with\nnew BPIDs.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n\nDepends-on: series-27659 (\"add hwpools and support exchanging mbufs between pools\")\n\n drivers/common/cnxk/roc_cpt.c | 10 +-\n drivers/common/cnxk/roc_cpt.h | 3 +-\n drivers/common/cnxk/roc_features.h | 7 ++\n drivers/common/cnxk/roc_mbox.h | 31 ++++-\n drivers/common/cnxk/roc_nix.h | 21 ++++\n drivers/common/cnxk/roc_nix_fc.c | 182 +++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_inl.c | 24 ++--\n drivers/common/cnxk/roc_nix_priv.h | 1 +\n drivers/common/cnxk/version.map | 5 +\n 9 files changed, 266 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex dff2fbf2a4..d235ff51ca 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -311,8 +311,7 @@ roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt,\n }\n \n int\n-roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1,\n-\t\t\t uint16_t param2, uint16_t opcode)\n+roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_inline_ipsec_inb_cfg *cfg)\n {\n \tstruct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);\n \tstruct cpt_rx_inline_lf_cfg_msg *req;\n@@ -328,9 +327,10 @@ roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1,\n \t}\n \n \treq->sso_pf_func = idev_sso_pffunc_get();\n-\treq->param1 = param1;\n-\treq->param2 = param2;\n-\treq->opcode = opcode;\n+\treq->param1 = cfg->param1;\n+\treq->param2 = cfg->param2;\n+\treq->opcode = cfg->opcode;\n+\treq->bpid = cfg->bpid;\n \n \trc = mbox_process(mbox);\n exit:\ndiff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nindex d3a5683dc8..92a18711dc 100644\n--- a/drivers/common/cnxk/roc_cpt.h\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -178,8 +178,7 @@ int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot,\n int __roc_api roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt,\n \t\t\t\t\tstruct roc_cpt_inline_ipsec_inb_cfg *cfg);\n int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt,\n-\t\t\t\t\t uint16_t param1, uint16_t param2,\n-\t\t\t\t\t uint16_t opcode);\n+\t\t\t\t\t struct roc_cpt_inline_ipsec_inb_cfg *cfg);\n int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);\n int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);\n void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);\ndiff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h\nindex 252f306a86..c2893faa65 100644\n--- a/drivers/common/cnxk/roc_features.h\n+++ b/drivers/common/cnxk/roc_features.h\n@@ -40,4 +40,11 @@ roc_feature_nix_has_reass(void)\n \treturn roc_model_is_cn10ka();\n }\n \n+static inline bool\n+roc_feature_nix_has_rxchan_multi_bpid(void)\n+{\n+\tif (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0())\n+\t\treturn true;\n+\treturn false;\n+}\n #endif\ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex af3c10b0b0..3d5746b9b8 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -275,7 +275,12 @@ struct mbox_msghdr {\n \tM(NIX_SPI_TO_SA_ADD, 0x8026, nix_spi_to_sa_add, nix_spi_to_sa_add_req, \\\n \t nix_spi_to_sa_add_rsp) \\\n \tM(NIX_SPI_TO_SA_DELETE, 0x8027, nix_spi_to_sa_delete, \\\n-\t nix_spi_to_sa_delete_req, msg_rsp)\n+\t nix_spi_to_sa_delete_req, msg_rsp) \\\n+\tM(NIX_ALLOC_BPIDS, 0x8028, nix_alloc_bpids, nix_alloc_bpid_req, \\\n+\t nix_bpids) \\\n+\tM(NIX_FREE_BPIDS, 0x8029, nix_free_bpids, nix_bpids, msg_rsp) \\\n+\tM(NIX_RX_CHAN_CFG, 0x802a, nix_rx_chan_cfg, nix_rx_chan_cfg, \\\n+\t nix_rx_chan_cfg)\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n@@ -1186,6 +1191,30 @@ struct nix_bp_cfg_rsp {\n \tuint8_t __io chan_cnt;\n };\n \n+struct nix_alloc_bpid_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io bpid_cnt;\n+\tuint8_t __io type;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct nix_bpids {\n+#define ROC_NIX_MAX_BPID_CNT\t8\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io bpid_cnt;\n+\tuint16_t __io bpids[ROC_NIX_MAX_BPID_CNT];\n+\tuint64_t __io rsvd;\n+};\n+\n+struct nix_rx_chan_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io type; /* Interface type(CGX/CPT/LBK) */\n+\tuint8_t __io read;\n+\tuint16_t __io chan; /* RX channel to be configured */\n+\tuint64_t __io val; /* NIX_AF_RX_CHAN_CFG value */\n+\tuint64_t __io rsvd;\n+};\n+\n /* Global NIX inline IPSec configuration */\n struct nix_inline_ipsec_cfg {\n \tstruct mbox_msghdr hdr;\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 0ec98ad630..2737bb9517 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -16,6 +16,17 @@\n #define ROC_NIX_SQB_LOWER_THRESH 70U\n #define ROC_NIX_SQB_SLACK\t 12U\n \n+/* Reserved interface types for BPID allocation */\n+#define ROC_NIX_INTF_TYPE_CGX 0\n+#define ROC_NIX_INTF_TYPE_LBK 1\n+#define ROC_NIX_INTF_TYPE_SDP 2\n+#define ROC_NIX_INTF_TYPE_CPT 3\n+#define ROC_NIX_INTF_TYPE_RSVD 4\n+\n+/* Application based types for BPID allocation, start from end (255 unused rsvd) */\n+#define ROC_NIX_INTF_TYPE_CPT_NIX 254\n+#define ROC_NIX_INTF_TYPE_SSO 253\n+\n enum roc_nix_rss_reta_sz {\n \tROC_NIX_RSS_RETA_SZ_64 = 64,\n \tROC_NIX_RSS_RETA_SZ_128 = 128,\n@@ -837,6 +848,16 @@ enum roc_nix_fc_mode __roc_api roc_nix_fc_mode_get(struct roc_nix *roc_nix);\n \n void __roc_api roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id,\n \t\t\t\t uint8_t ena, uint8_t force, uint8_t tc);\n+int __roc_api roc_nix_bpids_alloc(struct roc_nix *roc_nix, uint8_t type,\n+\t\t\t\t uint8_t bp_cnt, uint16_t *bpids);\n+int __roc_api roc_nix_bpids_free(struct roc_nix *roc_nix, uint8_t bp_cnt,\n+\t\t\t\t uint16_t *bpids);\n+int __roc_api roc_nix_rx_chan_cfg_get(struct roc_nix *roc_nix, uint16_t chan,\n+\t\t\t\t bool is_cpt, uint64_t *cfg);\n+int __roc_api roc_nix_rx_chan_cfg_set(struct roc_nix *roc_nix, uint16_t chan,\n+\t\t\t\t bool is_cpt, uint64_t val);\n+int __roc_api roc_nix_chan_bpid_set(struct roc_nix *roc_nix, uint16_t chan,\n+\t\t\t\t uint64_t bpid, int ena, bool cpt_chan);\n \n /* NPC */\n int __roc_api roc_nix_npc_promisc_ena_dis(struct roc_nix *roc_nix, int enable);\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex cec83b31f3..3b726673a6 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -104,6 +104,17 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)\n \t\tnix->cpt_lbpid = 0;\n \t}\n \n+\t/* CPT to NIX BP on all channels */\n+\tif (!roc_feature_nix_has_rxchan_multi_bpid() || !nix->cpt_nixbpid)\n+\t\tgoto exit;\n+\n+\tmbox_put(mbox);\n+\tfor (i = 0; i < nix->rx_chan_cnt; i++) {\n+\t\trc = roc_nix_chan_bpid_set(roc_nix, i, nix->cpt_nixbpid, enable, false);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\t}\n+\treturn rc;\n exit:\n \tmbox_put(mbox);\n \treturn rc;\n@@ -599,3 +610,174 @@ roc_nix_chan_count_get(struct roc_nix *roc_nix)\n \n \treturn nix->chan_cnt;\n }\n+\n+/* Allocate BPID for requested type\n+ * Returns number of BPIDs allocated\n+ *\t0 if no BPIDs available\n+ *\t-ve value on error\n+ */\n+int\n+roc_nix_bpids_alloc(struct roc_nix *roc_nix, uint8_t type, uint8_t bp_cnt, uint16_t *bpids)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = mbox_get(nix->dev.mbox);\n+\tstruct nix_alloc_bpid_req *req;\n+\tstruct nix_bpids *rsp;\n+\tint rc = -EINVAL;\n+\n+\t/* Use this api for unreserved interface types */\n+\tif ((type < ROC_NIX_INTF_TYPE_RSVD) || (bp_cnt > ROC_NIX_MAX_BPID_CNT) || !bpids)\n+\t\tgoto exit;\n+\n+\trc = -ENOSPC;\n+\treq = mbox_alloc_msg_nix_alloc_bpids(mbox);\n+\tif (req == NULL)\n+\t\tgoto exit;\n+\treq->type = type;\n+\treq->bpid_cnt = bp_cnt;\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tfor (rc = 0; rc < rsp->bpid_cnt; rc++)\n+\t\tbpids[rc] = rsp->bpids[rc];\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_bpids_free(struct roc_nix *roc_nix, uint8_t bp_cnt, uint16_t *bpids)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = mbox_get(nix->dev.mbox);\n+\tstruct nix_bpids *req;\n+\tint rc = -EINVAL;\n+\n+\t/* Use this api for unreserved interface types */\n+\tif ((bp_cnt > ROC_NIX_MAX_BPID_CNT) || !bpids)\n+\t\tgoto exit;\n+\n+\trc = -ENOSPC;\n+\treq = mbox_alloc_msg_nix_free_bpids(mbox);\n+\tif (req == NULL)\n+\t\tgoto exit;\n+\tfor (rc = 0; rc < bp_cnt; rc++)\n+\t\treq->bpids[rc] = bpids[rc];\n+\treq->bpid_cnt = rc;\n+\n+\trc = mbox_process(mbox);\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_rx_chan_cfg_get(struct roc_nix *roc_nix, uint16_t chan, bool is_cpt, uint64_t *cfg)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = mbox_get(nix->dev.mbox);\n+\tstruct nix_rx_chan_cfg *req;\n+\tstruct nix_rx_chan_cfg *rsp;\n+\tint rc = -EINVAL;\n+\n+\treq = mbox_alloc_msg_nix_rx_chan_cfg(mbox);\n+\tif (req == NULL)\n+\t\tgoto exit;\n+\tif (is_cpt)\n+\t\treq->type = ROC_NIX_INTF_TYPE_CPT;\n+\treq->chan = chan;\n+\treq->read = 1;\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\tgoto exit;\n+\t*cfg = rsp->val;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_rx_chan_cfg_set(struct roc_nix *roc_nix, uint16_t chan, bool is_cpt, uint64_t val)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = mbox_get(nix->dev.mbox);\n+\tstruct nix_rx_chan_cfg *req;\n+\tint rc = -EINVAL;\n+\n+\treq = mbox_alloc_msg_nix_rx_chan_cfg(mbox);\n+\tif (req == NULL)\n+\t\tgoto exit;\n+\tif (is_cpt)\n+\t\treq->type = ROC_NIX_INTF_TYPE_CPT;\n+\treq->chan = chan;\n+\treq->val = val;\n+\treq->read = 0;\n+\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tgoto exit;\n+exit:\n+\tmbox_put(mbox);\n+\treturn rc;\n+}\n+\n+#define NIX_BPID1_ENA 15\n+#define NIX_BPID2_ENA 14\n+#define NIX_BPID3_ENA 13\n+\n+#define NIX_BPID1_OFF 20\n+#define NIX_BPID2_OFF 32\n+#define NIX_BPID3_OFF 44\n+\n+int\n+roc_nix_chan_bpid_set(struct roc_nix *roc_nix, uint16_t chan, uint64_t bpid, int ena, bool cpt_chan)\n+{\n+\tuint64_t cfg;\n+\tint rc;\n+\n+\tif (!roc_feature_nix_has_rxchan_multi_bpid())\n+\t\treturn -ENOTSUP;\n+\n+\trc = roc_nix_rx_chan_cfg_get(roc_nix, chan, cpt_chan, &cfg);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (ena) {\n+\t\tif ((((cfg >> NIX_BPID1_OFF) & GENMASK_ULL(8, 0)) == bpid) ||\n+\t\t (((cfg >> NIX_BPID2_OFF) & GENMASK_ULL(8, 0)) == bpid) ||\n+\t\t (((cfg >> NIX_BPID3_OFF) & GENMASK_ULL(8, 0)) == bpid))\n+\t\t\treturn 0;\n+\n+\t\tif (!(cfg & BIT_ULL(NIX_BPID1_ENA))) {\n+\t\t\tcfg &= ~GENMASK_ULL(NIX_BPID1_OFF + 8, NIX_BPID1_OFF);\n+\t\t\tcfg |= (((uint64_t)bpid << NIX_BPID1_OFF) | BIT_ULL(NIX_BPID1_ENA));\n+\t\t} else if (!(cfg & BIT_ULL(NIX_BPID2_ENA))) {\n+\t\t\tcfg &= ~GENMASK_ULL(NIX_BPID2_OFF + 8, NIX_BPID2_OFF);\n+\t\t\tcfg |= (((uint64_t)bpid << NIX_BPID2_OFF) | BIT_ULL(NIX_BPID2_ENA));\n+\t\t} else if (!(cfg & BIT_ULL(NIX_BPID3_ENA))) {\n+\t\t\tcfg &= ~GENMASK_ULL(NIX_BPID3_OFF + 8, NIX_BPID3_OFF);\n+\t\t\tcfg |= (((uint64_t)bpid << NIX_BPID3_OFF) | BIT_ULL(NIX_BPID3_ENA));\n+\t\t} else {\n+\t\t\tplt_nix_dbg(\"Exceed maximum BPIDs\");\n+\t\t\treturn -ENOSPC;\n+\t\t}\n+\t} else {\n+\t\tif (((cfg >> NIX_BPID1_OFF) & GENMASK_ULL(8, 0)) == bpid) {\n+\t\t\tcfg &= ~(GENMASK_ULL(NIX_BPID1_OFF + 8, NIX_BPID1_OFF) |\n+\t\t\t\t BIT_ULL(NIX_BPID1_ENA));\n+\t\t} else if (((cfg >> NIX_BPID2_OFF) & GENMASK_ULL(8, 0)) == bpid) {\n+\t\t\tcfg &= ~(GENMASK_ULL(NIX_BPID2_OFF + 8, NIX_BPID2_OFF) |\n+\t\t\t\t BIT_ULL(NIX_BPID2_ENA));\n+\t\t} else if (((cfg >> NIX_BPID3_OFF) & GENMASK_ULL(8, 0)) == bpid) {\n+\t\t\tcfg &= ~(GENMASK_ULL(NIX_BPID3_OFF + 8, NIX_BPID3_OFF) |\n+\t\t\t\t BIT_ULL(NIX_BPID3_ENA));\n+\t\t} else {\n+\t\t\tplt_nix_dbg(\"BPID not found\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\treturn roc_nix_rx_chan_cfg_set(roc_nix, chan, cpt_chan, cfg);\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 076d83e8d5..9485bba099 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -603,11 +603,10 @@ int\n roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct roc_cpt_inline_ipsec_inb_cfg cfg;\n \tstruct idev_cfg *idev = idev_get_cfg();\n+\tuint16_t bpids[ROC_NIX_MAX_BPID_CNT];\n \tstruct roc_cpt *roc_cpt;\n-\tuint16_t opcode;\n-\tuint16_t param1;\n-\tuint16_t param2;\n \tint rc;\n \n \tif (idev == NULL)\n@@ -624,9 +623,9 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \t}\n \n \tif (roc_model_is_cn9k()) {\n-\t\tparam1 = (ROC_ONF_IPSEC_INB_MAX_L2_SZ >> 3) & 0xf;\n-\t\tparam2 = ROC_IE_ON_INB_IKEV2_SINGLE_SA_SUPPORT;\n-\t\topcode =\n+\t\tcfg.param1 = (ROC_ONF_IPSEC_INB_MAX_L2_SZ >> 3) & 0xf;\n+\t\tcfg.param2 = ROC_IE_ON_INB_IKEV2_SINGLE_SA_SUPPORT;\n+\t\tcfg.opcode =\n \t\t\t((ROC_IE_ON_INB_MAX_CTX_LEN << 8) |\n \t\t\t (ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6)));\n \t} else {\n@@ -634,13 +633,18 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \n \t\tu.u16 = 0;\n \t\tu.s.esp_trailer_disable = 1;\n-\t\tparam1 = u.u16;\n-\t\tparam2 = 0;\n-\t\topcode = (ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6));\n+\t\tcfg.param1 = u.u16;\n+\t\tcfg.param2 = 0;\n+\t\tcfg.opcode = (ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6));\n+\t\trc = roc_nix_bpids_alloc(roc_nix, ROC_NIX_INTF_TYPE_CPT_NIX, 1, bpids);\n+\t\tif (rc > 0) {\n+\t\t\tnix->cpt_nixbpid = bpids[0];\n+\t\t\tcfg.bpid = nix->cpt_nixbpid;\n+\t\t}\n \t}\n \n \t/* Do onetime Inbound Inline config in CPTPF */\n-\trc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, param1, param2, opcode);\n+\trc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, &cfg);\n \tif (rc && rc != -EEXIST) {\n \t\tplt_err(\"Failed to setup inbound lf, rc=%d\", rc);\n \t\treturn rc;\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 2fe9093324..99e27cdc56 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -208,6 +208,7 @@ struct nix {\n \tuint16_t outb_se_ring_cnt;\n \tuint16_t outb_se_ring_base;\n \tuint16_t cpt_lbpid;\n+\tuint16_t cpt_nixbpid;\n \tbool need_meta_aura;\n \t/* Mode provided by driver */\n \tbool inb_inl_dev;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 5281c71550..e7c6f6bce5 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -147,6 +147,9 @@ INTERNAL {\n \troc_nix_bpf_stats_reset;\n \troc_nix_bpf_stats_to_idx;\n \troc_nix_bpf_timeunit_get;\n+\troc_nix_bpids_alloc;\n+\troc_nix_bpids_free;\n+\troc_nix_chan_bpid_set;\n \troc_nix_chan_count_get;\n \troc_nix_cq_dump;\n \troc_nix_cq_fini;\n@@ -277,6 +280,8 @@ INTERNAL {\n \troc_nix_rss_key_set;\n \troc_nix_rss_reta_get;\n \troc_nix_rss_reta_set;\n+\troc_nix_rx_chan_cfg_get;\n+\troc_nix_rx_chan_cfg_set;\n \troc_nix_rx_drop_re_set;\n \troc_nix_rx_queue_intr_disable;\n \troc_nix_rx_queue_intr_enable;\n", "prefixes": [ "01/21" ] }