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GET /api/patches/125911/?format=api
{ "id": 125911, "url": "http://patchwork.dpdk.org/api/patches/125911/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230411091144.1087887-6-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230411091144.1087887-6-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230411091144.1087887-6-ndabilpuram@marvell.com", "date": "2023-04-11T09:11:29", "name": "[06/21] common/cnxk: add percent drop threshold to pool", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "83cc68e9359d1a52737c80e9dcb66c398487cd04", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230411091144.1087887-6-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 27660, "url": "http://patchwork.dpdk.org/api/series/27660/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27660", "date": "2023-04-11T09:11:24", "name": "[01/21] common/cnxk: allocate dynamic BPIDs", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27660/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/125911/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/125911/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8913A4291B;\n\tTue, 11 Apr 2023 11:12:40 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B9ECD42D12;\n\tTue, 11 Apr 2023 11:12:23 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 3B44C42D12\n for <dev@dpdk.org>; Tue, 11 Apr 2023 11:12:22 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33B8YWB3021305 for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:21 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1ss-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 11 Apr 2023 02:12:21 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 11 Apr 2023 02:12:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 11 Apr 2023 02:12:19 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 89A1F3F7074;\n Tue, 11 Apr 2023 02:12:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=IZJzYiBEt9LruT0K55ZXP6caZNBpY8CP/sPZF7L+Q1U=;\n b=ZKGMoJJ67G+pDvV6/1zTiFs+o//Hq450jcfAC2UfWXWUD1mRkOrYxTO9sQVmsmqKBRdo\n rUSZXDKjnro7AR2ZWU9sIPMCnESIHbpHSPcWqcfVXS1/lC2gL2ezbXc4VObdA9uyUj5w\n X0aGfQ9SMYPm2UnLxd50xkBHZBkitF6lwW2MaVI1/Z1F09r00/fE9h15J0BLFa84IUbn\n pGfmmn7p2hvuOQicyqxOBs489B7mjmY4E0KPYS/i8bMaU5+wgVr5wMcWEoFVC27B/mqK\n eKcsvJ59baMta1sFQ4P3fcvkCFE7v3bAeNWwC8e09NSl6ZQ5EaJH4obMog23b109dn2I bA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n \"Shijith Thotton\" <sthotton@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 06/21] common/cnxk: add percent drop threshold to pool", "Date": "Tue, 11 Apr 2023 14:41:29 +0530", "Message-ID": "<20230411091144.1087887-6-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "References": "<20230411091144.1087887-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "4j7uUD-j5wvRJKlut9yjRtH3rwAO7vc_", "X-Proofpoint-ORIG-GUID": "4j7uUD-j5wvRJKlut9yjRtH3rwAO7vc_", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nCurrently hard coded drop threshold(95%) is configured to aura/pool as a\nthreshold for drop limit.\n\nPatch adds a input parameter to RoC API so that user passed percentage\nvalue can be configured.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 6 ++++--\n drivers/common/cnxk/roc_nix_fc.c | 17 ++++++++++++-----\n drivers/common/cnxk/roc_nix_inl.c | 2 +-\n drivers/common/cnxk/roc_nix_priv.h | 2 +-\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 4 ++--\n 5 files changed, 20 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 50aef4fe85..fde8fe4ecc 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -15,6 +15,7 @@\n #define ROC_NIX_PFC_CLASS_INVALID UINT8_MAX\n #define ROC_NIX_SQB_THRESH\t 30U\n #define ROC_NIX_SQB_SLACK\t 12U\n+#define ROC_NIX_AURA_THRESH\t 95U\n \n /* Reserved interface types for BPID allocation */\n #define ROC_NIX_INTF_TYPE_CGX 0\n@@ -197,6 +198,7 @@ struct roc_nix_fc_cfg {\n \t\t\tuint16_t cq_drop;\n \t\t\tbool enable;\n \t\t\tuint64_t pool;\n+\t\t\tuint64_t pool_drop_pct;\n \t\t} rq_cfg;\n \n \t\tstruct {\n@@ -849,8 +851,8 @@ uint16_t __roc_api roc_nix_chan_count_get(struct roc_nix *roc_nix);\n \n enum roc_nix_fc_mode __roc_api roc_nix_fc_mode_get(struct roc_nix *roc_nix);\n \n-void __roc_api roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id,\n-\t\t\t\t uint8_t ena, uint8_t force, uint8_t tc);\n+void __roc_api roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n+\t\t\t\t uint8_t force, uint8_t tc, uint64_t drop_percent);\n int __roc_api roc_nix_bpids_alloc(struct roc_nix *roc_nix, uint8_t type,\n \t\t\t\t uint8_t bp_cnt, uint16_t *bpids);\n int __roc_api roc_nix_bpids_free(struct roc_nix *roc_nix, uint8_t bp_cnt,\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex 3618d2920b..98dd9a9e66 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -297,6 +297,7 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n {\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct roc_nix_fc_cfg tmp;\n+\tuint64_t pool_drop_pct;\n \tstruct roc_nix_rq *rq;\n \tint sso_ena = 0, rc;\n \n@@ -307,13 +308,19 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\treturn -EINVAL;\n \n \tif (sso_ena) {\n+\t\tpool_drop_pct = fc_cfg->rq_cfg.pool_drop_pct;\n+\t\t/* Use default value for zero pct */\n+\t\tif (fc_cfg->rq_cfg.enable && !pool_drop_pct)\n+\t\t\tpool_drop_pct = ROC_NIX_AURA_THRESH;\n+\n \t\troc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool,\n \t\t\t\t fc_cfg->rq_cfg.enable, true,\n-\t\t\t\t fc_cfg->rq_cfg.tc);\n+\t\t\t\t fc_cfg->rq_cfg.tc, fc_cfg->rq_cfg.pool_drop_pct);\n \n \t\tif (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle)\n \t\t\troc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle,\n-\t\t\t\t\t fc_cfg->rq_cfg.enable, true, fc_cfg->rq_cfg.tc);\n+\t\t\t\t\t fc_cfg->rq_cfg.enable, true, fc_cfg->rq_cfg.tc,\n+\t\t\t\t\t fc_cfg->rq_cfg.pool_drop_pct);\n \t}\n \n \t/* Copy RQ config to CQ config as they are occupying same area */\n@@ -476,8 +483,8 @@ nix_rx_chan_multi_bpid_cfg(struct roc_nix *roc_nix, uint8_t chan, uint16_t bpid,\n #define NIX_BPID_INVALID 0xFFFF\n \n void\n-roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n-\t\t uint8_t force, uint8_t tc)\n+roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, uint8_t force,\n+\t\t uint8_t tc, uint64_t drop_percent)\n {\n \tuint32_t aura_id = roc_npa_aura_handle_to_aura(pool_id);\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n@@ -513,7 +520,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena,\n \t}\n \n \tbp_intf = 1 << nix->is_nix1;\n-\tbp_thresh = NIX_RQ_AURA_THRESH(rsp->aura.limit >> rsp->aura.shift);\n+\tbp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift);\n \n \t/* BP is already enabled. */\n \tif (rsp->aura.bp_ena && ena) {\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex b16756d642..329ebf9405 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -263,7 +263,7 @@ roc_nix_inl_meta_aura_check(struct roc_nix *roc_nix, struct roc_nix_rq *rq)\n \t\t */\n \t\tif (aura_setup && nix->rqs[0] && nix->rqs[0]->tc != ROC_NIX_PFC_CLASS_INVALID)\n \t\t\troc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle,\n-\t\t\t\t\t true, true, nix->rqs[0]->tc);\n+\t\t\t\t\t true, true, nix->rqs[0]->tc, ROC_NIX_AURA_THRESH);\n \t} else {\n \t\trc = nix_inl_global_meta_buffer_validate(idev, rq);\n \t\tif (rc)\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 7144d1ee10..f900a81d8a 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -20,7 +20,7 @@\n /* Apply LBP at 75% of actual BP */\n #define NIX_CQ_LPB_THRESH_FRAC\t(75 * 16 / 100)\n #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)\n-#define NIX_RQ_AURA_THRESH(x)\t(((x)*95) / 100)\n+#define NIX_RQ_AURA_THRESH(percent, val) (((val) * (percent)) / 100)\n \n /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */\n #define CQ_CQE_THRESH_DEFAULT\t0x1ULL\ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nindex 5ec436382c..3dc3d04a1e 100644\n--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -263,7 +263,7 @@ cnxk_sso_rx_adapter_queue_add(\n \t\tif (rxq_sp->tx_pause)\n \t\t\troc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,\n \t\t\t\t\t rxq_sp->qconf.mp->pool_id, true,\n-\t\t\t\t\t dev->force_ena_bp, rxq_sp->tc);\n+\t\t\t\t\t dev->force_ena_bp, rxq_sp->tc, ROC_NIX_AURA_THRESH);\n \t\tcnxk_sso_tstamp_cfg(eth_dev->data->port_id, cnxk_eth_dev, dev);\n \t\tcnxk_eth_dev->nb_rxq_sso++;\n \t}\n@@ -307,7 +307,7 @@ cnxk_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n \t\trc = cnxk_sso_rxq_disable(cnxk_eth_dev, (uint16_t)rx_queue_id);\n \t\troc_nix_fc_npa_bp_cfg(&cnxk_eth_dev->nix,\n \t\t\t\t rxq_sp->qconf.mp->pool_id, false,\n-\t\t\t\t dev->force_ena_bp, 0);\n+\t\t\t\t dev->force_ena_bp, 0, ROC_NIX_AURA_THRESH);\n \t\tcnxk_eth_dev->nb_rxq_sso--;\n \n \t\t/* Enable drop_re if it was disabled earlier */\n", "prefixes": [ "06/21" ] }