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GET /api/patches/126351/?format=api
{ "id": 126351, "url": "http://patchwork.dpdk.org/api/patches/126351/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230421065048.106899-8-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230421065048.106899-8-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230421065048.106899-8-beilei.xing@intel.com", "date": "2023-04-21T06:50:45", "name": "[07/10] net/cpfl: support hairpin queue start/stop", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "90bc55cfc7b738fa721f0147a6da0c9f6ccc2f7c", "submitter": { "id": 410, "url": "http://patchwork.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230421065048.106899-8-beilei.xing@intel.com/mbox/", "series": [ { "id": 27810, "url": "http://patchwork.dpdk.org/api/series/27810/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27810", "date": "2023-04-21T06:50:38", "name": "add hairpin queue support", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27810/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126351/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/126351/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BECE4429A9;\n\tFri, 21 Apr 2023 09:14:43 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C9E0542D40;\n\tFri, 21 Apr 2023 09:14:06 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id C9F3442D40\n for <dev@dpdk.org>; Fri, 21 Apr 2023 09:14:04 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2023 00:14:04 -0700", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by orsmga008.jf.intel.com with ESMTP; 21 Apr 2023 00:14:02 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682061245; x=1713597245;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=s5ZcdxqIaRzfPIeOWiPPB8ptUyN6uA4V4BSKp2mOKGg=;\n b=m2fBoGPvJ5tWzkxpaCWQFJjj1cYTuOEXNw5Qhnk1rzBaTqNsUc/G3snx\n yWNX/Z0IvKtUjDZQ8/FAdBqk4yv5OBoED7JaGCYoB6GEcYsdcoXJ9PvBM\n oTDMiYnv0XtOTtjH/Uv5Xv10hboUj4HcXLUvO1iJDPos4eAcaEgA6mXnl\n X5hnVMuKKK2kKozQu4nR3nn9no9lCg5OfzxzSMZc0qBNuNTtBnK4h4D13\n 22lFMzByXUjMJp93uKKHR12RpYrFb2Ur/kPMHtTMPloevVM9YTuPEkb6S\n KfX67H6eMpYwIRdDZ+usxSl0eq5kFlHF2/SeAg1hRqFF2pkvbNFzYOHtq A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10686\"; a=\"326260084\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"326260084\"", "E=McAfee;i=\"6600,9927,10686\"; a=\"722669125\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"722669125\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>,\n Xiao Wang <xiao.w.wang@intel.com>", "Subject": "[PATCH 07/10] net/cpfl: support hairpin queue start/stop", "Date": "Fri, 21 Apr 2023 06:50:45 +0000", "Message-Id": "<20230421065048.106899-8-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20230421065048.106899-1-beilei.xing@intel.com>", "References": "<20230421065048.106899-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nThis patch supports Rx/Tx hairpin queue start/stop.\n\nSigned-off-by: Xiao Wang <xiao.w.wang@intel.com>\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/common/idpf/idpf_common_virtchnl.c | 2 +-\n drivers/common/idpf/idpf_common_virtchnl.h | 3 +\n drivers/common/idpf/version.map | 1 +\n drivers/net/cpfl/cpfl_ethdev.c | 39 ++++++\n drivers/net/cpfl/cpfl_rxtx.c | 153 ++++++++++++++++++---\n drivers/net/cpfl/cpfl_rxtx.h | 14 ++\n 6 files changed, 193 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/common/idpf/idpf_common_virtchnl.c b/drivers/common/idpf/idpf_common_virtchnl.c\nindex 50cd43a8dd..20a5bc085d 100644\n--- a/drivers/common/idpf/idpf_common_virtchnl.c\n+++ b/drivers/common/idpf/idpf_common_virtchnl.c\n@@ -733,7 +733,7 @@ idpf_vc_vectors_dealloc(struct idpf_vport *vport)\n \treturn err;\n }\n \n-static int\n+int\n idpf_vc_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid,\n \t\t\t uint32_t type, bool on)\n {\ndiff --git a/drivers/common/idpf/idpf_common_virtchnl.h b/drivers/common/idpf/idpf_common_virtchnl.h\nindex 277235ba7d..18db6cd8c8 100644\n--- a/drivers/common/idpf/idpf_common_virtchnl.h\n+++ b/drivers/common/idpf/idpf_common_virtchnl.h\n@@ -71,6 +71,9 @@ __rte_internal\n int idpf_vc_txq_config_by_info(struct idpf_vport *vport, struct virtchnl2_txq_info *txq_info,\n \t\t\t uint16_t num_qs);\n __rte_internal\n+int idpf_vc_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid,\n+\t\t\t uint32_t type, bool on);\n+__rte_internal\n int idpf_vc_queue_grps_del(struct idpf_vport *vport,\n \t\t\t uint16_t num_q_grps,\n \t\t\t struct virtchnl2_queue_group_id *qg_ids);\ndiff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map\nindex a339a4bf8e..0e87dba2ae 100644\n--- a/drivers/common/idpf/version.map\n+++ b/drivers/common/idpf/version.map\n@@ -45,6 +45,7 @@ INTERNAL {\n \tidpf_vc_cmd_execute;\n \tidpf_vc_ctlq_post_rx_buffs;\n \tidpf_vc_ctlq_recv;\n+\tidpf_vc_ena_dis_one_queue;\n \tidpf_vc_irq_map_unmap_config;\n \tidpf_vc_one_msg_read;\n \tidpf_vc_ptype_info_query;\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 13edf2e706..f154c83f27 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -895,6 +895,45 @@ cpfl_start_queues(struct rte_eth_dev *dev)\n \t\t}\n \t}\n \n+\t/* For non-cross vport hairpin queues, enable Tx queue and Rx queue,\n+\t * then enable Tx completion queue and Rx buffer queue.\n+\t */\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tcpfl_txq = dev->data->tx_queues[i];\n+\t\tif (cpfl_txq->hairpin_info.hairpin_q && !cpfl_txq->hairpin_info.manual_bind) {\n+\t\t\terr = cpfl_switch_hairpin_rxtx_queue(cpfl_vport,\n+\t\t\t\t\t\t\t i - cpfl_vport->nb_data_txq,\n+\t\t\t\t\t\t\t false, true);\n+\t\t\tif (err)\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch hairpin TX queue %u on\",\n+\t\t\t\t\t i);\n+\t\t\telse\n+\t\t\t\tcpfl_txq->base.q_started = true;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tcpfl_rxq = dev->data->rx_queues[i];\n+\t\tif (cpfl_rxq->hairpin_info.hairpin_q && !cpfl_rxq->hairpin_info.manual_bind) {\n+\t\t\terr = cpfl_switch_hairpin_rxtx_queue(cpfl_vport,\n+\t\t\t\t\t\t\t i - cpfl_vport->nb_data_rxq,\n+\t\t\t\t\t\t\t true, true);\n+\t\t\tif (err)\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch hairpin RX queue %u on\",\n+\t\t\t\t\t i);\n+\t\t\telse\n+\t\t\t\tcpfl_rxq->base.q_started = true;\n+\t\t}\n+\t}\n+\n+\tif (tx_cmplq_flag == 1 && rx_bufq_flag == 1) {\n+\t\terr = cpfl_switch_hairpin_bufq_complq(cpfl_vport, true);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch hairpin Tx complq and Rx bufq\");\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n \treturn err;\n }\n \ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex 040beb5bac..ed2d100c35 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -1010,6 +1010,83 @@ cpfl_hairpin_txq_config(struct idpf_vport *vport, struct cpfl_tx_queue *cpfl_txq\n \treturn idpf_vc_txq_config_by_info(vport, txq_info, 1);\n }\n \n+int\n+cpfl_switch_hairpin_bufq_complq(struct cpfl_vport *cpfl_vport, bool on)\n+{\n+\tstruct idpf_vport *vport = &cpfl_vport->base;\n+\tuint32_t type;\n+\tint err, queue_id;\n+\n+\ttype = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;\n+\tqueue_id = cpfl_vport->p2p_tx_complq->queue_id;\n+\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\tif (err)\n+\t\treturn err;\n+\n+\ttype = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;\n+\tqueue_id = cpfl_vport->p2p_rx_bufq->queue_id;\n+\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\n+\treturn err;\n+}\n+\n+int\n+cpfl_switch_hairpin_rxtx_queue(struct cpfl_vport *cpfl_vport, uint16_t logic_qid,\n+\t\t\t bool rx, bool on)\n+{\n+\tstruct idpf_vport *vport = &cpfl_vport->base;\n+\tuint32_t type;\n+\tint err, queue_id;\n+\n+\ttype = rx ? VIRTCHNL2_QUEUE_TYPE_RX : VIRTCHNL2_QUEUE_TYPE_TX;\n+\n+\tif (type == VIRTCHNL2_QUEUE_TYPE_RX)\n+\t\tqueue_id = cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info.rx_start_qid, logic_qid);\n+\telse\n+\t\tqueue_id = cpfl_hw_qid_get(cpfl_vport->p2p_q_chunks_info.tx_start_qid, logic_qid);\n+\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn err;\n+}\n+\n+static int\n+cpfl_alloc_split_p2p_rxq_mbufs(struct idpf_rx_queue *rxq)\n+{\n+\tvolatile struct virtchnl2_p2p_rx_buf_desc *rxd;\n+\tstruct rte_mbuf *mbuf = NULL;\n+\tuint64_t dma_addr;\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\tmbuf = rte_mbuf_raw_alloc(rxq->mp);\n+\t\tif (unlikely(!mbuf)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate mbuf for RX\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\trte_mbuf_refcnt_set(mbuf, 1);\n+\t\tmbuf->next = NULL;\n+\t\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n+\t\tmbuf->nb_segs = 1;\n+\t\tmbuf->port = rxq->port_id;\n+\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));\n+\n+\t\trxd = &((volatile struct virtchnl2_p2p_rx_buf_desc *)(rxq->rx_ring))[i];\n+\t\trxd->reserve0 = 0;\n+\t\trxd->pkt_addr = dma_addr;\n+\n+\t\trxq->sw_ring[i] = mbuf;\n+\t}\n+\n+\trxq->nb_rx_hold = 0;\n+\t/* The value written in the RX buffer queue tail register, must be a multiple of 8.*/\n+\trxq->rx_tail = rxq->nb_rx_desc - CPFL_HAIRPIN_Q_TAIL_AUX_VALUE;\n+\n+\treturn 0;\n+}\n+\n int\n cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n@@ -1063,22 +1140,31 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \t\tIDPF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n \t} else {\n \t\t/* Split queue */\n-\t\terr = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq1);\n-\t\tif (err != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX buffer queue mbuf\");\n-\t\t\treturn err;\n-\t\t}\n-\t\terr = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq2);\n-\t\tif (err != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX buffer queue mbuf\");\n-\t\t\treturn err;\n+\t\tif (cpfl_rxq->hairpin_info.hairpin_q) {\n+\t\t\terr = cpfl_alloc_split_p2p_rxq_mbufs(rxq->bufq1);\n+\t\t\tif (err != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate p2p RX buffer queue mbuf\");\n+\t\t\t\treturn err;\n+\t\t\t}\n+\t\t} else {\n+\t\t\terr = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq1);\n+\t\t\tif (err != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX buffer queue mbuf\");\n+\t\t\t\treturn err;\n+\t\t\t}\n+\t\t\terr = idpf_qc_split_rxq_mbufs_alloc(rxq->bufq2);\n+\t\t\tif (err != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX buffer queue mbuf\");\n+\t\t\t\treturn err;\n+\t\t\t}\n \t\t}\n \n \t\trte_wmb();\n \n \t\t/* Init the RX tail register. */\n \t\tIDPF_PCI_REG_WRITE(rxq->bufq1->qrx_tail, rxq->bufq1->rx_tail);\n-\t\tIDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2->rx_tail);\n+\t\tif (rxq->bufq2)\n+\t\t\tIDPF_PCI_REG_WRITE(rxq->bufq2->qrx_tail, rxq->bufq2->rx_tail);\n \t}\n \n \treturn err;\n@@ -1185,7 +1271,12 @@ cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \t\treturn -EINVAL;\n \n \tcpfl_rxq = dev->data->rx_queues[rx_queue_id];\n-\terr = idpf_vc_queue_switch(vport, rx_queue_id, true, false);\n+\tif (cpfl_rxq->hairpin_info.hairpin_q)\n+\t\terr = cpfl_switch_hairpin_rxtx_queue(cpfl_vport,\n+\t\t\t\t\t\t rx_queue_id - cpfl_vport->nb_data_txq,\n+\t\t\t\t\t\t true, false);\n+\telse\n+\t\terr = idpf_vc_queue_switch(vport, rx_queue_id, true, false);\n \tif (err != 0) {\n \t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u off\",\n \t\t\t rx_queue_id);\n@@ -1199,10 +1290,17 @@ cpfl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \t\tidpf_qc_single_rx_queue_reset(rxq);\n \t} else {\n \t\trxq->bufq1->ops->release_mbufs(rxq->bufq1);\n-\t\trxq->bufq2->ops->release_mbufs(rxq->bufq2);\n-\t\tidpf_qc_split_rx_queue_reset(rxq);\n+\t\tif (rxq->bufq2)\n+\t\t\trxq->bufq2->ops->release_mbufs(rxq->bufq2);\n+\t\tif (cpfl_rxq->hairpin_info.hairpin_q) {\n+\t\t\tcpfl_rx_hairpin_descq_reset(rxq);\n+\t\t\tcpfl_rx_hairpin_bufq_reset(rxq->bufq1);\n+\t\t} else {\n+\t\t\tidpf_qc_split_rx_queue_reset(rxq);\n+\t\t}\n \t}\n-\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\tif (!cpfl_rxq->hairpin_info.hairpin_q)\n+\t\tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n \n \treturn 0;\n }\n@@ -1221,7 +1319,12 @@ cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \n \tcpfl_txq = dev->data->tx_queues[tx_queue_id];\n \n-\terr = idpf_vc_queue_switch(vport, tx_queue_id, false, false);\n+\tif (cpfl_txq->hairpin_info.hairpin_q)\n+\t\terr = cpfl_switch_hairpin_rxtx_queue(cpfl_vport,\n+\t\t\t\t\t\t tx_queue_id - cpfl_vport->nb_data_txq,\n+\t\t\t\t\t\t false, false);\n+\telse\n+\t\terr = idpf_vc_queue_switch(vport, tx_queue_id, false, false);\n \tif (err != 0) {\n \t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u off\",\n \t\t\t tx_queue_id);\n@@ -1234,10 +1337,17 @@ cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n \t\tidpf_qc_single_tx_queue_reset(txq);\n \t} else {\n-\t\tidpf_qc_split_tx_descq_reset(txq);\n-\t\tidpf_qc_split_tx_complq_reset(txq->complq);\n+\t\tif (cpfl_txq->hairpin_info.hairpin_q) {\n+\t\t\tcpfl_tx_hairpin_descq_reset(txq);\n+\t\t\tcpfl_tx_hairpin_complq_reset(txq->complq);\n+\t\t} else {\n+\t\t\tidpf_qc_split_tx_descq_reset(txq);\n+\t\t\tidpf_qc_split_tx_complq_reset(txq->complq);\n+\t\t}\n \t}\n-\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\tif (!cpfl_txq->hairpin_info.hairpin_q)\n+\t\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n \n \treturn 0;\n }\n@@ -1257,10 +1367,17 @@ cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)\n void\n cpfl_stop_queues(struct rte_eth_dev *dev)\n {\n+\tstruct cpfl_vport *cpfl_vport =\n+\t\t(struct cpfl_vport *)dev->data->dev_private;\n \tstruct cpfl_rx_queue *cpfl_rxq;\n \tstruct cpfl_tx_queue *cpfl_txq;\n \tint i;\n \n+\tif (cpfl_vport->p2p_rx_bufq != NULL) {\n+\t\tif (cpfl_switch_hairpin_bufq_complq(cpfl_vport, false) != 0)\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to stop hairpin Tx complq and Rx bufq\");\n+\t}\n+\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\tcpfl_rxq = dev->data->rx_queues[i];\n \t\tif (cpfl_rxq == NULL)\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nindex b01ce5edf9..87603e161e 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.h\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -39,6 +39,17 @@\n \n #define CPFL_RX_BUF_STRIDE 64\n \n+/* The value written in the RX buffer queue tail register,\n+ * and in WritePTR field in the TX completion queue context,\n+ * must be a multiple of 8.\n+ */\n+#define CPFL_HAIRPIN_Q_TAIL_AUX_VALUE 8\n+\n+struct virtchnl2_p2p_rx_buf_desc {\n+\t__le64 reserve0;\n+\t__le64 pkt_addr; /* Packet buffer address */\n+};\n+\n struct cpfl_rxq_hairpin_info {\n \tbool hairpin_q;\t\t/* if rx queue is a hairpin queue */\n \tbool manual_bind;\t/* for cross vport */\n@@ -92,4 +103,7 @@ int cpfl_hairpin_tx_complq_config(struct cpfl_vport *cpfl_vport);\n int cpfl_hairpin_txq_config(struct idpf_vport *vport, struct cpfl_tx_queue *cpfl_txq);\n int cpfl_hairpin_rx_bufq_config(struct cpfl_vport *cpfl_vport);\n int cpfl_hairpin_rxq_config(struct idpf_vport *vport, struct cpfl_rx_queue *cpfl_rxq);\n+int cpfl_switch_hairpin_bufq_complq(struct cpfl_vport *cpfl_vport, bool on);\n+int cpfl_switch_hairpin_rxtx_queue(struct cpfl_vport *cpfl_vport, uint16_t qid,\n+\t\t\t\t bool rx, bool on);\n #endif /* _CPFL_RXTX_H_ */\n", "prefixes": [ "07/10" ] }