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GET /api/patches/126354/?format=api
{ "id": 126354, "url": "http://patchwork.dpdk.org/api/patches/126354/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230421065048.106899-11-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230421065048.106899-11-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230421065048.106899-11-beilei.xing@intel.com", "date": "2023-04-21T06:50:48", "name": "[10/10] net/cpfl: support hairpin bind/unbind", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5d13b1808e6efa42e99bb8e06db0fec90b66dd71", "submitter": { "id": 410, "url": "http://patchwork.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230421065048.106899-11-beilei.xing@intel.com/mbox/", "series": [ { "id": 27810, "url": "http://patchwork.dpdk.org/api/series/27810/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27810", "date": "2023-04-21T06:50:38", "name": "add hairpin queue support", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27810/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126354/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/126354/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0530A429A9;\n\tFri, 21 Apr 2023 09:15:05 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9081042D53;\n\tFri, 21 Apr 2023 09:14:11 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 1B92A42D5A\n for <dev@dpdk.org>; Fri, 21 Apr 2023 09:14:09 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2023 00:14:09 -0700", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by orsmga008.jf.intel.com with ESMTP; 21 Apr 2023 00:14:07 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682061250; x=1713597250;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=sbESs5t+E3FpWN47vka6v6FKJyjecGD2rZT8rP1aBpI=;\n b=VAGiiRXjW+XL177tPPjUlDJl1eUP+/AWp2cUXfQpPRTpFDm0VX4gvTGN\n N6RFqFCjImbeJoAQR4NdxF6Bc77JLB8mlSOD1dfp4Q3znu+MlI5txi8ek\n SJChjxRStoTVR0N63KKleZI1rnnzbASB9EoGe3c7yP2c5xP6pg4ONhm4/\n 3tMCbD0BQ7x/GBG9hrPWMwRuZ1xezeLRl8uq+TuntyIs7E+5SfZO/KIHY\n AjlXgfGG4ZgVW6tCRiNl1FVeToiF9OlPEl/bZoXhbmp6yIFuasJNAFzE7\n SzvlQJ4biB4EzjsCDSX53Uvj8Bx1Su0vnlj3A5japX/GPUNPxH8jrsEll g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10686\"; a=\"326260096\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"326260096\"", "E=McAfee;i=\"6600,9927,10686\"; a=\"722669146\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"722669146\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>,\n Xiao Wang <xiao.w.wang@intel.com>", "Subject": "[PATCH 10/10] net/cpfl: support hairpin bind/unbind", "Date": "Fri, 21 Apr 2023 06:50:48 +0000", "Message-Id": "<20230421065048.106899-11-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20230421065048.106899-1-beilei.xing@intel.com>", "References": "<20230421065048.106899-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nThis patch supports hairpin_bind/unbind ops.\n\nSigned-off-by: Xiao Wang <xiao.w.wang@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c | 137 +++++++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_rxtx.c | 28 +++++++\n drivers/net/cpfl/cpfl_rxtx.h | 2 +\n 3 files changed, 167 insertions(+)", "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 52c4ab601f..ddafc2f9e5 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -1107,6 +1107,141 @@ cpfl_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,\n \treturn j;\n }\n \n+static int\n+cpfl_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port)\n+{\n+\tstruct cpfl_vport *cpfl_tx_vport = dev->data->dev_private;\n+\tstruct idpf_vport *tx_vport = &cpfl_tx_vport->base;\n+\tstruct cpfl_vport *cpfl_rx_vport;\n+\tstruct cpfl_tx_queue *cpfl_txq;\n+\tstruct cpfl_rx_queue *cpfl_rxq;\n+\tstruct rte_eth_dev *peer_dev;\n+\tstruct idpf_vport *rx_vport;\n+\tint err = 0;\n+\tint i;\n+\n+\terr = cpfl_txq_hairpin_info_update(dev, rx_port);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to update Tx hairpin queue info.\");\n+\t\treturn err;\n+\t}\n+\n+\t/* configure hairpin queues */\n+\tfor (i = cpfl_tx_vport->nb_data_txq; i < dev->data->nb_tx_queues; i++) {\n+\t\tcpfl_txq = dev->data->tx_queues[i];\n+\t\terr = cpfl_hairpin_txq_config(tx_vport, cpfl_txq);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to configure hairpin Tx queue %u\", i);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\terr = cpfl_hairpin_tx_complq_config(cpfl_tx_vport);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to config Tx completion queue\");\n+\t\treturn err;\n+\t}\n+\n+\tpeer_dev = &rte_eth_devices[rx_port];\n+\tcpfl_rx_vport = (struct cpfl_vport *)peer_dev->data->dev_private;\n+\trx_vport = &cpfl_rx_vport->base;\n+\tcpfl_rxq_hairpin_mz_bind(peer_dev);\n+\n+\tfor (i = cpfl_rx_vport->nb_data_rxq; i < peer_dev->data->nb_rx_queues; i++) {\n+\t\tcpfl_rxq = peer_dev->data->rx_queues[i];\n+\t\terr = cpfl_hairpin_rxq_config(rx_vport, cpfl_rxq);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to configure hairpin Rx queue %u\", i);\n+\t\t\treturn err;\n+\t\t}\n+\t\terr = cpfl_rx_queue_init(peer_dev, i);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to init hairpin Rx queue %u\", i);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\terr = cpfl_hairpin_rx_bufq_config(cpfl_rx_vport);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Fail to config Rx buffer queue\");\n+\t\treturn err;\n+\t}\n+\n+\t/* enable hairpin queues */\n+\tfor (i = cpfl_tx_vport->nb_data_txq; i < dev->data->nb_tx_queues; i++) {\n+\t\tcpfl_txq = dev->data->tx_queues[i];\n+\t\terr = cpfl_switch_hairpin_rxtx_queue(cpfl_tx_vport,\n+\t\t\t\t\t\t i - cpfl_tx_vport->nb_data_txq,\n+\t\t\t\t\t\t false, true);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch hairpin TX queue %u on\",\n+\t\t\t\t i);\n+\t\t\treturn err;\n+\t\t}\n+\t\tcpfl_txq->base.q_started = true;\n+\t}\n+\n+\terr = cpfl_switch_hairpin_complq(cpfl_tx_vport, true);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to switch hairpin Tx complq\");\n+\t\treturn err;\n+\t}\n+\n+\tfor (i = cpfl_rx_vport->nb_data_rxq; i < peer_dev->data->nb_rx_queues; i++) {\n+\t\tcpfl_rxq = peer_dev->data->rx_queues[i];\n+\t\terr = cpfl_switch_hairpin_rxtx_queue(cpfl_rx_vport,\n+\t\t\t\t\t\t i - cpfl_rx_vport->nb_data_rxq,\n+\t\t\t\t\t\t true, true);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch hairpin RX queue %u on\",\n+\t\t\t\t i);\n+\t\t}\n+\t\tcpfl_rxq->base.q_started = true;\n+\t}\n+\n+\terr = cpfl_switch_hairpin_bufq(cpfl_rx_vport, true);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to switch hairpin Rx buffer queue\");\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port)\n+{\n+\tstruct cpfl_vport *cpfl_tx_vport = dev->data->dev_private;\n+\tstruct rte_eth_dev *peer_dev = &rte_eth_devices[rx_port];\n+\tstruct cpfl_vport *cpfl_rx_vport = peer_dev->data->dev_private;\n+\tstruct cpfl_tx_queue *cpfl_txq;\n+\tstruct cpfl_rx_queue *cpfl_rxq;\n+\tint i;\n+\n+\t/* disable hairpin queues */\n+\tfor (i = cpfl_tx_vport->nb_data_txq; i < dev->data->nb_tx_queues; i++) {\n+\t\tcpfl_txq = dev->data->tx_queues[i];\n+\t\tcpfl_switch_hairpin_rxtx_queue(cpfl_tx_vport,\n+\t\t\t\t\t i - cpfl_tx_vport->nb_data_txq,\n+\t\t\t\t\t false, false);\n+\t\tcpfl_txq->base.q_started = false;\n+\t}\n+\n+\tcpfl_switch_hairpin_complq(cpfl_tx_vport, false);\n+\n+\tfor (i = cpfl_rx_vport->nb_data_rxq; i < peer_dev->data->nb_rx_queues; i++) {\n+\t\tcpfl_rxq = peer_dev->data->rx_queues[i];\n+\t\tcpfl_switch_hairpin_rxtx_queue(cpfl_rx_vport,\n+\t\t\t\t\t i - cpfl_rx_vport->nb_data_rxq,\n+\t\t\t\t\t true, false);\n+\t\tcpfl_rxq->base.q_started = false;\n+\t}\n+\n+\tcpfl_switch_hairpin_bufq(cpfl_rx_vport, false);\n+\n+\treturn 0;\n+}\n+\n static const struct eth_dev_ops cpfl_eth_dev_ops = {\n \t.dev_configure\t\t\t= cpfl_dev_configure,\n \t.dev_close\t\t\t= cpfl_dev_close,\n@@ -1137,6 +1272,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = {\n \t.rx_hairpin_queue_setup\t\t= cpfl_rx_hairpin_queue_setup,\n \t.tx_hairpin_queue_setup\t\t= cpfl_tx_hairpin_queue_setup,\n \t.hairpin_get_peer_ports = cpfl_hairpin_get_peer_ports,\n+\t.hairpin_bind = cpfl_hairpin_bind,\n+\t.hairpin_unbind = cpfl_hairpin_unbind,\n };\n \n static int\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex ed2d100c35..e025bd014f 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -1030,6 +1030,34 @@ cpfl_switch_hairpin_bufq_complq(struct cpfl_vport *cpfl_vport, bool on)\n \treturn err;\n }\n \n+int\n+cpfl_switch_hairpin_complq(struct cpfl_vport *cpfl_vport, bool on)\n+{\n+\tstruct idpf_vport *vport = &cpfl_vport->base;\n+\tuint32_t type;\n+\tint err, queue_id;\n+\n+\ttype = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;\n+\tqueue_id = cpfl_vport->p2p_tx_complq->queue_id;\n+\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\n+\treturn err;\n+}\n+\n+int\n+cpfl_switch_hairpin_bufq(struct cpfl_vport *cpfl_vport, bool on)\n+{\n+\tstruct idpf_vport *vport = &cpfl_vport->base;\n+\tuint32_t type;\n+\tint err, queue_id;\n+\n+\ttype = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;\n+\tqueue_id = cpfl_vport->p2p_rx_bufq->queue_id;\n+\terr = idpf_vc_ena_dis_one_queue(vport, queue_id, type, on);\n+\n+\treturn err;\n+}\n+\n int\n cpfl_switch_hairpin_rxtx_queue(struct cpfl_vport *cpfl_vport, uint16_t logic_qid,\n \t\t\t bool rx, bool on)\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nindex 87603e161e..60308e16b2 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.h\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -104,6 +104,8 @@ int cpfl_hairpin_txq_config(struct idpf_vport *vport, struct cpfl_tx_queue *cpfl\n int cpfl_hairpin_rx_bufq_config(struct cpfl_vport *cpfl_vport);\n int cpfl_hairpin_rxq_config(struct idpf_vport *vport, struct cpfl_rx_queue *cpfl_rxq);\n int cpfl_switch_hairpin_bufq_complq(struct cpfl_vport *cpfl_vport, bool on);\n+int cpfl_switch_hairpin_complq(struct cpfl_vport *cpfl_vport, bool on);\n+int cpfl_switch_hairpin_bufq(struct cpfl_vport *cpfl_vport, bool on);\n int cpfl_switch_hairpin_rxtx_queue(struct cpfl_vport *cpfl_vport, uint16_t qid,\n \t\t\t\t bool rx, bool on);\n #endif /* _CPFL_RXTX_H_ */\n", "prefixes": [ "10/10" ] }