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GET /api/patches/126452/?format=api
{ "id": 126452, "url": "http://patchwork.dpdk.org/api/patches/126452/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230424091707.488045-5-wenjing.qiao@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230424091707.488045-5-wenjing.qiao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230424091707.488045-5-wenjing.qiao@intel.com", "date": "2023-04-24T09:17:04", "name": "[v3,4/7] common/idpf: enhance timestamp offload feature for ACC", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "991e82f02b6164b3f64a1ee6dc9be29d22ce0c89", "submitter": { "id": 2680, "url": "http://patchwork.dpdk.org/api/people/2680/?format=api", "name": "Wenjing Qiao", "email": "wenjing.qiao@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230424091707.488045-5-wenjing.qiao@intel.com/mbox/", "series": [ { "id": 27841, "url": "http://patchwork.dpdk.org/api/series/27841/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27841", "date": "2023-04-24T09:17:00", "name": "fix and enhance idpf and cpfl timestamp", "version": 3, "mbox": "http://patchwork.dpdk.org/series/27841/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126452/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/126452/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CB500429D9;\n\tMon, 24 Apr 2023 11:23:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4448742C76;\n\tMon, 24 Apr 2023 11:23:01 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id C89CC42D31;\n Mon, 24 Apr 2023 11:22:59 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Apr 2023 02:22:59 -0700", "from dpdk-wenjing-01.sh.intel.com ([10.67.118.239])\n by fmsmga001.fm.intel.com with ESMTP; 24 Apr 2023 02:22:57 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682328180; x=1713864180;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=D1xeMQBK3/UBoW/17IB/HQbbUD/ywjtGem9EljSzqaU=;\n b=E86t9ueB+4fMuN/nAl+ThlhqZXO/e87vicUx9C2O7i7U4HcnCHFAWzwh\n MOVYRXAg+zFJhL+B2dkbWrBZk6jmDLCvYX01xZKfzbzTgx2/qqD6cl2sI\n cNGF024fdGdHXHO+h48rHl2gOFboUCJoDThl0LZmQRKILnxqWcMVdiB7d\n Eaa0GSaP2icIPuSk9hk8e8U7ciGeZHfj/n4zjxBNFiDGEAjoxG2VAbNJB\n C465BPZy7m3sWCepqJ6mWFdoJ8vYfS4DgCeFbsJjBdKYqL/GUiRU/XZ7b\n dwPfsIuw6hD1v0a8CpFr+nmXBHdMVz6mfebunwOF019Ghog2K6+8DTwL5 w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10689\"; a=\"411680065\"", "E=Sophos;i=\"5.99,222,1677571200\"; d=\"scan'208\";a=\"411680065\"", "E=McAfee;i=\"6600,9927,10689\"; a=\"836895091\"", "E=Sophos;i=\"5.99,222,1677571200\"; d=\"scan'208\";a=\"836895091\"" ], "X-ExtLoop1": "1", "From": "Wenjing Qiao <wenjing.qiao@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com,\n Wenjing Qiao <wenjing.qiao@intel.com>,\n stable@dpdk.org", "Subject": "[PATCH v3 4/7] common/idpf: enhance timestamp offload feature for ACC", "Date": "Mon, 24 Apr 2023 05:17:04 -0400", "Message-Id": "<20230424091707.488045-5-wenjing.qiao@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230424091707.488045-1-wenjing.qiao@intel.com>", "References": "<20230421071603.55680-2-wenjing.qiao@intel.com>\n <20230424091707.488045-1-wenjing.qiao@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "For ACC, getting main time from MTS registers by shared memory.\n\nNotice: it is a workaround, and it will be removed after generic\nsolution are provided.\n\nFixes: 8c6098afa075 (\"common/idpf: add Rx/Tx data path\")\nCc: stable@dpdk.org\n\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\n---\n config/meson.build | 3 ++\n drivers/common/idpf/base/idpf_osdep.h | 48 ++++++++++++++++++++++++++\n drivers/common/idpf/idpf_common_rxtx.c | 30 +++++++++++++---\n meson_options.txt | 2 ++\n 4 files changed, 79 insertions(+), 4 deletions(-)", "diff": "diff --git a/config/meson.build b/config/meson.build\nindex fa730a1b14..8d74f301b4 100644\n--- a/config/meson.build\n+++ b/config/meson.build\n@@ -316,6 +316,9 @@ endif\n if get_option('mbuf_refcnt_atomic')\n dpdk_conf.set('RTE_MBUF_REFCNT_ATOMIC', true)\n endif\n+if get_option('enable_acc_timestamp')\n+ dpdk_conf.set('IDPF_ACC_TIMESTAMP', true)\n+endif\n dpdk_conf.set10('RTE_IOVA_IN_MBUF', get_option('enable_iova_as_pa'))\n \n compile_time_cpuflags = []\ndiff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h\nindex 99ae9cf60a..e634939a51 100644\n--- a/drivers/common/idpf/base/idpf_osdep.h\n+++ b/drivers/common/idpf/base/idpf_osdep.h\n@@ -24,6 +24,13 @@\n #include <rte_random.h>\n #include <rte_io.h>\n \n+#ifdef IDPF_ACC_TIMESTAMP\n+#include <stdio.h>\n+#include <fcntl.h>\n+#include <unistd.h>\n+#include <sys/mman.h>\n+#endif /* IDPF_ACC_TIMESTAMP */\n+\n #define INLINE inline\n #define STATIC static\n \n@@ -361,4 +368,45 @@ idpf_hweight32(u32 num)\n \n #endif\n \n+#ifdef IDPF_ACC_TIMESTAMP\n+#define IDPF_ACC_TIMESYNC_BASE_ADDR 0x480D500000\n+#define IDPF_ACC_GLTSYN_TIME_H (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x1C)\n+#define IDPF_ACC_GLTSYN_TIME_L (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x10)\n+\n+inline uint32_t\n+idpf_mmap_r32(uint64_t pa)\n+{\n+\tint fd;\n+\tvoid *bp, *vp;\n+\tuint32_t rval = 0xdeadbeef;\n+\tuint32_t ps, ml, of;\n+\n+\tfd = open(\"/dev/mem\", (O_RDWR | O_SYNC));\n+\tif (fd == -1) {\n+\t\tperror(\"/dev/mem\");\n+\t\treturn -1;\n+\t}\n+\tml = ps = getpagesize();\n+\tof = (uint32_t)pa & (ps - 1);\n+\tif (of + (sizeof(uint32_t) * 4) > ps)\n+\t\tml *= 2;\n+\tbp = mmap(NULL, ml, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, pa & ~(uint64_t)(ps - 1));\n+\tif (bp == MAP_FAILED) {\n+\t\tperror(\"mmap\");\n+\t\tgoto done;\n+\t}\n+\n+\tvp = (char *)bp + of;\n+\n+\trval = *(volatile uint32_t *)vp;\n+\tif (munmap(bp, ml) == -1)\n+\t\tperror(\"munmap\");\n+done:\n+\tclose(fd);\n+\n+\treturn rval;\n+}\n+\n+#endif /* IDPF_ACC_TIMESTAMP */\n+\n #endif /* _IDPF_OSDEP_H_ */\ndiff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c\nindex 19bcb94077..9c58f3fb11 100644\n--- a/drivers/common/idpf/idpf_common_rxtx.c\n+++ b/drivers/common/idpf/idpf_common_rxtx.c\n@@ -1582,12 +1582,36 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq)\n void\n idpf_dev_read_time_hw(void *cb_arg)\n {\n-#ifdef RTE_ARCH_X86_64\n \tstruct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;\n \tuint32_t hi, lo, lo2;\n \tint rc = 0;\n+#ifndef IDPF_ACC_TIMESTAMP\n \tstruct idpf_hw *hw = &ad->hw;\n+#endif /* !IDPF_ACC_TIMESTAMP */\n \n+#ifdef IDPF_ACC_TIMESTAMP\n+\n+\tlo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);\n+\thi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H);\n+\tDRV_LOG(DEBUG, \"lo : %X,\", lo);\n+\tDRV_LOG(DEBUG, \"hi : %X,\", hi);\n+\t/*\n+\t * On typical system, the delta between lo and lo2 is ~1000ns,\n+\t * so 10000 seems a large-enough but not overly-big guard band.\n+\t */\n+\tif (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))\n+\t\tlo2 = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);\n+\telse\n+\t\tlo2 = lo;\n+\n+\tif (lo2 < lo) {\n+\t\tlo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);\n+\t\thi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H);\n+\t}\n+\n+\tad->time_hw = ((uint64_t)hi << 32) | lo;\n+\n+#else /* !IDPF_ACC_TIMESTAMP */\n \tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n \tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,\n \t\t PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n@@ -1608,9 +1632,7 @@ idpf_dev_read_time_hw(void *cb_arg)\n \t}\n \n \tad->time_hw = ((uint64_t)hi << 32) | lo;\n-#else /* !RTE_ARCH_X86_64 */\n-\tad->time_hw = 0;\n-#endif /* RTE_ARCH_X86_64 */\n+#endif /* IDPF_ACC_TIMESTAMP */\n \n \t/* re-alarm watchdog */\n \trc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);\ndiff --git a/meson_options.txt b/meson_options.txt\nindex 82c8297065..31fc634aa0 100644\n--- a/meson_options.txt\n+++ b/meson_options.txt\n@@ -52,3 +52,5 @@ option('tests', type: 'boolean', value: true, description:\n 'build unit tests')\n option('use_hpet', type: 'boolean', value: false, description:\n 'use HPET timer in EAL')\n+option('enable_acc_timestamp', type: 'boolean', value: false, description:\n+ 'enable timestamp on ACC.')\n", "prefixes": [ "v3", "4/7" ] }