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GET /api/patches/126476/?format=api
{ "id": 126476, "url": "http://patchwork.dpdk.org/api/patches/126476/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230424122835.39493-4-sedara@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230424122835.39493-4-sedara@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230424122835.39493-4-sedara@marvell.com", "date": "2023-04-24T12:28:26", "name": "[v3,03/11] net/octeon_ep: support error propagation", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "47b2eefc5ea9457fa55dc7231d41d976f1d21c2e", "submitter": { "id": 2729, "url": "http://patchwork.dpdk.org/api/people/2729/?format=api", "name": "Sathesh B Edara", "email": "sedara@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230424122835.39493-4-sedara@marvell.com/mbox/", "series": [ { "id": 27844, "url": "http://patchwork.dpdk.org/api/series/27844/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27844", "date": "2023-04-24T12:28:24", "name": "extend octeon ep driver functionality", "version": 3, "mbox": "http://patchwork.dpdk.org/series/27844/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126476/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/126476/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E1498429DB;\n\tMon, 24 Apr 2023 15:55:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F1D7542B8C;\n\tMon, 24 Apr 2023 15:55:14 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id D3601410ED\n for <dev@dpdk.org>; Mon, 24 Apr 2023 15:55:11 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 33O7WYUr028418 for <dev@dpdk.org>; Mon, 24 Apr 2023 06:55:10 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3q5nfb1b6t-10\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 24 Apr 2023 06:55:10 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Mon, 24 Apr 2023 05:28:49 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Mon, 24 Apr 2023 05:28:49 -0700", "from localhost.marvell.com (unknown [10.106.27.249])\n by maili.marvell.com (Postfix) with ESMTP id 7F1FA3F70A0;\n Mon, 24 Apr 2023 05:28:49 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=2M1W+aEYz14v42PvW79iESxTmW7hZ91nQOlAL2e7r30=;\n b=QoZ87+uiXLHJai/q16hSHiusdMYVkaCHFOLoAJVz5o61LMq0z2LUSCVQhbom34EmWQcN\n CIL6x3r1M05ajdL3689lGCJ+9EOY/j73z6HBWapF+SD3oYQplfa+FckwshfGlkR8VLu1\n VwGT5h+V9ke6WWJykSBQOWtXxp4GSyhZo4RYSGg2LBDiG/jmsCN7jGuzGjQztOVpbBbl\n QX0mEusKputDi0/Zrw5SmMfB9wGBkHoLzMT8I2yhKJ2H/OUFTYITGehGNL0sVUSSwdII\n BccOoF1D68vq+eLFnYM3FXxLiTRemkgPPE64XK5YeBcCh1fgahw/gJykdM21OM707ULc Wg==", "From": "Sathesh Edara <sedara@marvell.com>", "To": "<sburla@marvell.com>, <jerinj@marvell.com>, <sedara@marvell.com>, \"Radha\n Mohan Chintakuntla\" <radhac@marvell.com>, Veerasenareddy Burru\n <vburru@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v3 03/11] net/octeon_ep: support error propagation", "Date": "Mon, 24 Apr 2023 05:28:26 -0700", "Message-ID": "<20230424122835.39493-4-sedara@marvell.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20230424122835.39493-1-sedara@marvell.com>", "References": "<20230405142537.1899973-2-sedara@marvell.com>\n <20230424122835.39493-1-sedara@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "QykaN8NwW4nTTiXjXDrgFwMm7vrxaYXx", "X-Proofpoint-GUID": "QykaN8NwW4nTTiXjXDrgFwMm7vrxaYXx", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-24_09,2023-04-21_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adds detection of loop limits being hit,\nand propagate errors up the call chain\nwhen this happens.\n\nSigned-off-by: Sathesh Edara <sedara@marvell.com>\n---\n drivers/net/octeon_ep/cnxk_ep_vf.c | 51 +++++++++++--------\n drivers/net/octeon_ep/otx2_ep_vf.c | 49 ++++++++++--------\n drivers/net/octeon_ep/otx_ep_common.h | 6 +--\n drivers/net/octeon_ep/otx_ep_ethdev.c | 27 +++++++---\n drivers/net/octeon_ep/otx_ep_rxtx.c | 51 +++++++++----------\n drivers/net/octeon_ep/otx_ep_vf.c | 71 +++++++++++++++++++--------\n 6 files changed, 155 insertions(+), 100 deletions(-)", "diff": "diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c\nindex 3427fb213b..1a92887109 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.c\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.c\n@@ -47,36 +47,43 @@ cnxk_ep_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)\n \toct_ep_write64(reg_val, otx_ep->hw_addr + CNXK_EP_R_OUT_CONTROL(q_no));\n }\n \n-static void\n+static int\n cnxk_ep_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)\n {\n \tuint64_t q_no = 0ull;\n \n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\tcnxk_ep_vf_setup_global_iq_reg(otx_ep, q_no);\n+\treturn 0;\n }\n \n-static void\n+static int\n cnxk_ep_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)\n {\n \tuint32_t q_no;\n \n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\tcnxk_ep_vf_setup_global_oq_reg(otx_ep, q_no);\n+\treturn 0;\n }\n \n-static void\n+static int\n cnxk_ep_vf_setup_device_regs(struct otx_ep_device *otx_ep)\n {\n-\tcnxk_ep_vf_setup_global_input_regs(otx_ep);\n-\tcnxk_ep_vf_setup_global_output_regs(otx_ep);\n+\tint ret;\n+\n+\tret = cnxk_ep_vf_setup_global_input_regs(otx_ep);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = cnxk_ep_vf_setup_global_output_regs(otx_ep);\n+\treturn ret;\n }\n \n-static void\n+static int\n cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n {\n \tstruct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];\n-\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \tvolatile uint64_t reg_val = 0ull;\n \n \treg_val = oct_ep_read64(otx_ep->hw_addr + CNXK_EP_R_IN_CONTROL(iq_no));\n@@ -91,9 +98,9 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\t} while ((!(reg_val & CNXK_EP_R_IN_CTL_IDLE)) && loop--);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"IDLE bit is not set\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \n \t/* Write the start of the input queue's ring and its size */\n@@ -115,9 +122,9 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\trte_delay_ms(1);\n \t} while (reg_val != 0 && loop--);\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"INST CNT REGISTER is not zero\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \n \t/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR\n@@ -125,14 +132,15 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t */\n \toct_ep_write64(OTX_EP_CLEAR_SDP_IN_INT_LVLS,\n \t\t otx_ep->hw_addr + CNXK_EP_R_IN_INT_LEVELS(iq_no));\n+\treturn 0;\n }\n \n-static void\n+static int\n cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n {\n \tvolatile uint64_t reg_val = 0ull;\n \tuint64_t oq_ctl = 0ull;\n-\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \tstruct otx_ep_droq *droq = otx_ep->droq[oq_no];\n \n \t/* Wait on IDLE to set to 1, supposed to configure BADDR\n@@ -145,9 +153,9 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"OUT CNT REGISTER value is zero\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \n \toct_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr + CNXK_EP_R_OUT_SLIST_BADDR(oq_no));\n@@ -181,9 +189,9 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"Packets credit register value is not cleared\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \n \totx_ep_dbg(\"SDP_R[%d]_credit:%x\", oq_no, rte_read32(droq->pkts_credit_reg));\n@@ -201,18 +209,19 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"Packets sent register value is not cleared\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \n \totx_ep_dbg(\"SDP_R[%d]_sent: %x\", oq_no, rte_read32(droq->pkts_sent_reg));\n+\t\treturn 0;\n }\n \n static int\n cnxk_ep_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n {\n-\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \tuint64_t reg_val = 0ull;\n \n \t/* Resetting doorbells during IQ enabling also to handle abrupt\n@@ -225,7 +234,7 @@ cnxk_ep_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"INSTR DBELL not coming back to 0\\n\");\n \t\treturn -EIO;\n \t}\ndiff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c\nindex 3c9a70157e..3ffc7275c7 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.c\n@@ -49,32 +49,39 @@ otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)\n \toct_ep_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n }\n \n-static void\n+static int\n otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)\n {\n \tuint64_t q_no = 0ull;\n \n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\totx2_vf_setup_global_iq_reg(otx_ep, q_no);\n+\treturn 0;\n }\n \n-static void\n+static int\n otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)\n {\n \tuint32_t q_no;\n \n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\totx2_vf_setup_global_oq_reg(otx_ep, q_no);\n+\treturn 0;\n }\n \n-static void\n+static int\n otx2_vf_setup_device_regs(struct otx_ep_device *otx_ep)\n {\n-\totx2_vf_setup_global_input_regs(otx_ep);\n-\totx2_vf_setup_global_output_regs(otx_ep);\n+\tint ret;\n+\n+\tret = otx2_vf_setup_global_input_regs(otx_ep);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = otx2_vf_setup_global_output_regs(otx_ep);\n+\treturn ret;\n }\n \n-static void\n+static int\n otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n {\n \tstruct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];\n@@ -92,9 +99,9 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\t} while ((!(reg_val & SDP_VF_R_IN_CTL_IDLE)) && loop--);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"IDLE bit is not set\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \n \t/* Write the start of the input queue's ring and its size */\n@@ -115,9 +122,9 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\trte_write32(reg_val, iq->inst_cnt_reg);\n \t} while (reg_val != 0 && loop--);\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"INST CNT REGISTER is not zero\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \n \t/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR\n@@ -125,14 +132,15 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t */\n \toct_ep_write64(OTX_EP_CLEAR_SDP_IN_INT_LVLS,\n \t\t otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));\n+\treturn 0;\n }\n \n-static void\n+static int\n otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n {\n \tvolatile uint64_t reg_val = 0ull;\n \tuint64_t oq_ctl = 0ull;\n-\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \tstruct otx_ep_droq *droq = otx_ep->droq[oq_no];\n \n \t/* Wait on IDLE to set to 1, supposed to configure BADDR\n@@ -145,9 +153,9 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"OUT CNT REGISTER value is zero\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \n \toct_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(oq_no));\n@@ -181,9 +189,9 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"Packets credit register value is not cleared\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \totx_ep_dbg(\"SDP_R[%d]_credit:%x\", oq_no, rte_read32(droq->pkts_credit_reg));\n \n@@ -200,17 +208,18 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"Packets sent register value is not cleared\\n\");\n-\t\treturn;\n+\t\treturn -EIO;\n \t}\n \totx_ep_dbg(\"SDP_R[%d]_sent: %x\", oq_no, rte_read32(droq->pkts_sent_reg));\n+\treturn 0;\n }\n \n static int\n otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n {\n-\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n+\tint loop = SDP_VF_BUSY_LOOP_COUNT;\n \tuint64_t reg_val = 0ull;\n \n \t/* Resetting doorbells during IQ enabling also to handle abrupt\n@@ -223,7 +232,7 @@ otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (!loop) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"INSTR DBELL not coming back to 0\\n\");\n \t\treturn -EIO;\n \t}\ndiff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h\nindex e4c92270d4..479bb1a1a0 100644\n--- a/drivers/net/octeon_ep/otx_ep_common.h\n+++ b/drivers/net/octeon_ep/otx_ep_common.h\n@@ -394,11 +394,11 @@ struct otx_ep_sriov_info {\n \n /* Required functions for each VF device */\n struct otx_ep_fn_list {\n-\tvoid (*setup_iq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);\n+\tint (*setup_iq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);\n \n-\tvoid (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);\n+\tint (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);\n \n-\tvoid (*setup_device_regs)(struct otx_ep_device *otx_ep);\n+\tint (*setup_device_regs)(struct otx_ep_device *otx_ep);\n \n \tint (*enable_io_queues)(struct otx_ep_device *otx_ep);\n \tvoid (*disable_io_queues)(struct otx_ep_device *otx_ep);\ndiff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c\nindex b23d52ff84..5677a2d6a6 100644\n--- a/drivers/net/octeon_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c\n@@ -151,13 +151,17 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \telse if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||\n \t\t otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||\n \t\t otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||\n-\t\t otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF)\n-\t\totx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;\n-\telse if (otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||\n+\t\t otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF ||\n+\t\t otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||\n \t\t otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF ||\n \t\t otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF ||\n-\t\t otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF)\n+\t\t otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) {\n \t\totx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;\n+\t} else {\n+\t\totx_ep_err(\"Invalid chip_id\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto setup_fail;\n+\t}\n \tethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);\n \totx_epvf->max_rx_queues = ethdev_queues;\n \totx_epvf->max_tx_queues = ethdev_queues;\n@@ -489,6 +493,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\trte_eth_copy_pci_info(eth_dev, pdev);\n \totx_epvf->eth_dev = eth_dev;\n \totx_epvf->port_id = eth_dev->data->port_id;\n \teth_dev->dev_ops = &otx_ep_eth_dev_ops;\n@@ -503,7 +508,8 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \totx_epvf->hw_addr = pdev->mem_resource[0].addr;\n \totx_epvf->pdev = pdev;\n \n-\totx_epdev_init(otx_epvf);\n+\tif (otx_epdev_init(otx_epvf))\n+\t\treturn -ENOMEM;\n \tif (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||\n \t otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||\n \t otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||\n@@ -511,11 +517,16 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||\n \t otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF ||\n \t otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF ||\n-\t otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF)\n+\t otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) {\n \t\totx_epvf->pkind = SDP_OTX2_PKIND_FS0;\n-\telse\n+\t\totx_ep_info(\"using pkind %d\\n\", otx_epvf->pkind);\n+\t} else if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF) {\n \t\totx_epvf->pkind = SDP_PKIND;\n-\totx_ep_info(\"using pkind %d\\n\", otx_epvf->pkind);\n+\t\totx_ep_info(\"Using pkind %d.\\n\", otx_epvf->pkind);\n+\t} else {\n+\t\totx_ep_err(\"Invalid chip id\\n\");\n+\t\treturn -EINVAL;\n+\t}\n \n \treturn 0;\n }\ndiff --git a/drivers/net/octeon_ep/otx_ep_rxtx.c b/drivers/net/octeon_ep/otx_ep_rxtx.c\nindex 6912ca2401..9712e6cce6 100644\n--- a/drivers/net/octeon_ep/otx_ep_rxtx.c\n+++ b/drivers/net/octeon_ep/otx_ep_rxtx.c\n@@ -3,7 +3,7 @@\n */\n \n #include <unistd.h>\n-\n+#include <assert.h>\n #include <rte_eal.h>\n #include <rte_mempool.h>\n #include <rte_mbuf.h>\n@@ -81,6 +81,7 @@ otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,\n \tconst struct otx_ep_config *conf;\n \tstruct otx_ep_instr_queue *iq;\n \tuint32_t q_size;\n+\tint ret;\n \n \tconf = otx_ep->conf;\n \tiq = otx_ep->instr_queue[iq_no];\n@@ -140,7 +141,9 @@ otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,\n \tiq->iqcmd_64B = (conf->iq.instr_type == 64);\n \n \t/* Set up IQ registers */\n-\totx_ep->fn_list.setup_iq_regs(otx_ep, iq_no);\n+\tret = otx_ep->fn_list.setup_iq_regs(otx_ep, iq_no);\n+\tif (ret)\n+\t\treturn ret;\n \n \treturn 0;\n \n@@ -271,6 +274,7 @@ otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no,\n \tuint32_t c_refill_threshold;\n \tstruct otx_ep_droq *droq;\n \tuint32_t desc_ring_size;\n+\tint ret;\n \n \totx_ep_info(\"OQ[%d] Init start\\n\", q_no);\n \n@@ -318,7 +322,9 @@ otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no,\n \tdroq->refill_threshold = c_refill_threshold;\n \n \t/* Set up OQ registers */\n-\totx_ep->fn_list.setup_oq_regs(otx_ep, q_no);\n+\tret = otx_ep->fn_list.setup_oq_regs(otx_ep, q_no);\n+\tif (ret)\n+\t\treturn ret;\n \n \totx_ep->io_qmask.oq |= (1ull << q_no);\n \n@@ -852,19 +858,15 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,\n \t\t * droq->pkts_pending);\n \t\t */\n \t\tdroq->stats.pkts_delayed_data++;\n-\t\twhile (retry && !info->length)\n+\t\twhile (retry && !info->length) {\n \t\t\tretry--;\n+\t\t\trte_delay_us_block(50);\n+\t\t}\n \t\tif (!retry && !info->length) {\n \t\t\totx_ep_err(\"OCTEON DROQ[%d]: read_idx: %d; Retry failed !!\\n\",\n \t\t\t\t droq->q_no, droq->read_idx);\n \t\t\t/* May be zero length packet; drop it */\n-\t\t\trte_pktmbuf_free(droq_pkt);\n-\t\t\tdroq->recv_buf_list[droq->read_idx] = NULL;\n-\t\t\tdroq->read_idx = otx_ep_incr_index(droq->read_idx, 1,\n-\t\t\t\t\t\t\t droq->nb_desc);\n-\t\t\tdroq->stats.dropped_zlp++;\n-\t\t\tdroq->refill_count++;\n-\t\t\tgoto oq_read_fail;\n+\t\t\tassert(0);\n \t\t}\n \t}\n \tif (next_fetch) {\n@@ -938,6 +940,7 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,\n \t\t\t\tlast_buf = droq_pkt;\n \t\t\t} else {\n \t\t\t\totx_ep_err(\"no buf\\n\");\n+\t\t\t\tassert(0);\n \t\t\t}\n \n \t\t\tpkt_len += cpy_len;\n@@ -953,16 +956,7 @@ otx_ep_droq_read_packet(struct otx_ep_device *otx_ep,\n \tdroq_pkt->l3_len = hdr_lens.l3_len;\n \tdroq_pkt->l4_len = hdr_lens.l4_len;\n \n-\tif (droq_pkt->nb_segs > 1 &&\n-\t !(otx_ep->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)) {\n-\t\trte_pktmbuf_free(droq_pkt);\n-\t\tgoto oq_read_fail;\n-\t}\n-\n \treturn droq_pkt;\n-\n-oq_read_fail:\n-\treturn NULL;\n }\n \n static inline uint32_t\n@@ -992,6 +986,7 @@ otx_ep_recv_pkts(void *rx_queue,\n \tstruct rte_mbuf *oq_pkt;\n \n \tuint32_t pkts = 0;\n+\tuint32_t valid_pkts = 0;\n \tuint32_t new_pkts = 0;\n \tint next_fetch;\n \n@@ -1019,14 +1014,15 @@ otx_ep_recv_pkts(void *rx_queue,\n \t\t\t\t \"last_pkt_count %\" PRIu64 \"new_pkts %d.\\n\",\n \t\t\t\t droq->pkts_pending, droq->last_pkt_count,\n \t\t\t\t new_pkts);\n-\t\t\tdroq->pkts_pending -= pkts;\n \t\t\tdroq->stats.rx_err++;\n-\t\t\tgoto finish;\n+\t\t\tcontinue;\n+\t\t} else {\n+\t\t\trx_pkts[valid_pkts] = oq_pkt;\n+\t\t\tvalid_pkts++;\n+\t\t\t/* Stats */\n+\t\t\tdroq->stats.pkts_received++;\n+\t\t\tdroq->stats.bytes_received += oq_pkt->pkt_len;\n \t\t}\n-\t\trx_pkts[pkts] = oq_pkt;\n-\t\t/* Stats */\n-\t\tdroq->stats.pkts_received++;\n-\t\tdroq->stats.bytes_received += oq_pkt->pkt_len;\n \t}\n \tdroq->pkts_pending -= pkts;\n \n@@ -1053,6 +1049,5 @@ otx_ep_recv_pkts(void *rx_queue,\n \n \t\trte_write32(0, droq->pkts_credit_reg);\n \t}\n-finish:\n-\treturn pkts;\n+\treturn valid_pkts;\n }\ndiff --git a/drivers/net/octeon_ep/otx_ep_vf.c b/drivers/net/octeon_ep/otx_ep_vf.c\nindex 96366b2a7f..4f3538146b 100644\n--- a/drivers/net/octeon_ep/otx_ep_vf.c\n+++ b/drivers/net/octeon_ep/otx_ep_vf.c\n@@ -12,10 +12,11 @@\n #include \"otx_ep_vf.h\"\n \n \n-static void\n+static int\n otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)\n {\n \tvolatile uint64_t reg_val = 0ull;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \n \t/* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs\n \t * IS_64B is by default enabled.\n@@ -33,8 +34,11 @@ otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)\n \t\tdo {\n \t\t\treg_val = rte_read64(otx_ep->hw_addr +\n \t\t\t\t\t OTX_EP_R_IN_CONTROL(q_no));\n-\t\t} while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));\n+\t\t} while (!(reg_val & OTX_EP_R_IN_CTL_IDLE) && loop--);\n+\t\tif (loop < 0)\n+\t\t\treturn -EIO;\n \t}\n+\treturn 0;\n }\n \n static void\n@@ -60,13 +64,18 @@ otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)\n \totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no));\n }\n \n-static void\n+static int\n otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep)\n {\n \tuint64_t q_no = 0ull;\n+\tint ret = 0;\n \n-\tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n-\t\totx_ep_setup_global_iq_reg(otx_ep, q_no);\n+\tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++) {\n+\t\tret = otx_ep_setup_global_iq_reg(otx_ep, q_no);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\treturn 0;\n }\n \n static void\n@@ -78,18 +87,24 @@ otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep)\n \t\totx_ep_setup_global_oq_reg(otx_ep, q_no);\n }\n \n-static void\n+static int\n otx_ep_setup_device_regs(struct otx_ep_device *otx_ep)\n {\n-\totx_ep_setup_global_input_regs(otx_ep);\n+\tint ret;\n+\n+\tret = otx_ep_setup_global_input_regs(otx_ep);\n+\tif (ret)\n+\t\treturn ret;\n \totx_ep_setup_global_output_regs(otx_ep);\n+\treturn 0;\n }\n \n-static void\n+static int\n otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n {\n \tstruct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];\n \tvolatile uint64_t reg_val = 0ull;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \n \treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(iq_no));\n \n@@ -100,7 +115,9 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\tdo {\n \t\t\treg_val = rte_read64(otx_ep->hw_addr +\n \t\t\t\t\t OTX_EP_R_IN_CONTROL(iq_no));\n-\t\t} while (!(reg_val & OTX_EP_R_IN_CTL_IDLE));\n+\t\t} while (!(reg_val & OTX_EP_R_IN_CTL_IDLE) && loop--);\n+\t\tif (loop < 0)\n+\t\t\treturn -EIO;\n \t}\n \n \t/* Write the start of the input queue's ring and its size */\n@@ -120,10 +137,13 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \totx_ep_dbg(\"InstQ[%d]:dbell reg @ 0x%p inst_cnt_reg @ 0x%p\\n\",\n \t\t iq_no, iq->doorbell_reg, iq->inst_cnt_reg);\n \n+\tloop = OTX_EP_BUSY_LOOP_COUNT;\n \tdo {\n \t\treg_val = rte_read32(iq->inst_cnt_reg);\n \t\trte_write32(reg_val, iq->inst_cnt_reg);\n-\t} while (reg_val != 0);\n+\t} while ((reg_val != 0) && loop--);\n+\tif (loop < 0)\n+\t\treturn -EIO;\n \n \t/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR\n \t * to raise\n@@ -133,13 +153,15 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t */\n \totx_ep_write64(OTX_EP_CLEAR_IN_INT_LVLS, otx_ep->hw_addr,\n \t\t OTX_EP_R_IN_INT_LEVELS(iq_no));\n+\treturn 0;\n }\n \n-static void\n+static int\n otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n {\n \tvolatile uint64_t reg_val = 0ull;\n \tuint64_t oq_ctl = 0ull;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \n \tstruct otx_ep_droq *droq = otx_ep->droq[oq_no];\n \n@@ -150,10 +172,12 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \n \treg_val = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CONTROL(oq_no));\n \n-\twhile (!(reg_val & OTX_EP_R_OUT_CTL_IDLE)) {\n+\twhile (!(reg_val & OTX_EP_R_OUT_CTL_IDLE) && loop--) {\n \t\treg_val = rte_read64(otx_ep->hw_addr +\n \t\t\t\t OTX_EP_R_OUT_CONTROL(oq_no));\n \t}\n+\tif (loop < 0)\n+\t\treturn -EIO;\n \n \totx_ep_write64(droq->desc_ring_dma, otx_ep->hw_addr,\n \t\t OTX_EP_R_OUT_SLIST_BADDR(oq_no));\n@@ -180,11 +204,14 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\t OTX_EP_R_OUT_INT_LEVELS(oq_no));\n \n \t/* Clear the OQ doorbell */\n+\tloop = OTX_EP_BUSY_LOOP_COUNT;\n \trte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);\n-\twhile ((rte_read32(droq->pkts_credit_reg) != 0ull)) {\n+\twhile ((rte_read32(droq->pkts_credit_reg) != 0ull) && loop--) {\n \t\trte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);\n \t\trte_delay_ms(1);\n \t}\n+\tif (loop < 0)\n+\t\treturn -EIO;\n \totx_ep_dbg(\"OTX_EP_R[%d]_credit:%x\\n\", oq_no,\n \t\t rte_read32(droq->pkts_credit_reg));\n \n@@ -195,18 +222,22 @@ otx_ep_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \totx_ep_dbg(\"OTX_EP_R[%d]_sent: %x\\n\", oq_no,\n \t\t rte_read32(droq->pkts_sent_reg));\n \n-\twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {\n+\tloop = OTX_EP_BUSY_LOOP_COUNT;\n+\twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull) && loop--) {\n \t\treg_val = rte_read32(droq->pkts_sent_reg);\n \t\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n \t\trte_delay_ms(1);\n \t}\n+\tif (loop < 0)\n+\t\treturn -EIO;\n+\treturn 0;\n }\n \n static int\n otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n {\n-\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n-\tuint64_t reg_val = 0ull;\n+\tvolatile uint64_t reg_val = 0ull;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \n \t/* Resetting doorbells during IQ enabling also to handle abrupt\n \t * guest reboot. IQ reset does not clear the doorbells.\n@@ -219,7 +250,7 @@ otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n \t\trte_delay_ms(1);\n \t}\n \n-\tif (loop == 0) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"dbell reset failed\\n\");\n \t\treturn -EIO;\n \t}\n@@ -238,8 +269,8 @@ otx_ep_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)\n static int\n otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)\n {\n-\tuint64_t reg_val = 0ull;\n-\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t reg_val = 0ull;\n+\tint loop = OTX_EP_BUSY_LOOP_COUNT;\n \n \t/* Resetting doorbells during IQ enabling also to handle abrupt\n \t * guest reboot. IQ reset does not clear the doorbells.\n@@ -250,7 +281,7 @@ otx_ep_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)\n \t\t OTX_EP_R_OUT_SLIST_DBELL(q_no))) != 0ull) && loop--) {\n \t\trte_delay_ms(1);\n \t}\n-\tif (loop == 0) {\n+\tif (loop < 0) {\n \t\totx_ep_err(\"dbell reset failed\\n\");\n \t\treturn -EIO;\n \t}\n", "prefixes": [ "v3", "03/11" ] }