Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/126545/?format=api
{ "id": 126545, "url": "http://patchwork.dpdk.org/api/patches/126545/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230426102259.205992-13-wenjing.qiao@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230426102259.205992-13-wenjing.qiao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230426102259.205992-13-wenjing.qiao@intel.com", "date": "2023-04-26T10:22:56", "name": "[v3,12/15] common/idpf/base: replace MAKEMASK to IDPF_M", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2f7ac4f9708916959c400b5e620c4788d4e2c3fa", "submitter": { "id": 2680, "url": "http://patchwork.dpdk.org/api/people/2680/?format=api", "name": "Wenjing Qiao", "email": "wenjing.qiao@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230426102259.205992-13-wenjing.qiao@intel.com/mbox/", "series": [ { "id": 27874, "url": "http://patchwork.dpdk.org/api/series/27874/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27874", "date": "2023-04-26T10:22:44", "name": "update idpf base code", "version": 3, "mbox": "http://patchwork.dpdk.org/series/27874/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126545/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/126545/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A7A9842A02;\n\tWed, 26 Apr 2023 12:29:16 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 84BB442D77;\n\tWed, 26 Apr 2023 12:28:20 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 8040F42D40\n for <dev@dpdk.org>; Wed, 26 Apr 2023 12:28:17 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 03:28:17 -0700", "from dpdk-wenjing-01.sh.intel.com ([10.67.118.239])\n by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:15 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682504897; x=1714040897;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=SXo7/Pjj7jQW2OleKGH8O2pr2IQLIl9HMg3yjKXI2e4=;\n b=A8JNtp2ZFxyLhJT2TvNvLL7f5lQcN2TJvubR7J2pgWkvviOCwRGSTyNT\n I4nmQFCKi4KlXIcrki8eUr3xn86cgfXdaOsS1fl07/nTIHsudw7eHrS6B\n jyYd39pSDbcHgx1RCAOg9rz4E2z9NbpXl+/bYLgorc4cm2RSVKXzBjq5M\n lXRpbpNy7LNrWaStuEvyWYjh9Lr4p691OUbp/n2TqxmUFiM2QjObuhTvz\n oxoaY/0Az8dXSxLnI4rTLXSCLiWrxMo1PqvpRYnomHyust4o1ZCRJms/h\n xhkJkUreJl8dkYl2VQITRRh3X9Vb5LFBat3zCfkyK6mx93v5MNz18rBy4 w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10691\"; a=\"327391572\"", "E=Sophos;i=\"5.99,227,1677571200\"; d=\"scan'208\";a=\"327391572\"", "E=McAfee;i=\"6600,9927,10691\"; a=\"1023552761\"", "E=Sophos;i=\"5.99,227,1677571200\"; d=\"scan'208\";a=\"1023552761\"" ], "X-ExtLoop1": "1", "From": "Wenjing Qiao <wenjing.qiao@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com,\n Wenjing Qiao <wenjing.qiao@intel.com>,\n Priyalee Kushwaha <priyalee.kushwaha@intel.com>", "Subject": "[PATCH v3 12/15] common/idpf/base: replace MAKEMASK to IDPF_M", "Date": "Wed, 26 Apr 2023 06:22:56 -0400", "Message-Id": "<20230426102259.205992-13-wenjing.qiao@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230426102259.205992-1-wenjing.qiao@intel.com>", "References": "<20230421084043.135503-2-wenjing.qiao@intel.com>\n <20230426102259.205992-1-wenjing.qiao@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Replace MAKEMASK to IDPF_M to avoid conflicts with MAKEMASK\nredefinition from various subcomponents.\n\nSigned-off-by: Priyalee Kushwaha <priyalee.kushwaha@intel.com>\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\n---\n drivers/common/idpf/base/idpf_controlq.h | 3 --\n drivers/common/idpf/base/idpf_lan_pf_regs.h | 26 +++++------\n drivers/common/idpf/base/idpf_lan_txrx.h | 46 +++++++++----------\n drivers/common/idpf/base/idpf_lan_vf_regs.h | 16 +++----\n drivers/common/idpf/base/idpf_osdep.h | 2 +\n drivers/common/idpf/base/idpf_type.h | 2 -\n drivers/common/idpf/base/virtchnl2_lan_desc.h | 28 +++++------\n 7 files changed, 60 insertions(+), 63 deletions(-)", "diff": "diff --git a/drivers/common/idpf/base/idpf_controlq.h b/drivers/common/idpf/base/idpf_controlq.h\nindex e7b0d803b3..47bffcf79f 100644\n--- a/drivers/common/idpf/base/idpf_controlq.h\n+++ b/drivers/common/idpf/base/idpf_controlq.h\n@@ -97,9 +97,6 @@ struct idpf_ctlq_desc {\n #define IDPF_CTLQ_FLAG_VFC\tBIT(IDPF_CTLQ_FLAG_VFC_S)\t/* 0x800 */\n #define IDPF_CTLQ_FLAG_BUF\tBIT(IDPF_CTLQ_FLAG_BUF_S)\t/* 0x1000 */\n \n-/* Host ID is a special field that has 3b and not a 1b flag */\n-#define IDPF_CTLQ_FLAG_HOST_ID_M MAKE_MASK(0x7000UL, IDPF_CTLQ_FLAG_HOST_ID_S)\n-\n struct idpf_mbxq_desc {\n \tu8 pad[8];\t\t/* CTLQ flags/opcode/len/retval fields */\n \tu32 chnl_opcode;\t/* avoid confusion with desc->opcode */\ndiff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h\nindex 7f731ec3d6..1c665d1f3b 100644\n--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h\n@@ -24,7 +24,7 @@\n #define PF_FW_ARQBAH\t\t\t(PF_FW_BASE + 0x4)\n #define PF_FW_ARQLEN\t\t\t(PF_FW_BASE + 0x8)\n #define PF_FW_ARQLEN_ARQLEN_S\t\t0\n-#define PF_FW_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x1FFF, PF_FW_ARQLEN_ARQLEN_S)\n+#define PF_FW_ARQLEN_ARQLEN_M\t\tIDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S)\n #define PF_FW_ARQLEN_ARQVFE_S\t\t28\n #define PF_FW_ARQLEN_ARQVFE_M\t\tBIT(PF_FW_ARQLEN_ARQVFE_S)\n #define PF_FW_ARQLEN_ARQOVFL_S\t\t29\n@@ -35,14 +35,14 @@\n #define PF_FW_ARQLEN_ARQENABLE_M\tBIT(PF_FW_ARQLEN_ARQENABLE_S)\n #define PF_FW_ARQH\t\t\t(PF_FW_BASE + 0xC)\n #define PF_FW_ARQH_ARQH_S\t\t0\n-#define PF_FW_ARQH_ARQH_M\t\tMAKEMASK(0x1FFF, PF_FW_ARQH_ARQH_S)\n+#define PF_FW_ARQH_ARQH_M\t\tIDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S)\n #define PF_FW_ARQT\t\t\t(PF_FW_BASE + 0x10)\n \n #define PF_FW_ATQBAL\t\t\t(PF_FW_BASE + 0x14)\n #define PF_FW_ATQBAH\t\t\t(PF_FW_BASE + 0x18)\n #define PF_FW_ATQLEN\t\t\t(PF_FW_BASE + 0x1C)\n #define PF_FW_ATQLEN_ATQLEN_S\t\t0\n-#define PF_FW_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, PF_FW_ATQLEN_ATQLEN_S)\n+#define PF_FW_ATQLEN_ATQLEN_M\t\tIDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S)\n #define PF_FW_ATQLEN_ATQVFE_S\t\t28\n #define PF_FW_ATQLEN_ATQVFE_M\t\tBIT(PF_FW_ATQLEN_ATQVFE_S)\n #define PF_FW_ATQLEN_ATQOVFL_S\t\t29\n@@ -53,7 +53,7 @@\n #define PF_FW_ATQLEN_ATQENABLE_M\tBIT(PF_FW_ATQLEN_ATQENABLE_S)\n #define PF_FW_ATQH\t\t\t(PF_FW_BASE + 0x20)\n #define PF_FW_ATQH_ATQH_S\t\t0\n-#define PF_FW_ATQH_ATQH_M\t\tMAKEMASK(0x3FF, PF_FW_ATQH_ATQH_S)\n+#define PF_FW_ATQH_ATQH_M\t\tIDPF_M(0x3FF, PF_FW_ATQH_ATQH_S)\n #define PF_FW_ATQT\t\t\t(PF_FW_BASE + 0x24)\n \n /* Interrupts */\n@@ -66,7 +66,7 @@\n #define PF_GLINT_DYN_CTL_SWINT_TRIG_S\t2\n #define PF_GLINT_DYN_CTL_SWINT_TRIG_M\tBIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S)\n #define PF_GLINT_DYN_CTL_ITR_INDX_S\t3\n-#define PF_GLINT_DYN_CTL_ITR_INDX_M\tMAKEMASK(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S)\n+#define PF_GLINT_DYN_CTL_ITR_INDX_M\tIDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S)\n #define PF_GLINT_DYN_CTL_INTERVAL_S\t5\n #define PF_GLINT_DYN_CTL_INTERVAL_M\tBIT(PF_GLINT_DYN_CTL_INTERVAL_S)\n #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S\t24\n@@ -86,13 +86,13 @@\n #define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))\n #define PF_GLINT_ITR_MAX_INDEX\t\t2\n #define PF_GLINT_ITR_INTERVAL_S\t\t0\n-#define PF_GLINT_ITR_INTERVAL_M\t\tMAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S)\n+#define PF_GLINT_ITR_INTERVAL_M\t\tIDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S)\n \n /* Timesync registers */\n #define PF_TIMESYNC_BASE\t\t0x08404000\n #define PF_GLTSYN_CMD_SYNC\t\t(PF_TIMESYNC_BASE)\n #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S\t0\n-#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M\tMAKEMASK(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S)\n+#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M\tIDPF_M(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S)\n #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S\t2\n #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M\tBIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S)\n #define PF_GLTSYN_SHTIME_0\t\t(PF_TIMESYNC_BASE + 0x4)\n@@ -104,23 +104,23 @@\n /* Generic registers */\n #define PF_INT_DIR_OICR_ENA\t\t0x08406000\n #define PF_INT_DIR_OICR_ENA_S\t\t0\n-#define PF_INT_DIR_OICR_ENA_M\tMAKEMASK(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S)\n+#define PF_INT_DIR_OICR_ENA_M\tIDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S)\n #define PF_INT_DIR_OICR\t\t\t0x08406004\n #define PF_INT_DIR_OICR_TSYN_EVNT\t0\n #define PF_INT_DIR_OICR_PHY_TS_0\tBIT(1)\n #define PF_INT_DIR_OICR_PHY_TS_1\tBIT(2)\n #define PF_INT_DIR_OICR_CAUSE\t\t0x08406008\n #define PF_INT_DIR_OICR_CAUSE_CAUSE_S\t0\n-#define PF_INT_DIR_OICR_CAUSE_CAUSE_M\tMAKEMASK(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S)\n+#define PF_INT_DIR_OICR_CAUSE_CAUSE_M\tIDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S)\n #define PF_INT_PBA_CLEAR\t\t0x0840600C\n \n #define PF_FUNC_RID\t\t\t0x08406010\n #define PF_FUNC_RID_FUNCTION_NUMBER_S\t0\n-#define PF_FUNC_RID_FUNCTION_NUMBER_M\tMAKEMASK(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S)\n+#define PF_FUNC_RID_FUNCTION_NUMBER_M\tIDPF_M(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S)\n #define PF_FUNC_RID_DEVICE_NUMBER_S\t3\n-#define PF_FUNC_RID_DEVICE_NUMBER_M\tMAKEMASK(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S)\n+#define PF_FUNC_RID_DEVICE_NUMBER_M\tIDPF_M(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S)\n #define PF_FUNC_RID_BUS_NUMBER_S\t8\n-#define PF_FUNC_RID_BUS_NUMBER_M\tMAKEMASK(0xFF, PF_FUNC_RID_BUS_NUMBER_S)\n+#define PF_FUNC_RID_BUS_NUMBER_M\tIDPF_M(0xFF, PF_FUNC_RID_BUS_NUMBER_S)\n \n /* Reset registers */\n #define PFGEN_RTRIG\t\t\t0x08407000\n@@ -132,7 +132,7 @@\n #define PFGEN_RTRIG_IMCR_M\t\tBIT(2)\n #define PFGEN_RSTAT\t\t\t0x08407008 /* PFR Status */\n #define PFGEN_RSTAT_PFR_STATE_S\t\t0\n-#define PFGEN_RSTAT_PFR_STATE_M\t\tMAKEMASK(0x3, PFGEN_RSTAT_PFR_STATE_S)\n+#define PFGEN_RSTAT_PFR_STATE_M\t\tIDPF_M(0x3, PFGEN_RSTAT_PFR_STATE_S)\n #define PFGEN_CTRL\t\t\t0x0840700C\n #define PFGEN_CTRL_PFSWR\t\tBIT(0)\n \ndiff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h\nindex 98484b267c..82742857be 100644\n--- a/drivers/common/idpf/base/idpf_lan_txrx.h\n+++ b/drivers/common/idpf/base/idpf_lan_txrx.h\n@@ -68,9 +68,9 @@ enum idpf_rss_hash {\n #define IDPF_TXD_COMPLQ_GEN_M\t\tBIT_ULL(IDPF_TXD_COMPLQ_GEN_S)\n #define IDPF_TXD_COMPLQ_COMPL_TYPE_S\t11\n #define IDPF_TXD_COMPLQ_COMPL_TYPE_M\t\\\n-\tMAKEMASK(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S)\n+\tIDPF_M(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S)\n #define IDPF_TXD_COMPLQ_QID_S\t0\n-#define IDPF_TXD_COMPLQ_QID_M\t\tMAKEMASK(0x3FFUL, IDPF_TXD_COMPLQ_QID_S)\n+#define IDPF_TXD_COMPLQ_QID_M\t\tIDPF_M(0x3FFUL, IDPF_TXD_COMPLQ_QID_S)\n \n /* For base mode TX descriptors */\n \n@@ -100,29 +100,29 @@ enum idpf_rss_hash {\n \n #define IDPF_TXD_CTX_QW1_MSS_S\t\t50\n #define IDPF_TXD_CTX_QW1_MSS_M\t\t\\\n-\tMAKEMASK(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S)\n+\tIDPF_M(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S)\n #define IDPF_TXD_CTX_QW1_TSO_LEN_S\t30\n #define IDPF_TXD_CTX_QW1_TSO_LEN_M\t\\\n-\tMAKEMASK(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S)\n+\tIDPF_M(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S)\n #define IDPF_TXD_CTX_QW1_CMD_S\t\t4\n #define IDPF_TXD_CTX_QW1_CMD_M\t\t\\\n-\tMAKEMASK(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S)\n+\tIDPF_M(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S)\n #define IDPF_TXD_CTX_QW1_DTYPE_S\t0\n #define IDPF_TXD_CTX_QW1_DTYPE_M\t\\\n-\tMAKEMASK(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S)\n+\tIDPF_M(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S)\n #define IDPF_TXD_QW1_L2TAG1_S\t\t48\n #define IDPF_TXD_QW1_L2TAG1_M\t\t\\\n-\tMAKEMASK(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S)\n+\tIDPF_M(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S)\n #define IDPF_TXD_QW1_TX_BUF_SZ_S\t34\n #define IDPF_TXD_QW1_TX_BUF_SZ_M\t\\\n-\tMAKEMASK(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S)\n+\tIDPF_M(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S)\n #define IDPF_TXD_QW1_OFFSET_S\t\t16\n #define IDPF_TXD_QW1_OFFSET_M\t\t\\\n-\tMAKEMASK(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S)\n+\tIDPF_M(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S)\n #define IDPF_TXD_QW1_CMD_S\t\t4\n-#define IDPF_TXD_QW1_CMD_M\t\tMAKEMASK(0xFFFUL, IDPF_TXD_QW1_CMD_S)\n+#define IDPF_TXD_QW1_CMD_M\t\tIDPF_M(0xFFFUL, IDPF_TXD_QW1_CMD_S)\n #define IDPF_TXD_QW1_DTYPE_S\t\t0\n-#define IDPF_TXD_QW1_DTYPE_M\t\tMAKEMASK(0xFUL, IDPF_TXD_QW1_DTYPE_S)\n+#define IDPF_TXD_QW1_DTYPE_M\t\tIDPF_M(0xFUL, IDPF_TXD_QW1_DTYPE_S)\n \n /* TX Completion Descriptor Completion Types */\n #define IDPF_TXD_COMPLT_ITR_FLUSH\t0\n@@ -173,10 +173,10 @@ enum idpf_tx_desc_len_fields {\n \tIDPF_TX_DESC_LEN_L4_LEN_S\t= 14 /* 4 BITS */\n };\n \n-#define IDPF_TXD_QW1_MACLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S)\n-#define IDPF_TXD_QW1_IPLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S)\n-#define IDPF_TXD_QW1_L4LEN_M MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)\n-#define IDPF_TXD_QW1_FCLEN_M MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)\n+#define IDPF_TXD_QW1_MACLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S)\n+#define IDPF_TXD_QW1_IPLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S)\n+#define IDPF_TXD_QW1_L4LEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)\n+#define IDPF_TXD_QW1_FCLEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S)\n \n enum idpf_tx_base_desc_cmd_bits {\n \tIDPF_TX_DESC_CMD_EOP\t\t\t= 0x0001,\n@@ -244,9 +244,9 @@ struct idpf_flex_tx_desc {\n \t\t__le16 cmd_dtype;\n #define IDPF_FLEX_TXD_QW1_DTYPE_S\t\t0\n #define IDPF_FLEX_TXD_QW1_DTYPE_M\t\t\\\n-\t\tMAKEMASK(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S)\n+\t\tIDPF_M(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S)\n #define IDPF_FLEX_TXD_QW1_CMD_S\t\t5\n-#define IDPF_FLEX_TXD_QW1_CMD_M\t\tMAKEMASK(0x7FFUL, IDPF_TXD_QW1_CMD_S)\n+#define IDPF_FLEX_TXD_QW1_CMD_M\t\tIDPF_M(0x7FFUL, IDPF_TXD_QW1_CMD_S)\n \t\tunion {\n \t\t\t/* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */\n \t\t\tu8 raw[4];\n@@ -388,9 +388,9 @@ struct idpf_flex_tx_hs_ctx_desc {\n #define IDPF_TXD_FLEX_CTX_MSS_RT_0\t0\n #define IDPF_TXD_FLEX_CTX_MSS_RT_M\t0x3FFF\n #define IDPF_TXD_FLEX_CTX_FTYPE_S\t14\n-#define IDPF_TXD_FLEX_CTX_FTYPE_VF\tMAKEMASK(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S)\n-#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV\tMAKEMASK(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S)\n-#define IDPF_TXD_FLEX_CTX_FTYPE_PF\tMAKEMASK(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S)\n+#define IDPF_TXD_FLEX_CTX_FTYPE_VF\tIDPF_M(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S)\n+#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV\tIDPF_M(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S)\n+#define IDPF_TXD_FLEX_CTX_FTYPE_PF\tIDPF_M(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S)\n \t\t\tu8 hdr_len;\n \t\t\tu8 ptag;\n \t\t} tso;\n@@ -407,10 +407,10 @@ struct idpf_flex_tx_hs_ctx_desc {\n #define IDPF_TXD_FLEX_CTX_QW1_PASID_M\t\t0xFFFFF\n #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S\t36\n #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID\t\\\n-\t\tMAKEMASK(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S)\n+\t\tIDPF_M(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S)\n #define IDPF_TXD_FLEX_CTX_QW1_TPH_S\t\t37\n #define IDPF_TXD_FLEX_CTX_QW1_TPH \\\n-\t\tMAKEMASK(0x1, IDPF_TXD_FLEX_CTX_TPH_S)\n+\t\tIDPF_M(0x1, IDPF_TXD_FLEX_CTX_TPH_S)\n #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S\t\t38\n #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M\t\t0xF\n /* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */\n@@ -418,7 +418,7 @@ struct idpf_flex_tx_hs_ctx_desc {\n #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M\t\t0x1FFFFF\n #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S\t63\n #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID\t\\\n-\t\tMAKEMASK(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S)\n+\t\tIDPF_M(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S)\n /* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */\n #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S\t\t48\n #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M\t\t0xFF\ndiff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h\nindex 13c5c5a7da..c8739fae7a 100644\n--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h\n@@ -9,7 +9,7 @@\n /* Reset */\n #define VFGEN_RSTAT\t\t\t0x00008800\n #define VFGEN_RSTAT_VFR_STATE_S\t\t0\n-#define VFGEN_RSTAT_VFR_STATE_M\t\tMAKEMASK(0x3, VFGEN_RSTAT_VFR_STATE_S)\n+#define VFGEN_RSTAT_VFR_STATE_M\t\tIDPF_M(0x3, VFGEN_RSTAT_VFR_STATE_S)\n \n /* Control(VF Mailbox) Queue */\n #define VF_BASE\t\t\t\t0x00006000\n@@ -18,7 +18,7 @@\n #define VF_ATQBAH\t\t\t(VF_BASE + 0x1800)\n #define VF_ATQLEN\t\t\t(VF_BASE + 0x0800)\n #define VF_ATQLEN_ATQLEN_S\t\t0\n-#define VF_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, VF_ATQLEN_ATQLEN_S)\n+#define VF_ATQLEN_ATQLEN_M\t\tIDPF_M(0x3FF, VF_ATQLEN_ATQLEN_S)\n #define VF_ATQLEN_ATQVFE_S\t\t28\n #define VF_ATQLEN_ATQVFE_M\t\tBIT(VF_ATQLEN_ATQVFE_S)\n #define VF_ATQLEN_ATQOVFL_S\t\t29\n@@ -29,14 +29,14 @@\n #define VF_ATQLEN_ATQENABLE_M\t\tBIT(VF_ATQLEN_ATQENABLE_S)\n #define VF_ATQH\t\t\t\t(VF_BASE + 0x0400)\n #define VF_ATQH_ATQH_S\t\t\t0\n-#define VF_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, VF_ATQH_ATQH_S)\n+#define VF_ATQH_ATQH_M\t\t\tIDPF_M(0x3FF, VF_ATQH_ATQH_S)\n #define VF_ATQT\t\t\t\t(VF_BASE + 0x2400)\n \n #define VF_ARQBAL\t\t\t(VF_BASE + 0x0C00)\n #define VF_ARQBAH\t\t\t(VF_BASE)\n #define VF_ARQLEN\t\t\t(VF_BASE + 0x2000)\n #define VF_ARQLEN_ARQLEN_S\t\t0\n-#define VF_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, VF_ARQLEN_ARQLEN_S)\n+#define VF_ARQLEN_ARQLEN_M\t\tIDPF_M(0x3FF, VF_ARQLEN_ARQLEN_S)\n #define VF_ARQLEN_ARQVFE_S\t\t28\n #define VF_ARQLEN_ARQVFE_M\t\tBIT(VF_ARQLEN_ARQVFE_S)\n #define VF_ARQLEN_ARQOVFL_S\t\t29\n@@ -47,7 +47,7 @@\n #define VF_ARQLEN_ARQENABLE_M\t\tBIT(VF_ARQLEN_ARQENABLE_S)\n #define VF_ARQH\t\t\t\t(VF_BASE + 0x1400)\n #define VF_ARQH_ARQH_S\t\t\t0\n-#define VF_ARQH_ARQH_M\t\t\tMAKEMASK(0x1FFF, VF_ARQH_ARQH_S)\n+#define VF_ARQH_ARQH_M\t\t\tIDPF_M(0x1FFF, VF_ARQH_ARQH_S)\n #define VF_ARQT\t\t\t\t(VF_BASE + 0x1000)\n \n /* Transmit queues */\n@@ -69,7 +69,7 @@\n #define VF_INT_DYN_CTL0_INTENA_S\t0\n #define VF_INT_DYN_CTL0_INTENA_M\tBIT(VF_INT_DYN_CTL0_INTENA_S)\n #define VF_INT_DYN_CTL0_ITR_INDX_S\t3\n-#define VF_INT_DYN_CTL0_ITR_INDX_M\tMAKEMASK(0x3, VF_INT_DYN_CTL0_ITR_INDX_S)\n+#define VF_INT_DYN_CTL0_ITR_INDX_M\tIDPF_M(0x3, VF_INT_DYN_CTL0_ITR_INDX_S)\n #define VF_INT_DYN_CTLN(_INT)\t\t(0x00003800 + ((_INT) * 4))\n #define VF_INT_DYN_CTLN_EXT(_INT)\t(0x00070000 + ((_INT) * 4))\n #define VF_INT_DYN_CTLN_INTENA_S\t0\n@@ -79,7 +79,7 @@\n #define VF_INT_DYN_CTLN_SWINT_TRIG_S\t2\n #define VF_INT_DYN_CTLN_SWINT_TRIG_M\tBIT(VF_INT_DYN_CTLN_SWINT_TRIG_S)\n #define VF_INT_DYN_CTLN_ITR_INDX_S\t3\n-#define VF_INT_DYN_CTLN_ITR_INDX_M\tMAKEMASK(0x3, VF_INT_DYN_CTLN_ITR_INDX_S)\n+#define VF_INT_DYN_CTLN_ITR_INDX_M\tIDPF_M(0x3, VF_INT_DYN_CTLN_ITR_INDX_S)\n #define VF_INT_DYN_CTLN_INTERVAL_S\t5\n #define VF_INT_DYN_CTLN_INTERVAL_M\tBIT(VF_INT_DYN_CTLN_INTERVAL_S)\n #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S\t24\n@@ -104,7 +104,7 @@\n #define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))\n #define VF_INT_ITRN_MAX_INDEX\t\t2\n #define VF_INT_ITRN_INTERVAL_S\t\t0\n-#define VF_INT_ITRN_INTERVAL_M\t\tMAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S)\n+#define VF_INT_ITRN_INTERVAL_M\t\tIDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S)\n #define VF_INT_PBA_CLEAR\t\t0x00008900\n \n #define VF_INT_ICR0_ENA1\t\t0x00005000\ndiff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h\nindex 99ae9cf60a..abcf68f1a2 100644\n--- a/drivers/common/idpf/base/idpf_osdep.h\n+++ b/drivers/common/idpf/base/idpf_osdep.h\n@@ -45,6 +45,8 @@ typedef struct idpf_lock idpf_lock;\n #define low_16_bits(x)\t\t((x) & 0xFFFF)\n #define high_16_bits(x)\t\t(((x) & 0xFFFF0000) >> 16)\n \n+#define IDPF_M(m, s)\t\t((m) << (s))\n+\n #ifndef ETH_ADDR_LEN\n #define ETH_ADDR_LEN\t\t6\n #endif\ndiff --git a/drivers/common/idpf/base/idpf_type.h b/drivers/common/idpf/base/idpf_type.h\nindex 3b46536287..2a97d32a8b 100644\n--- a/drivers/common/idpf/base/idpf_type.h\n+++ b/drivers/common/idpf/base/idpf_type.h\n@@ -14,8 +14,6 @@\n #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)\n #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t)\n \n-#define MAKEMASK(m, s)\t((m) << (s))\n-\n struct idpf_eth_stats {\n \tu64 rx_bytes;\t\t\t/* gorc */\n \tu64 rx_unicast;\t\t\t/* uprc */\ndiff --git a/drivers/common/idpf/base/virtchnl2_lan_desc.h b/drivers/common/idpf/base/virtchnl2_lan_desc.h\nindex b8cb22e474..0992cefc6c 100644\n--- a/drivers/common/idpf/base/virtchnl2_lan_desc.h\n+++ b/drivers/common/idpf/base/virtchnl2_lan_desc.h\n@@ -80,19 +80,19 @@\n /* For splitq virtchnl2_rx_flex_desc_adv desc members */\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S\t\t0\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M\t\t\\\n-\tMAKEMASK(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S)\n+\tIDPF_M(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S\t\t0\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M\t\t\\\n-\tMAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S)\n+\tIDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S\t\t10\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M\t\t\\\n-\tMAKEMASK(0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S)\n+\tIDPF_M(0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S\t\t12\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M\t\t\t\\\n-\tMAKEMASK(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S)\n+\tIDPF_M(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S\t\t0\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M\t\\\n-\tMAKEMASK(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S)\n+\tIDPF_M(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S\t\t14\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M\t\t\t\\\n \tBIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S)\n@@ -101,7 +101,7 @@\n \tBIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S\t\t0\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M\t\t\\\n-\tMAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S)\n+\tIDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S\t\t10\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M\t\t\t\\\n \tBIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S)\n@@ -110,7 +110,7 @@\n \tBIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_S\t\t12\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M\t\t\t\\\n-\tMAKEMASK(0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M)\n+\tIDPF_M(0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M)\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S\t\t15\n #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_M\t\t\\\n \tBIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S)\n@@ -159,12 +159,12 @@\n /* for virtchnl2_rx_flex_desc.ptype_flex_flags0 member */\n #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_S\t\t\t0\n #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M\t\t\t\\\n-\tMAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */\n+\tIDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */\n \n /* for virtchnl2_rx_flex_desc.pkt_length member */\n #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S\t\t\t0\n #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M\t\t\t\\\n-\tMAKEMASK(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */\n+\tIDPF_M(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */\n \n /* VIRTCHNL2_RX_FLEX_DESC_STATUS_ERROR_0_BITS\n * for singleq (flex) virtchnl2_rx_flex_desc\n@@ -212,19 +212,19 @@\n \tBIT_ULL(VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S)\n #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S\t52\n #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_M\t\\\n-\tMAKEMASK(0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S)\n+\tIDPF_M(0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S)\n #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S\t38\n #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M\t\\\n-\tMAKEMASK(0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S)\n+\tIDPF_M(0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S)\n #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S\t30\n #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M\t\\\n-\tMAKEMASK(0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S)\n+\tIDPF_M(0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S)\n #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S\t19\n #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M\t\\\n-\tMAKEMASK(0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S)\n+\tIDPF_M(0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S)\n #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S\t0\n #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M\t\\\n-\tMAKEMASK(0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S)\n+\tIDPF_M(0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S)\n \n /* VIRTCHNL2_RX_BASE_DESC_STATUS_BITS\n * for singleq (base) virtchnl2_rx_base_desc\n", "prefixes": [ "v3", "12/15" ] }