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{
    "id": 126579,
    "url": "http://patchwork.dpdk.org/api/patches/126579/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230427062001.478032-13-qiming.yang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230427062001.478032-13-qiming.yang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-13-qiming.yang@intel.com",
    "date": "2023-04-27T06:19:43",
    "name": "[12/30] net/ice/base: add E830 device ids",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "09e47ebc5f42ca313ec35d6ae78c85c09cb87819",
    "submitter": {
        "id": 522,
        "url": "http://patchwork.dpdk.org/api/people/522/?format=api",
        "name": "Qiming Yang",
        "email": "qiming.yang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patchwork.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230427062001.478032-13-qiming.yang@intel.com/mbox/",
    "series": [
        {
            "id": 27885,
            "url": "http://patchwork.dpdk.org/api/series/27885/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27885",
            "date": "2023-04-27T06:19:31",
            "name": "net/ice/base: share code update",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/27885/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/126579/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/126579/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 732B342A08;\n\tThu, 27 Apr 2023 08:39:20 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 267FE42DA5;\n\tThu, 27 Apr 2023 08:38:10 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id C25B742D98\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:38:07 +0200 (CEST)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:38:07 -0700",
            "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:04 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577488; x=1714113488;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Dml7IPuwImFCYfQl9Ol3ZFdDKXyJSwna4GZz66SkY6U=;\n b=Bl6nxe4FZmFFsxUognEEkgRAYY7t8E7o/D2ul+fk5BXJhTuXu+/pTeZX\n v3Uu86euZLK/JXZyntM45hJSchP/Q7gQvnuVm+9OAtM4AJVXpe3MxLL6p\n MD36lRoHYAzAH3qwndSTKkhjMkAPDTmEsVK7RPnM91mSwwzm0qaSN43as\n x+TcCB19K6DozcVQjxLDq4VX67hZblKADJjvY9PV+VpXZ3dXvo3RT6W3S\n weIdwwdRmfNXPnxgjYLPfioyZro4wWmHF5D3r7uP4hXH9rG05WZuJiQXQ\n 5p/9Fy/jAUBTLqznmq95uUeSEPWPSlr4iqwszEdWJsjC20t87jSuuRT7E A==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10692\"; a=\"375324315\"",
            "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324315\"",
            "E=McAfee;i=\"6600,9927,10692\"; a=\"805845740\"",
            "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845740\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qiming Yang <qiming.yang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Paul Greenwalt <paul.greeenwalt@intel.com>",
        "Subject": "[PATCH 12/30] net/ice/base: add E830 device ids",
        "Date": "Thu, 27 Apr 2023 06:19:43 +0000",
        "Message-Id": "<20230427062001.478032-13-qiming.yang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>",
        "References": "<20230427062001.478032-1-qiming.yang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Added new E830 device id and related registers.\n\nSigned-off-by: Paul Greenwalt <paul.greeenwalt@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_common.c     |    8 +-\n drivers/net/ice/base/ice_ddp.c        |    6 +\n drivers/net/ice/base/ice_ddp.h        |    1 +\n drivers/net/ice/base/ice_devids.h     |    8 +\n drivers/net/ice/base/ice_hw_autogen.h | 1640 +++++++++++++++++++++++++\n drivers/net/ice/base/ice_lan_tx_rx.h  |    2 +-\n drivers/net/ice/base/ice_nvm.c        |   15 +-\n drivers/net/ice/base/ice_type.h       |    1 +\n 8 files changed, 1673 insertions(+), 8 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 6967ff1a8f..58da198d62 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -9,7 +9,7 @@\n #include \"ice_flow.h\"\n #include \"ice_switch.h\"\n \n-#define ICE_PF_RESET_WAIT_COUNT\t300\n+#define ICE_PF_RESET_WAIT_COUNT\t500\n \n static const char * const ice_link_mode_str_low[] = {\n \tice_arr_elem_idx(0, \"100BASE_TX\"),\n@@ -249,6 +249,12 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw)\n \tcase ICE_DEV_ID_E825X:\n \t\thw->mac_type = ICE_MAC_GENERIC;\n \t\tbreak;\n+\tcase ICE_DEV_ID_E830_BACKPLANE:\n+\tcase ICE_DEV_ID_E830_QSFP56:\n+\tcase ICE_DEV_ID_E830_SFP:\n+\tcase ICE_DEV_ID_E830_SFP_DD:\n+\t\thw->mac_type = ICE_MAC_E830;\n+\t\tbreak;\n \tdefault:\n \t\thw->mac_type = ICE_MAC_UNKNOWN;\n \t\tbreak;\ndiff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c\nindex ae0a03c8ba..e3c1f413dd 100644\n--- a/drivers/net/ice/base/ice_ddp.c\n+++ b/drivers/net/ice/base/ice_ddp.c\n@@ -439,6 +439,9 @@ static u32 ice_get_pkg_segment_id(enum ice_mac_type mac_type)\n \tu32 seg_id;\n \n \tswitch (mac_type) {\n+\tcase ICE_MAC_E830:\n+\t\tseg_id = SEGMENT_TYPE_ICE_E830;\n+\t\tbreak;\n \tcase ICE_MAC_GENERIC:\n \tcase ICE_MAC_GENERIC_3K:\n \tdefault:\n@@ -458,6 +461,9 @@ static u32 ice_get_pkg_sign_type(enum ice_mac_type mac_type)\n \tu32 sign_type;\n \n \tswitch (mac_type) {\n+\tcase ICE_MAC_E830:\n+\t\tsign_type = SEGMENT_SIGN_TYPE_RSA3K_SBB;\n+\t\tbreak;\n \tcase ICE_MAC_GENERIC_3K:\n \t\tsign_type = SEGMENT_SIGN_TYPE_RSA3K;\n \t\tbreak;\ndiff --git a/drivers/net/ice/base/ice_ddp.h b/drivers/net/ice/base/ice_ddp.h\nindex 4896e85b91..57b39c72ca 100644\n--- a/drivers/net/ice/base/ice_ddp.h\n+++ b/drivers/net/ice/base/ice_ddp.h\n@@ -106,6 +106,7 @@ struct ice_generic_seg_hdr {\n #define SEGMENT_TYPE_METADATA\t0x00000001\n #define SEGMENT_TYPE_ICE_E810\t0x00000010\n #define SEGMENT_TYPE_SIGNING\t0x00001001\n+#define SEGMENT_TYPE_ICE_E830\t0x00000017\n #define SEGMENT_TYPE_ICE_RUN_TIME_CFG 0x00000020\n \t__le32 seg_type;\n \tstruct ice_pkg_ver seg_format_ver;\ndiff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h\nindex f80789ebc5..9ea915b967 100644\n--- a/drivers/net/ice/base/ice_devids.h\n+++ b/drivers/net/ice/base/ice_devids.h\n@@ -15,6 +15,14 @@\n #define ICE_DEV_ID_E823L_1GBE\t\t0x124F\n /* Intel(R) Ethernet Connection E823-L for QSFP */\n #define ICE_DEV_ID_E823L_QSFP\t\t0x151D\n+/* Intel(R) Ethernet Controller E830-C for backplane */\n+#define ICE_DEV_ID_E830_BACKPLANE\t0x12D1\n+/* Intel(R) Ethernet Controller E830-C for QSFP */\n+#define ICE_DEV_ID_E830_QSFP56\t\t0x12D2\n+/* Intel(R) Ethernet Controller E830-C for SFP */\n+#define ICE_DEV_ID_E830_SFP\t\t0x12D3\n+/* Intel(R) Ethernet Controller E830-C for SFP-DD */\n+#define ICE_DEV_ID_E830_SFP_DD\t\t0x12D4\n /* Intel(R) Ethernet Controller E810-C for backplane */\n #define ICE_DEV_ID_E810C_BACKPLANE\t0x1591\n /* Intel(R) Ethernet Controller E810-C for QSFP */\ndiff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h\nindex 4610cec6a7..522840a847 100644\n--- a/drivers/net/ice/base/ice_hw_autogen.h\n+++ b/drivers/net/ice/base/ice_hw_autogen.h\n@@ -9458,5 +9458,1645 @@\n #define VFPE_WQEALLOC1_PEQPID_M\t\t\tMAKEMASK(0x3FFFF, 0)\n #define VFPE_WQEALLOC1_WQE_DESC_INDEX_S\t\t20\n #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M\t\tMAKEMASK(0xFFF, 20)\n+#define E830_GL_QRX_CONTEXT_CTL\t\t\t0x00296640 /* Reset Source: CORER */\n+#define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_S\t0\n+#define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_M\tMAKEMASK(0xFFF, 0)\n+#define E830_GL_QRX_CONTEXT_CTL_CMD_S\t\t16\n+#define E830_GL_QRX_CONTEXT_CTL_CMD_M\t\tMAKEMASK(0x7, 16)\n+#define E830_GL_QRX_CONTEXT_CTL_CMD_EXEC_S\t19\n+#define E830_GL_QRX_CONTEXT_CTL_CMD_EXEC_M\tBIT(19)\n+#define E830_GL_QRX_CONTEXT_DATA(_i)\t\t(0x00296620 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_QRX_CONTEXT_DATA_MAX_INDEX\t7\n+#define E830_GL_QRX_CONTEXT_DATA_DATA_S\t\t0\n+#define E830_GL_QRX_CONTEXT_DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_QRX_CONTEXT_STAT\t\t0x00296644 /* Reset Source: CORER */\n+#define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_S\t0\n+#define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_M\tBIT(0)\n+#define E830_GL_RCB_INTERNAL(_i)\t\t(0x00122600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define E830_GL_RCB_INTERNAL_MAX_INDEX\t\t63\n+#define E830_GL_RCB_INTERNAL_INTERNAL_S\t\t0\n+#define E830_GL_RCB_INTERNAL_INTERNAL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_RLAN_INTERNAL(_i)\t\t(0x00296700 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define E830_GL_RLAN_INTERNAL_MAX_INDEX\t\t63\n+#define E830_GL_RLAN_INTERNAL_INTERNAL_S\t0\n+#define E830_GL_RLAN_INTERNAL_INTERNAL_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS 0x002D30F8 /* Reset Source: CORER */\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_S 0\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_M MAKEMASK(0xFF, 0)\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_S 8\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 8)\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS\t0x002D30FC /* Reset Source: CORER */\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_S 0\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_M MAKEMASK(0x3F, 0)\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_S 6\n+#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 6)\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS\t0x002D30F0 /* Reset Source: CORER */\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_DBLQ_S 0\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_DBLQ_M MAKEMASK(0xFF, 0)\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_FDBL_S 8\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_FDBL_M MAKEMASK(0xFF, 8)\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_TXT_S 16\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 16)\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS\t0x002D30F4 /* Reset Source: CORER */\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_DBLQ_S 0\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_DBLQ_M MAKEMASK(0x3F, 0)\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_FDBL_S 6\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_FDBL_M MAKEMASK(0x3F, 6)\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_TXT_S 12\n+#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 12)\n+#define E830_GLQTX_TXTIME_DBELL_LSB(_DBQM)\t(0x002E0000 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */\n+#define E830_GLQTX_TXTIME_DBELL_LSB_MAX_INDEX\t16383\n+#define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_S 0\n+#define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLQTX_TXTIME_DBELL_MSB(_DBQM)\t(0x002E0004 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */\n+#define E830_GLQTX_TXTIME_DBELL_MSB_MAX_INDEX\t16383\n+#define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_S 0\n+#define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS\t0x002D320C /* Reset Source: CORER */\n+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_S 0\n+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_M MAKEMASK(0xFF, 0)\n+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_S 8\n+#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_M MAKEMASK(0xFF, 8)\n+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS\t0x002D3210 /* Reset Source: CORER */\n+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_S 0\n+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_M MAKEMASK(0x3F, 0)\n+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_S 6\n+#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_M MAKEMASK(0x3F, 6)\n+#define E830_GLTXTIME_FETCH_PROFILE(_i, _j)\t(0x002D3500 + ((_i) * 4 + (_j) * 64)) /* _i=0...15, _j=0...15 */ /* Reset Source: CORER */\n+#define E830_GLTXTIME_FETCH_PROFILE_MAX_INDEX\t15\n+#define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_S 0\n+#define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_M MAKEMASK(0x1FF, 0)\n+#define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_S 9\n+#define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_M MAKEMASK(0x7F, 9)\n+#define E830_GLTXTIME_OUTST_REQ_CNTL\t\t0x002D3214 /* Reset Source: CORER */\n+#define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_S 0\n+#define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_M MAKEMASK(0x3FF, 0)\n+#define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_S\t10\n+#define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_M\tMAKEMASK(0x3FF, 10)\n+#define E830_GLTXTIME_QTX_CNTX_CTL\t\t0x002D3204 /* Reset Source: CORER */\n+#define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_S\t0\n+#define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_M\tMAKEMASK(0x7FF, 0)\n+#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_S\t16\n+#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_M\tMAKEMASK(0x7, 16)\n+#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_EXEC_S\t19\n+#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_EXEC_M\tBIT(19)\n+#define E830_GLTXTIME_QTX_CNTX_DATA(_i)\t\t(0x002D3104 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */\n+#define E830_GLTXTIME_QTX_CNTX_DATA_MAX_INDEX\t6\n+#define E830_GLTXTIME_QTX_CNTX_DATA_DATA_S\t0\n+#define E830_GLTXTIME_QTX_CNTX_DATA_DATA_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTXTIME_QTX_CNTX_STAT\t\t0x002D3208 /* Reset Source: CORER */\n+#define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_S 0\n+#define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0)\n+#define E830_GLTXTIME_TS_CFG\t\t\t0x002D3100 /* Reset Source: CORER */\n+#define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_S\t0\n+#define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_M\tBIT(0)\n+#define E830_GLTXTIME_TS_CFG_STORAGE_MODE_S\t2\n+#define E830_GLTXTIME_TS_CFG_STORAGE_MODE_M\tMAKEMASK(0x7, 2)\n+#define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_S 5\n+#define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_M MAKEMASK(0x1FFF, 5)\n+#define E830_MBX_PF_DEC_ERR\t\t\t0x00234100 /* Reset Source: CORER */\n+#define E830_MBX_PF_DEC_ERR_DEC_ERR_S\t\t0\n+#define E830_MBX_PF_DEC_ERR_DEC_ERR_M\t\tBIT(0)\n+#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH\t0x00234000 /* Reset Source: CORER */\n+#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_S 0\n+#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_M MAKEMASK(0x3FF, 0)\n+#define E830_MBX_VF_DEC_TRIG(_VF)\t\t(0x00233800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_MBX_VF_DEC_TRIG_MAX_INDEX\t\t255\n+#define E830_MBX_VF_DEC_TRIG_DEC_S\t\t0\n+#define E830_MBX_VF_DEC_TRIG_DEC_M\t\tMAKEMASK(0x3FF, 0)\n+#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT(_VF) (0x00233000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MAX_INDEX 255\n+#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_S 0\n+#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_M MAKEMASK(0x3FF, 0)\n+#define E830_GLRCB_AG_ARBITER_CONFIG\t\t0x00122500 /* Reset Source: CORER */\n+#define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_S 0\n+#define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0xFFFFF, 0)\n+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG\t0x00122518 /* Reset Source: CORER */\n+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_S 0\n+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0x7F, 0)\n+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_STRICT_WRR_S 7\n+#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_STRICT_WRR_M BIT(7)\n+#define E830_GLRCB_AG_DCB_NODE_CONFIG(_i)\t(0x00122510 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define E830_GLRCB_AG_DCB_NODE_CONFIG_MAX_INDEX\t1\n+#define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_S\t0\n+#define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_M\tMAKEMASK(0xF, 0)\n+#define E830_GLRCB_AG_DCB_NODE_STATE(_i)\t(0x00122508 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define E830_GLRCB_AG_DCB_NODE_STATE_MAX_INDEX\t1\n+#define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_S\t0\n+#define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_M\tMAKEMASK(0xFF, 0)\n+#define E830_GLRCB_AG_NODE_CONFIG(_i)\t\t(0x001224E0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLRCB_AG_NODE_CONFIG_MAX_INDEX\t7\n+#define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_S\t0\n+#define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_M\tMAKEMASK(0x7F, 0)\n+#define E830_GLRCB_AG_NODE_STATE(_i)\t\t(0x001224C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLRCB_AG_NODE_STATE_MAX_INDEX\t7\n+#define E830_GLRCB_AG_NODE_STATE_CREDITS_S\t0\n+#define E830_GLRCB_AG_NODE_STATE_CREDITS_M\tMAKEMASK(0xFFFFF, 0)\n+#define E830_PRT_AG_PORT_FC_MAP\t\t\t0x00122520 /* Reset Source: CORER */\n+#define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_S\t0\n+#define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_M\tMAKEMASK(0xFF, 0)\n+#define E830_GL_FW_LOGS_CTL\t\t\t0x000827F8 /* Reset Source: POR */\n+#define E830_GL_FW_LOGS_CTL_PAGE_SELECT_S\t0\n+#define E830_GL_FW_LOGS_CTL_PAGE_SELECT_M\tMAKEMASK(0x3FF, 0)\n+#define E830_GL_FW_LOGS_STS\t\t\t0x000827FC /* Reset Source: POR */\n+#define E830_GL_FW_LOGS_STS_MAX_PAGE_S\t\t0\n+#define E830_GL_FW_LOGS_STS_MAX_PAGE_M\t\tMAKEMASK(0x3FF, 0)\n+#define E830_GL_FW_LOGS_STS_FW_LOGS_ENA_S\t31\n+#define E830_GL_FW_LOGS_STS_FW_LOGS_ENA_M\tBIT(31)\n+#define E830_GLGEN_RTRIG_EMPR_WO_GLOBR_S\t3\n+#define E830_GLGEN_RTRIG_EMPR_WO_GLOBR_M\tBIT(3)\n+#define E830_GLPE_TSCD_NUM_PQS\t\t\t0x0051E2FC /* Reset Source: CORER */\n+#define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_S\t0\n+#define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTPB_100G_RPB_FC_THRESH2\t\t0x0009972C /* Reset Source: CORER */\n+#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_S 0\n+#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_S 16\n+#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_GLTPB_100G_RPB_FC_THRESH3\t\t0x00099730 /* Reset Source: CORER */\n+#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_S 0\n+#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_S 16\n+#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PORT_TIMER_SEL(_i)\t\t\t(0x00088BE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_PORT_TIMER_SEL_MAX_INDEX\t\t7\n+#define E830_PORT_TIMER_SEL_TIMER_SEL_S\t\t0\n+#define E830_PORT_TIMER_SEL_TIMER_SEL_M\t\tBIT(0)\n+#define E830_GLINT_FW_DCF_CTL(_i)\t\t(0x0016CFD4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLINT_FW_DCF_CTL_MAX_INDEX\t\t7\n+#define E830_GLINT_FW_DCF_CTL_MSIX_INDX_S\t0\n+#define E830_GLINT_FW_DCF_CTL_MSIX_INDX_M\tMAKEMASK(0x7FF, 0)\n+#define E830_GLINT_FW_DCF_CTL_ITR_INDX_S\t11\n+#define E830_GLINT_FW_DCF_CTL_ITR_INDX_M\tMAKEMASK(0x3, 11)\n+#define E830_GLINT_FW_DCF_CTL_CAUSE_ENA_S\t30\n+#define E830_GLINT_FW_DCF_CTL_CAUSE_ENA_M\tBIT(30)\n+#define E830_GLINT_FW_DCF_CTL_INTEVENT_S\t31\n+#define E830_GLINT_FW_DCF_CTL_INTEVENT_M\tBIT(31)\n+#define E830_GL_MDET_RX_FIFO\t\t\t0x00296840 /* Reset Source: CORER */\n+#define E830_GL_MDET_RX_FIFO_FUNC_NUM_S\t\t0\n+#define E830_GL_MDET_RX_FIFO_FUNC_NUM_M\t\tMAKEMASK(0x3FF, 0)\n+#define E830_GL_MDET_RX_FIFO_PF_NUM_S\t\t10\n+#define E830_GL_MDET_RX_FIFO_PF_NUM_M\t\tMAKEMASK(0x7, 10)\n+#define E830_GL_MDET_RX_FIFO_FUNC_TYPE_S\t13\n+#define E830_GL_MDET_RX_FIFO_FUNC_TYPE_M\tMAKEMASK(0x3, 13)\n+#define E830_GL_MDET_RX_FIFO_MAL_TYPE_S\t\t15\n+#define E830_GL_MDET_RX_FIFO_MAL_TYPE_M\t\tMAKEMASK(0x1F, 15)\n+#define E830_GL_MDET_RX_FIFO_FIFO_FULL_S\t20\n+#define E830_GL_MDET_RX_FIFO_FIFO_FULL_M\tBIT(20)\n+#define E830_GL_MDET_RX_FIFO_VALID_S\t\t21\n+#define E830_GL_MDET_RX_FIFO_VALID_M\t\tBIT(21)\n+#define E830_GL_MDET_RX_PF_CNT(_i)\t\t(0x00296800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_RX_PF_CNT_MAX_INDEX\t7\n+#define E830_GL_MDET_RX_PF_CNT_CNT_S\t\t0\n+#define E830_GL_MDET_RX_PF_CNT_CNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MDET_RX_VF(_i)\t\t\t(0x00296820 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_RX_VF_MAX_INDEX\t\t7\n+#define E830_GL_MDET_RX_VF_VF_MAL_EVENT_S\t0\n+#define E830_GL_MDET_RX_VF_VF_MAL_EVENT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MDET_TX_PQM_FIFO\t\t0x002D4B00 /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_S\t0\n+#define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_M\tMAKEMASK(0x3FF, 0)\n+#define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_S\t10\n+#define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_M\tMAKEMASK(0x7, 10)\n+#define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_S\t13\n+#define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_M\tMAKEMASK(0x3, 13)\n+#define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_S\t15\n+#define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_M\tMAKEMASK(0x1F, 15)\n+#define E830_GL_MDET_TX_PQM_FIFO_FIFO_FULL_S\t20\n+#define E830_GL_MDET_TX_PQM_FIFO_FIFO_FULL_M\tBIT(20)\n+#define E830_GL_MDET_TX_PQM_FIFO_VALID_S\t21\n+#define E830_GL_MDET_TX_PQM_FIFO_VALID_M\tBIT(21)\n+#define E830_GL_MDET_TX_PQM_PF_CNT(_i)\t\t(0x002D4AC0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_PQM_PF_CNT_MAX_INDEX\t7\n+#define E830_GL_MDET_TX_PQM_PF_CNT_CNT_S\t0\n+#define E830_GL_MDET_TX_PQM_PF_CNT_CNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MDET_TX_PQM_VF(_i)\t\t(0x002D4AE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_PQM_VF_MAX_INDEX\t7\n+#define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_S\t0\n+#define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MDET_TX_TCLAN_FIFO\t\t0x000FD000 /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_S\t0\n+#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_M\tMAKEMASK(0x3FF, 0)\n+#define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_S\t10\n+#define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_M\tMAKEMASK(0x7, 10)\n+#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_S\t13\n+#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_M\tMAKEMASK(0x3, 13)\n+#define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_S\t15\n+#define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_M\tMAKEMASK(0x1F, 15)\n+#define E830_GL_MDET_TX_TCLAN_FIFO_FIFO_FULL_S\t20\n+#define E830_GL_MDET_TX_TCLAN_FIFO_FIFO_FULL_M\tBIT(20)\n+#define E830_GL_MDET_TX_TCLAN_FIFO_VALID_S\t21\n+#define E830_GL_MDET_TX_TCLAN_FIFO_VALID_M\tBIT(21)\n+#define E830_GL_MDET_TX_TCLAN_PF_CNT(_i)\t(0x000FCFC0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_TCLAN_PF_CNT_MAX_INDEX\t7\n+#define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_S\t0\n+#define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MDET_TX_TCLAN_VF(_i)\t\t(0x000FCFE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_TCLAN_VF_MAX_INDEX\t7\n+#define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_S\t0\n+#define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MDET_TX_TDPU_FIFO\t\t0x00049D80 /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_S\t0\n+#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_M\tMAKEMASK(0x3FF, 0)\n+#define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_S\t10\n+#define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_M\tMAKEMASK(0x7, 10)\n+#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_S\t13\n+#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_M\tMAKEMASK(0x3, 13)\n+#define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_S\t15\n+#define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_M\tMAKEMASK(0x1F, 15)\n+#define E830_GL_MDET_TX_TDPU_FIFO_FIFO_FULL_S\t20\n+#define E830_GL_MDET_TX_TDPU_FIFO_FIFO_FULL_M\tBIT(20)\n+#define E830_GL_MDET_TX_TDPU_FIFO_VALID_S\t21\n+#define E830_GL_MDET_TX_TDPU_FIFO_VALID_M\tBIT(21)\n+#define E830_GL_MDET_TX_TDPU_PF_CNT(_i)\t\t(0x00049D40 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_TDPU_PF_CNT_MAX_INDEX\t7\n+#define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_S\t0\n+#define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MDET_TX_TDPU_VF(_i)\t\t(0x00049D60 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_TX_TDPU_VF_MAX_INDEX\t7\n+#define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_S\t0\n+#define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MNG_ECDSA_PUBKEY(_i)\t\t(0x00083300 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */\n+#define E830_GL_MNG_ECDSA_PUBKEY_MAX_INDEX\t11\n+#define E830_GL_MNG_ECDSA_PUBKEY_GL_MNG_ECDSA_PUBKEY_S 0\n+#define E830_GL_MNG_ECDSA_PUBKEY_GL_MNG_ECDSA_PUBKEY_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_PPRS_RX_SIZE_CTRL_0(_i)\t\t(0x00084900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_INDEX\t1\n+#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_S 16\n+#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)\n+#define E830_GL_PPRS_RX_SIZE_CTRL_1(_i)\t\t(0x00085900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_INDEX\t1\n+#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_S 16\n+#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)\n+#define E830_GL_PPRS_RX_SIZE_CTRL_2(_i)\t\t(0x00086900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_INDEX\t1\n+#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_S 16\n+#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)\n+#define E830_GL_PPRS_RX_SIZE_CTRL_3(_i)\t\t(0x00087900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_INDEX\t1\n+#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_S 16\n+#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP\t0x00200740 /* Reset Source: CORER */\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0)\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_S 8\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8)\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_S 16\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16)\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_S 24\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24)\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP\t0x00200744 /* Reset Source: CORER */\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0)\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_S 8\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8)\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_S 16\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16)\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_S 24\n+#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24)\n+#define E830_GL_RPRS_PROT_ID_MAP(_i)\t\t(0x00200800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_GL_RPRS_PROT_ID_MAP_MAX_INDEX\t255\n+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_S\t0\n+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_M\tMAKEMASK(0xFF, 0)\n+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_S\t8\n+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_M\tMAKEMASK(0xFF, 8)\n+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_S\t16\n+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_M\tMAKEMASK(0xFF, 16)\n+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_S\t24\n+#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_M\tMAKEMASK(0xFF, 24)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL(_i)\t(0x00201000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_MAX_INDEX\t63\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_S 2\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_S 4\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_S 6\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_S 8\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_S 10\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_S 12\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_S 14\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_S 16\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_S 18\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_S 20\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_S 22\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_S 24\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_S 26\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_S 28\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28)\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_S 30\n+#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30)\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL\t0x00200748 /* Reset Source: CORER */\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0)\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_S 1\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_M BIT(1)\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_S 2\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_M BIT(2)\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_S 3\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_M BIT(3)\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_S 4\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_M BIT(4)\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_S 5\n+#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_M BIT(5)\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP\t0x00203A04 /* Reset Source: CORER */\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0)\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_S 8\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8)\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_S 16\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16)\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_S 24\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24)\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP\t0x00203A08 /* Reset Source: CORER */\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0)\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_S 8\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8)\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_S 16\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16)\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_S 24\n+#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24)\n+#define E830_GL_TPRS_PROT_ID_MAP(_i)\t\t(0x00202200 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_GL_TPRS_PROT_ID_MAP_MAX_INDEX\t255\n+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_S\t0\n+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_M\tMAKEMASK(0xFF, 0)\n+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_S\t8\n+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_M\tMAKEMASK(0xFF, 8)\n+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_S\t16\n+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_M\tMAKEMASK(0xFF, 16)\n+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_S\t24\n+#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_M\tMAKEMASK(0xFF, 24)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL(_i)\t(0x00202A00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_MAX_INDEX\t63\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_S 2\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_S 4\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_S 6\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_S 8\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_S 10\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_S 12\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_S 14\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_S 16\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_S 18\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_S 20\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_S 22\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_S 24\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_S 26\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_S 28\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28)\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_S 30\n+#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30)\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL\t0x00203A00 /* Reset Source: CORER */\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0)\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_S 1\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_M BIT(1)\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_S 2\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_M BIT(2)\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_S 3\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_M BIT(3)\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_S 4\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_M BIT(4)\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_S 5\n+#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_M BIT(5)\n+#define E830_PRT_TDPU_TX_SIZE_CTRL\t\t0x00049D20 /* Reset Source: CORER */\n+#define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_S 16\n+#define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)\n+#define E830_PRT_TPB_RX_LB_SIZE_CTRL\t\t0x00099740 /* Reset Source: CORER */\n+#define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_S 16\n+#define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16)\n+#define E830_GLNVM_AL_DONE_HLP_PAGE\t\t0x02D004B0 /* Reset Source: POR */\n+#define E830_GLNVM_AL_DONE_HLP_PAGE_HLP_CORER_S\t0\n+#define E830_GLNVM_AL_DONE_HLP_PAGE_HLP_CORER_M\tBIT(0)\n+#define E830_GLNVM_AL_DONE_HLP_PAGE_HLP_FULLR_S\t1\n+#define E830_GLNVM_AL_DONE_HLP_PAGE_HLP_FULLR_M\tBIT(1)\n+#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE(_DBQM)\t(0x04000008 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */\n+#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_MAX_INDEX 16383\n+#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_S 0\n+#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE(_DBQM)\t(0x0400000C + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */\n+#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_MAX_INDEX 16383\n+#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_S 0\n+#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PF0INT_OICR_CPM_PAGE_PTM_COMP_S\t8\n+#define E830_PF0INT_OICR_CPM_PAGE_PTM_COMP_M\tBIT(8)\n+#define E830_PF0INT_OICR_CPM_PAGE_RSV4_S\t9\n+#define E830_PF0INT_OICR_CPM_PAGE_RSV4_M\tBIT(9)\n+#define E830_PF0INT_OICR_CPM_PAGE_RSV5_S\t10\n+#define E830_PF0INT_OICR_CPM_PAGE_RSV5_M\tBIT(10)\n+#define E830_PF0INT_OICR_HLP_PAGE_PTM_COMP_S\t8\n+#define E830_PF0INT_OICR_HLP_PAGE_PTM_COMP_M\tBIT(8)\n+#define E830_PF0INT_OICR_HLP_PAGE_RSV4_S\t9\n+#define E830_PF0INT_OICR_HLP_PAGE_RSV4_M\tBIT(9)\n+#define E830_PF0INT_OICR_HLP_PAGE_RSV5_S\t10\n+#define E830_PF0INT_OICR_HLP_PAGE_RSV5_M\tBIT(10)\n+#define E830_PF0INT_OICR_PSM_PAGE_PTM_COMP_S\t8\n+#define E830_PF0INT_OICR_PSM_PAGE_PTM_COMP_M\tBIT(8)\n+#define E830_PF0INT_OICR_PSM_PAGE_RSV4_S\t9\n+#define E830_PF0INT_OICR_PSM_PAGE_RSV4_M\tBIT(9)\n+#define E830_PF0INT_OICR_PSM_PAGE_RSV5_S\t10\n+#define E830_PF0INT_OICR_PSM_PAGE_RSV5_M\tBIT(10)\n+#define E830_GL_HIBA(_i)\t\t\t(0x00081000 + ((_i) * 4)) /* _i=0...1023 */ /* Reset Source: EMPR */\n+#define E830_GL_HIBA_MAX_INDEX\t\t\t1023\n+#define E830_GL_HIBA_GL_HIBA_S\t\t\t0\n+#define E830_GL_HIBA_GL_HIBA_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_HICR\t\t\t\t0x00082040 /* Reset Source: EMPR */\n+#define E830_GL_HICR_C_S\t\t\t1\n+#define E830_GL_HICR_C_M\t\t\tBIT(1)\n+#define E830_GL_HICR_SV_S\t\t\t2\n+#define E830_GL_HICR_SV_M\t\t\tBIT(2)\n+#define E830_GL_HICR_EV_S\t\t\t3\n+#define E830_GL_HICR_EV_M\t\t\tBIT(3)\n+#define E830_GL_HICR_EN\t\t\t\t0x00082044 /* Reset Source: EMPR */\n+#define E830_GL_HICR_EN_EN_S\t\t\t0\n+#define E830_GL_HICR_EN_EN_M\t\t\tBIT(0)\n+#define E830_GL_HIDA(_i)\t\t\t(0x00082000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: EMPR */\n+#define E830_GL_HIDA_MAX_INDEX\t\t\t15\n+#define E830_GL_HIDA_GL_HIDB_S\t\t\t0\n+#define E830_GL_HIDA_GL_HIDB_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_S\t18\n+#define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_M\tMAKEMASK(0xF, 18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_S\t18\n+#define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_M\tMAKEMASK(0xF, 18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_S\t18\n+#define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_M\tMAKEMASK(0xF, 18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_S\t18\n+#define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_M\tMAKEMASK(0xF, 18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_S\t18\n+#define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_M\tMAKEMASK(0xF, 18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_S\t18\n+#define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_M\tMAKEMASK(0xF, 18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_6(_i)\t\t(0x0045CE00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_MAX_INDEX\t63\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_S\t0\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_S 8\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_L2TAG_OVRD_EN_S 18\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_L2TAG_OVRD_EN_M BIT(18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_S\t19\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_M\tMAKEMASK(0x7, 19)\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_S 30\n+#define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_M MAKEMASK(0x3, 30)\n+#define E830_GLFLXP_RXDID_FLX_WRD_7(_i)\t\t(0x0045CF00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_MAX_INDEX\t63\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_S\t0\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_S 8\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_L2TAG_OVRD_EN_S 18\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_L2TAG_OVRD_EN_M BIT(18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_S\t19\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_M\tMAKEMASK(0x7, 19)\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_S 30\n+#define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_M MAKEMASK(0x3, 30)\n+#define E830_GLFLXP_RXDID_FLX_WRD_8(_i)\t\t(0x0045D500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_MAX_INDEX\t63\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_S\t0\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_S 8\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_L2TAG_OVRD_EN_S 18\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_L2TAG_OVRD_EN_M BIT(18)\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_S\t19\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_M\tMAKEMASK(0x7, 19)\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_S 30\n+#define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_M MAKEMASK(0x3, 30)\n+#define E830_GL_FW_LOGS(_i)\t\t\t(0x00082800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: POR */\n+#define E830_GL_FW_LOGS_MAX_INDEX\t\t255\n+#define E830_GL_FW_LOGS_GL_FW_LOGS_S\t\t0\n+#define E830_GL_FW_LOGS_GL_FW_LOGS_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_FWSTS_FWABS_S\t\t\t10\n+#define E830_GL_FWSTS_FWABS_M\t\t\tMAKEMASK(0x3, 10)\n+#define E830_GL_FWSTS_FW_FAILOVER_TRIG_S\t12\n+#define E830_GL_FWSTS_FW_FAILOVER_TRIG_M\tBIT(12)\n+#define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_S\t19\n+#define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_M\tMAKEMASK(0x3, 19)\n+#define E830_GLPCI_PLATFORM_INFO\t\t0x0009DDC4 /* Reset Source: POR */\n+#define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_S 0\n+#define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_M MAKEMASK(0xFF, 0)\n+#define E830_GL_MDCK_TDAT_TCLAN_DESC_TYPE_ACL_DTYPE_NOT_ALLOWED_S 21\n+#define E830_GL_MDCK_TDAT_TCLAN_DESC_TYPE_ACL_DTYPE_NOT_ALLOWED_M BIT(21)\n+#define E830_GL_TPB_LOCAL_TOPO\t\t\t0x000996F4 /* Reset Source: CORER */\n+#define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_S 0\n+#define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_M BIT(0)\n+#define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_S\t1\n+#define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_M\tMAKEMASK(0x3, 1)\n+#define E830_GL_TPB_PM_RESET\t\t\t0x000996F0 /* Reset Source: CORER */\n+#define E830_GL_TPB_PM_RESET_MAC_PM_RESET_S\t0\n+#define E830_GL_TPB_PM_RESET_MAC_PM_RESET_M\tBIT(0)\n+#define E830_GL_TPB_PM_RESET_RPB_PM_RESET_S\t1\n+#define E830_GL_TPB_PM_RESET_RPB_PM_RESET_M\tBIT(1)\n+#define E830_GLTPB_100G_MAC_FC_THRESH1\t\t0x00099724 /* Reset Source: CORER */\n+#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_S 0\n+#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_S 16\n+#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_GLTPB_100G_RPB_FC_THRESH0\t\t0x0009963C /* Reset Source: CORER */\n+#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_S 0\n+#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_S 16\n+#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_GLTPB_100G_RPB_FC_THRESH1\t\t0x00099728 /* Reset Source: CORER */\n+#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_S 0\n+#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_S 16\n+#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_S\t12\n+#define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_M\tMAKEMASK(0xFFFF, 12)\n+#define E830_PF0INT_OICR_CPM_PTM_COMP_S\t\t8\n+#define E830_PF0INT_OICR_CPM_PTM_COMP_M\t\tBIT(8)\n+#define E830_PF0INT_OICR_CPM_RSV4_S\t\t9\n+#define E830_PF0INT_OICR_CPM_RSV4_M\t\tBIT(9)\n+#define E830_PF0INT_OICR_CPM_RSV5_S\t\t10\n+#define E830_PF0INT_OICR_CPM_RSV5_M\t\tBIT(10)\n+#define E830_PF0INT_OICR_HLP_PTM_COMP_S\t\t8\n+#define E830_PF0INT_OICR_HLP_PTM_COMP_M\t\tBIT(8)\n+#define E830_PF0INT_OICR_HLP_RSV4_S\t\t9\n+#define E830_PF0INT_OICR_HLP_RSV4_M\t\tBIT(9)\n+#define E830_PF0INT_OICR_HLP_RSV5_S\t\t10\n+#define E830_PF0INT_OICR_HLP_RSV5_M\t\tBIT(10)\n+#define E830_PF0INT_OICR_PSM_PTM_COMP_S\t\t8\n+#define E830_PF0INT_OICR_PSM_PTM_COMP_M\t\tBIT(8)\n+#define E830_PF0INT_OICR_PSM_RSV4_S\t\t9\n+#define E830_PF0INT_OICR_PSM_RSV4_M\t\tBIT(9)\n+#define E830_PF0INT_OICR_PSM_RSV5_S\t\t10\n+#define E830_PF0INT_OICR_PSM_RSV5_M\t\tBIT(10)\n+#define E830_PFINT_OICR_PTM_COMP_S\t\t8\n+#define E830_PFINT_OICR_PTM_COMP_M\t\tBIT(8)\n+#define E830_PFINT_OICR_RSV4_S\t\t\t9\n+#define E830_PFINT_OICR_RSV4_M\t\t\tBIT(9)\n+#define E830_PFINT_OICR_RSV5_S\t\t\t10\n+#define E830_PFINT_OICR_RSV5_M\t\t\tBIT(10)\n+#define E830_GLQF_FLAT_QTABLE(_i)\t\t(0x00488000 + ((_i) * 4)) /* _i=0...6143 */ /* Reset Source: CORER */\n+#define E830_GLQF_FLAT_QTABLE_MAX_INDEX\t\t6143\n+#define E830_GLQF_FLAT_QTABLE_QINDEX_0_S\t0\n+#define E830_GLQF_FLAT_QTABLE_QINDEX_0_M\tMAKEMASK(0x7FF, 0)\n+#define E830_GLQF_FLAT_QTABLE_QINDEX_1_S\t16\n+#define E830_GLQF_FLAT_QTABLE_QINDEX_1_M\tMAKEMASK(0x7FF, 16)\n+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA\t0x001E3854 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0\n+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16\n+#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH\t0x001E3864 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0\n+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16\n+#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA\t0x001E3858 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0\n+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_S 16\n+#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH\t0x001E3868 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0\n+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_S 16\n+#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA\t0x001E385C /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0\n+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_S 16\n+#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH\t0x001E386C /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0\n+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_S 16\n+#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA\t0x001E3860 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0\n+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_S 16\n+#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH\t0x001E3870 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0\n+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_S 16\n+#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG\t\t0x001E3808 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_S 0\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_M BIT(0)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ENA_S 1\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ENA_M BIT(1)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED1_S 3\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED1_M BIT(3)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PROMIS_EN_S 4\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PROMIS_EN_M BIT(4)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED2_S 5\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED2_M BIT(5)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_CRC_FWD_S 6\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_CRC_FWD_M BIT(6)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_FWD_S 7\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_FWD_M BIT(7)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_IGNORE_S 8\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_IGNORE_M BIT(8)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ADDR_INS_S 9\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ADDR_INS_M BIT(9)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_LOOP_ENA_S 10\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_LOOP_ENA_M BIT(10)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_PAD_EN_S 11\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_PAD_EN_M BIT(11)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_SW_RESET_S 12\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_SW_RESET_M BIT(12)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_CNTL_FRM_ENA_S 13\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_CNTL_FRM_ENA_M BIT(13)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED3_S 14\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED3_M BIT(14)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PHY_TXENA_S 15\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PHY_TXENA_M BIT(15)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_FORCE_SEND__S 16\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_FORCE_SEND__M BIT(16)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_NO_LGTH_CHECK_S 17\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_NO_LGTH_CHECK_M BIT(17)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED5_S 18\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED5_M BIT(18)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PFC_MODE_S 19\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PFC_MODE_M BIT(19)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_PFC_COMP_S 20\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_PFC_COMP_M BIT(20)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_SFD_ANY_S 21\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_SFD_ANY_M BIT(21)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FLUSH_S 22\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FLUSH_M BIT(22)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_TX_STOP_S 25\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_TX_STOP_M BIT(25)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FIFO_RESET_S 26\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FIFO_RESET_M BIT(26)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_HDL_DIS_S 27\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_HDL_DIS_M BIT(27)\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_INV_LOOP_S 31\n+#define E830_PRTMAC_200G_COMMAND_CONFIG_INV_LOOP_M BIT(31)\n+#define E830_PRTMAC_200G_CRC_INV_M\t\t0x001E384C /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_S 0\n+#define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_200G_FRM_LENGTH\t\t0x001E3814 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_S 0\n+#define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_S\t16\n+#define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_M\tMAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD\t\t0x001E382C /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_S 0\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_M MAKEMASK(0x3F, 0)\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD_RESERVED_2_S 6\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD_RESERVED_2_M MAKEMASK(0x3, 6)\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD_MCAST_EN_S 8\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD_MCAST_EN_M BIT(8)\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD_RESERVED1_S 9\n+#define E830_PRTMAC_200G_HASHTABLE_LOAD_RESERVED1_M MAKEMASK(0x7FFFFF, 9)\n+#define E830_PRTMAC_200G_MAC_ADDR_0\t\t0x001E380C /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_S 0\n+#define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_200G_MAC_ADDR_1\t\t0x001E3810 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_S 0\n+#define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS\t0x001E3830 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_S 0\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0)\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_RD_ERR_S 1\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_RD_ERR_M BIT(1)\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_S 2\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2)\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_S 5\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_M BIT(5)\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLS_45_EN_S 6\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLS_45_EN_M BIT(6)\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_S 7\n+#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7)\n+#define E830_PRTMAC_200G_MDIO_COMMAND\t\t0x001E3834 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_S 0\n+#define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_200G_MDIO_DATA\t\t0x001E3838 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_S\t0\n+#define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_200G_MDIO_REGADDR\t\t0x001E383C /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_S 0\n+#define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_200G_REVISION\t\t0x001E3800 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_REVISION_CORE_REVISION_S 0\n+#define E830_PRTMAC_200G_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0)\n+#define E830_PRTMAC_200G_REVISION_CORE_VERSION_S 8\n+#define E830_PRTMAC_200G_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8)\n+#define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_S 16\n+#define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_RX_PAUSE_STATUS\t0x001E3874 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0\n+#define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0)\n+#define E830_PRTMAC_200G_SCRATCH\t\t0x001E3804 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_SCRATCH_SCRATCH_S\t0\n+#define E830_PRTMAC_200G_SCRATCH_SCRATCH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_200G_STATUS\t\t\t0x001E3840 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_S\t0\n+#define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_M\tBIT(0)\n+#define E830_PRTMAC_200G_STATUS_RX_REM_FAULT_S\t1\n+#define E830_PRTMAC_200G_STATUS_RX_REM_FAULT_M\tBIT(1)\n+#define E830_PRTMAC_200G_STATUS_PHY_LOS_S\t2\n+#define E830_PRTMAC_200G_STATUS_PHY_LOS_M\tBIT(2)\n+#define E830_PRTMAC_200G_STATUS_TS_AVAIL_S\t3\n+#define E830_PRTMAC_200G_STATUS_TS_AVAIL_M\tBIT(3)\n+#define E830_PRTMAC_200G_STATUS_RESERVED_5_S\t4\n+#define E830_PRTMAC_200G_STATUS_RESERVED_5_M\tBIT(4)\n+#define E830_PRTMAC_200G_STATUS_TX_EMPTY_S\t5\n+#define E830_PRTMAC_200G_STATUS_TX_EMPTY_M\tBIT(5)\n+#define E830_PRTMAC_200G_STATUS_RX_EMPTY_S\t6\n+#define E830_PRTMAC_200G_STATUS_RX_EMPTY_M\tBIT(6)\n+#define E830_PRTMAC_200G_STATUS_RESERVED1_S\t7\n+#define E830_PRTMAC_200G_STATUS_RESERVED1_M\tBIT(7)\n+#define E830_PRTMAC_200G_STATUS_TX_ISIDLE_S\t8\n+#define E830_PRTMAC_200G_STATUS_TX_ISIDLE_M\tBIT(8)\n+#define E830_PRTMAC_200G_STATUS_RESERVED2_S\t9\n+#define E830_PRTMAC_200G_STATUS_RESERVED2_M\tMAKEMASK(0x7FFFFF, 9)\n+#define E830_PRTMAC_200G_TS_TIMESTAMP\t\t0x001E387C /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_S 0\n+#define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS\t0x001E3820 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0\n+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_S 16\n+#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_200G_TX_IPG_LENGTH\t\t0x001E3844 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_S 0\n+#define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x7F, 0)\n+#define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_S 19\n+#define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_M MAKEMASK(0x1FFF, 19)\n+#define E830_PRTMAC_200G_XIF_MODE\t\t0x001E3880 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_S\t0\n+#define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_M\tMAKEMASK(0x1F, 0)\n+#define E830_PRTMAC_200G_XIF_MODE_ONE_STEP_ENA_S 5\n+#define E830_PRTMAC_200G_XIF_MODE_ONE_STEP_ENA_M BIT(5)\n+#define E830_PRTMAC_200G_XIF_MODE_PFC_PULSE_MODE_S 17\n+#define E830_PRTMAC_200G_XIF_MODE_PFC_PULSE_MODE_M BIT(17)\n+#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_MODE_S\t18\n+#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_MODE_M\tBIT(18)\n+#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_16PRI_S 19\n+#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_16PRI_M BIT(19)\n+#define E830_PRTMAC_CF_GEN_STATUS\t\t0x001E33C0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_S\t0\n+#define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_M\tBIT(0)\n+#define E830_PRTMAC_CL01_PAUSE_QUANTA\t\t0x001E32A0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0\n+#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16\n+#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_CL01_QUANTA_THRESH\t\t0x001E3320 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0\n+#define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16\n+#define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_CL23_PAUSE_QUANTA\t\t0x001E32C0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0\n+#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_S 16\n+#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_CL23_QUANTA_THRESH\t\t0x001E3340 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0\n+#define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_S 16\n+#define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_CL45_PAUSE_QUANTA\t\t0x001E32E0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0\n+#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_S 16\n+#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_CL45_QUANTA_THRESH\t\t0x001E3360 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0\n+#define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_S 16\n+#define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_CL67_PAUSE_QUANTA\t\t0x001E3300 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0\n+#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_S 16\n+#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_CL67_QUANTA_THRESH\t\t0x001E3380 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0\n+#define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_S 16\n+#define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_COMMAND_CONFIG\t\t0x001E3040 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_S\t0\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_M\tBIT(0)\n+#define E830_PRTMAC_COMMAND_CONFIG_RX_ENA_S\t1\n+#define E830_PRTMAC_COMMAND_CONFIG_RX_ENA_M\tBIT(1)\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED1_S\t3\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED1_M\tBIT(3)\n+#define E830_PRTMAC_COMMAND_CONFIG_PROMIS_EN_S\t4\n+#define E830_PRTMAC_COMMAND_CONFIG_PROMIS_EN_M\tBIT(4)\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED2_S\t5\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED2_M\tBIT(5)\n+#define E830_PRTMAC_COMMAND_CONFIG_CRC_FWD_S\t6\n+#define E830_PRTMAC_COMMAND_CONFIG_CRC_FWD_M\tBIT(6)\n+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_FWD_S\t7\n+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_FWD_M\tBIT(7)\n+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_IGNORE_S 8\n+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_IGNORE_M BIT(8)\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_ADDR_INS_S 9\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_ADDR_INS_M BIT(9)\n+#define E830_PRTMAC_COMMAND_CONFIG_LOOP_ENA_S\t10\n+#define E830_PRTMAC_COMMAND_CONFIG_LOOP_ENA_M\tBIT(10)\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_PAD_EN_S\t11\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_PAD_EN_M\tBIT(11)\n+#define E830_PRTMAC_COMMAND_CONFIG_SW_RESET_S\t12\n+#define E830_PRTMAC_COMMAND_CONFIG_SW_RESET_M\tBIT(12)\n+#define E830_PRTMAC_COMMAND_CONFIG_CNTL_FRM_ENA_S 13\n+#define E830_PRTMAC_COMMAND_CONFIG_CNTL_FRM_ENA_M BIT(13)\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED3_S\t14\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED3_M\tBIT(14)\n+#define E830_PRTMAC_COMMAND_CONFIG_PHY_TXENA_S\t15\n+#define E830_PRTMAC_COMMAND_CONFIG_PHY_TXENA_M\tBIT(15)\n+#define E830_PRTMAC_COMMAND_CONFIG_FORCE_SEND__S 16\n+#define E830_PRTMAC_COMMAND_CONFIG_FORCE_SEND__M BIT(16)\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED4_S\t17\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED4_M\tBIT(17)\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED5_S\t18\n+#define E830_PRTMAC_COMMAND_CONFIG_RESERVED5_M\tBIT(18)\n+#define E830_PRTMAC_COMMAND_CONFIG_PFC_MODE_S\t19\n+#define E830_PRTMAC_COMMAND_CONFIG_PFC_MODE_M\tBIT(19)\n+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_PFC_COMP_S 20\n+#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_PFC_COMP_M BIT(20)\n+#define E830_PRTMAC_COMMAND_CONFIG_RX_SFD_ANY_S\t21\n+#define E830_PRTMAC_COMMAND_CONFIG_RX_SFD_ANY_M\tBIT(21)\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_FLUSH_S\t22\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_FLUSH_M\tBIT(22)\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_LOWP_ENA_S 23\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_LOWP_ENA_M BIT(23)\n+#define E830_PRTMAC_COMMAND_CONFIG_REG_LOWP_RXEMPTY_S 24\n+#define E830_PRTMAC_COMMAND_CONFIG_REG_LOWP_RXEMPTY_M BIT(24)\n+#define E830_PRTMAC_COMMAND_CONFIG_FLT_TX_STOP_S 25\n+#define E830_PRTMAC_COMMAND_CONFIG_FLT_TX_STOP_M BIT(25)\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_FIFO_RESET_S 26\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_FIFO_RESET_M BIT(26)\n+#define E830_PRTMAC_COMMAND_CONFIG_FLT_HDL_DIS_S 27\n+#define E830_PRTMAC_COMMAND_CONFIG_FLT_HDL_DIS_M BIT(27)\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_PAUSE_DIS_S 28\n+#define E830_PRTMAC_COMMAND_CONFIG_TX_PAUSE_DIS_M BIT(28)\n+#define E830_PRTMAC_COMMAND_CONFIG_RX_PAUSE_DIS_S 29\n+#define E830_PRTMAC_COMMAND_CONFIG_RX_PAUSE_DIS_M BIT(29)\n+#define E830_PRTMAC_COMMAND_CONFIG_SHORT_PREAM_S 30\n+#define E830_PRTMAC_COMMAND_CONFIG_SHORT_PREAM_M BIT(30)\n+#define E830_PRTMAC_COMMAND_CONFIG_NO_PREAM_S\t31\n+#define E830_PRTMAC_COMMAND_CONFIG_NO_PREAM_M\tBIT(31)\n+#define E830_PRTMAC_CRC_INV_M\t\t\t0x001E3260 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_S\t0\n+#define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_CRC_MODE\t\t\t0x001E3240 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CRC_MODE_RESERVED_1_S\t0\n+#define E830_PRTMAC_CRC_MODE_RESERVED_1_M\tMAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_CRC_MODE_DISABLE_RX_CRC_CHECKING_S 16\n+#define E830_PRTMAC_CRC_MODE_DISABLE_RX_CRC_CHECKING_M BIT(16)\n+#define E830_PRTMAC_CRC_MODE_RESERVED1_S\t17\n+#define E830_PRTMAC_CRC_MODE_RESERVED1_M\tBIT(17)\n+#define E830_PRTMAC_CRC_MODE_ONE_BYTE_CRC_S\t18\n+#define E830_PRTMAC_CRC_MODE_ONE_BYTE_CRC_M\tBIT(18)\n+#define E830_PRTMAC_CRC_MODE_TWO_BYTES_CRC_S\t19\n+#define E830_PRTMAC_CRC_MODE_TWO_BYTES_CRC_M\tBIT(19)\n+#define E830_PRTMAC_CRC_MODE_ZERO_BYTE_CRC_S\t20\n+#define E830_PRTMAC_CRC_MODE_ZERO_BYTE_CRC_M\tBIT(20)\n+#define E830_PRTMAC_CRC_MODE_RESERVED2_S\t21\n+#define E830_PRTMAC_CRC_MODE_RESERVED2_M\tMAKEMASK(0x7FF, 21)\n+#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE\t\t0x001E2180 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S 0\n+#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)\n+#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE\t\t0x001E21A0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S 0\n+#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)\n+#define E830_PRTMAC_FRM_LENGTH\t\t\t0x001E30A0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_S\t0\n+#define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_M\tMAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_FRM_LENGTH_TX_MTU_S\t\t16\n+#define E830_PRTMAC_FRM_LENGTH_TX_MTU_M\t\tMAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_MAC_ADDR_0\t\t\t0x001E3060 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_S\t0\n+#define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_MAC_ADDR_1\t\t\t0x001E3080 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_S\t0\n+#define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_M\tMAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_MDIO_CFG_STATUS\t\t0x001E3180 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_S\t0\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_M\tBIT(0)\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_RD_ERR_S 1\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_RD_ERR_M BIT(1)\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_S 2\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2)\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_S 5\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_M BIT(5)\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLS_45_EN_S 6\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLS_45_EN_M BIT(6)\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_S 7\n+#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7)\n+#define E830_PRTMAC_MDIO_COMMAND\t\t0x001E31A0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_S\t0\n+#define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_MDIO_DATA\t\t\t0x001E31C0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_MDIO_DATA_MDIO_DATA_S\t0\n+#define E830_PRTMAC_MDIO_DATA_MDIO_DATA_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_MDIO_REGADDR\t\t0x001E31E0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_S\t0\n+#define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_REVISION\t\t\t0x001E3000 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_REVISION_CORE_REVISION_S\t0\n+#define E830_PRTMAC_REVISION_CORE_REVISION_M\tMAKEMASK(0xFF, 0)\n+#define E830_PRTMAC_REVISION_CORE_VERSION_S\t8\n+#define E830_PRTMAC_REVISION_CORE_VERSION_M\tMAKEMASK(0xFF, 8)\n+#define E830_PRTMAC_REVISION_CUSTOMER_VERSION_S\t16\n+#define E830_PRTMAC_REVISION_CUSTOMER_VERSION_M\tMAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_RX_PAUSE_STATUS\t\t0x001E33A0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0\n+#define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0)\n+#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_S 12\n+#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 12)\n+#define E830_PRTMAC_SCRATCH\t\t\t0x001E3020 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_SCRATCH_SCRATCH_S\t\t0\n+#define E830_PRTMAC_SCRATCH_SCRATCH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_STATUS\t\t\t0x001E3200 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_STATUS_RX_LOC_FAULT_S\t0\n+#define E830_PRTMAC_STATUS_RX_LOC_FAULT_M\tBIT(0)\n+#define E830_PRTMAC_STATUS_RX_REM_FAULT_S\t1\n+#define E830_PRTMAC_STATUS_RX_REM_FAULT_M\tBIT(1)\n+#define E830_PRTMAC_STATUS_PHY_LOS_S\t\t2\n+#define E830_PRTMAC_STATUS_PHY_LOS_M\t\tBIT(2)\n+#define E830_PRTMAC_STATUS_TS_AVAIL_S\t\t3\n+#define E830_PRTMAC_STATUS_TS_AVAIL_M\t\tBIT(3)\n+#define E830_PRTMAC_STATUS_RX_LOWP_S\t\t4\n+#define E830_PRTMAC_STATUS_RX_LOWP_M\t\tBIT(4)\n+#define E830_PRTMAC_STATUS_TX_EMPTY_S\t\t5\n+#define E830_PRTMAC_STATUS_TX_EMPTY_M\t\tBIT(5)\n+#define E830_PRTMAC_STATUS_RX_EMPTY_S\t\t6\n+#define E830_PRTMAC_STATUS_RX_EMPTY_M\t\tBIT(6)\n+#define E830_PRTMAC_STATUS_RX_LINT_FAULT_S\t7\n+#define E830_PRTMAC_STATUS_RX_LINT_FAULT_M\tBIT(7)\n+#define E830_PRTMAC_STATUS_TX_ISIDLE_S\t\t8\n+#define E830_PRTMAC_STATUS_TX_ISIDLE_M\t\tBIT(8)\n+#define E830_PRTMAC_STATUS_RESERVED_10_S\t9\n+#define E830_PRTMAC_STATUS_RESERVED_10_M\tMAKEMASK(0x7FFFFF, 9)\n+#define E830_PRTMAC_TS_RX_PCS_LATENCY\t\t0x001E2220 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_S 0\n+#define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_TS_TIMESTAMP\t\t0x001E33E0 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_S\t0\n+#define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_TS_TX_MEM_VALID_H\t\t0x001E2020 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_S 0\n+#define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_TS_TX_MEM_VALID_L\t\t0x001E2000 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_S 0\n+#define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PRTMAC_TS_TX_PCS_LATENCY\t\t0x001E2200 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_S 0\n+#define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_TX_FIFO_SECTIONS\t\t0x001E3100 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0\n+#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0)\n+#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_S 16\n+#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_TX_IPG_LENGTH\t\t0x001E3220 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_S\t0\n+#define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_M\tMAKEMASK(0x3F, 0)\n+#define E830_PRTMAC_TX_IPG_LENGTH_RESERVED1_S\t6\n+#define E830_PRTMAC_TX_IPG_LENGTH_RESERVED1_M\tMAKEMASK(0x3, 6)\n+#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_S 8\n+#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_M MAKEMASK(0xFF, 8)\n+#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_S 16\n+#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_M MAKEMASK(0xFFFF, 16)\n+#define E830_PRTMAC_XIF_MODE\t\t\t0x001E3400 /* Reset Source: GLOBR */\n+#define E830_PRTMAC_XIF_MODE_XGMII_ENA_S\t0\n+#define E830_PRTMAC_XIF_MODE_XGMII_ENA_M\tBIT(0)\n+#define E830_PRTMAC_XIF_MODE_RESERVED_2_S\t1\n+#define E830_PRTMAC_XIF_MODE_RESERVED_2_M\tMAKEMASK(0x7, 1)\n+#define E830_PRTMAC_XIF_MODE_PAUSETIMERX8_S\t4\n+#define E830_PRTMAC_XIF_MODE_PAUSETIMERX8_M\tBIT(4)\n+#define E830_PRTMAC_XIF_MODE_ONE_STEP_ENA_S\t5\n+#define E830_PRTMAC_XIF_MODE_ONE_STEP_ENA_M\tBIT(5)\n+#define E830_PRTMAC_XIF_MODE_RX_PAUSE_BYPASS_S\t6\n+#define E830_PRTMAC_XIF_MODE_RX_PAUSE_BYPASS_M\tBIT(6)\n+#define E830_PRTMAC_XIF_MODE_RESERVED1_S\t7\n+#define E830_PRTMAC_XIF_MODE_RESERVED1_M\tBIT(7)\n+#define E830_PRTMAC_XIF_MODE_TX_MAC_RS_ERR_S\t8\n+#define E830_PRTMAC_XIF_MODE_TX_MAC_RS_ERR_M\tBIT(8)\n+#define E830_PRTMAC_XIF_MODE_TS_DELTA_MODE_S\t9\n+#define E830_PRTMAC_XIF_MODE_TS_DELTA_MODE_M\tBIT(9)\n+#define E830_PRTMAC_XIF_MODE_TS_DELAY_MODE_S\t10\n+#define E830_PRTMAC_XIF_MODE_TS_DELAY_MODE_M\tBIT(10)\n+#define E830_PRTMAC_XIF_MODE_TS_BINARY_MODE_S\t11\n+#define E830_PRTMAC_XIF_MODE_TS_BINARY_MODE_M\tBIT(11)\n+#define E830_PRTMAC_XIF_MODE_TS_UPD64_MODE_S\t12\n+#define E830_PRTMAC_XIF_MODE_TS_UPD64_MODE_M\tBIT(12)\n+#define E830_PRTMAC_XIF_MODE_RESERVED2_S\t13\n+#define E830_PRTMAC_XIF_MODE_RESERVED2_M\tMAKEMASK(0x7, 13)\n+#define E830_PRTMAC_XIF_MODE_RX_CNT_MODE_S\t16\n+#define E830_PRTMAC_XIF_MODE_RX_CNT_MODE_M\tBIT(16)\n+#define E830_PRTMAC_XIF_MODE_PFC_PULSE_MODE_S\t17\n+#define E830_PRTMAC_XIF_MODE_PFC_PULSE_MODE_M\tBIT(17)\n+#define E830_PRTMAC_XIF_MODE_PFC_LP_MODE_S\t18\n+#define E830_PRTMAC_XIF_MODE_PFC_LP_MODE_M\tBIT(18)\n+#define E830_PRTMAC_XIF_MODE_PFC_LP_16PRI_S\t19\n+#define E830_PRTMAC_XIF_MODE_PFC_LP_16PRI_M\tBIT(19)\n+#define E830_PRTMAC_XIF_MODE_TS_SFD_ENA_S\t20\n+#define E830_PRTMAC_XIF_MODE_TS_SFD_ENA_M\tBIT(20)\n+#define E830_PRTMAC_XIF_MODE_RESERVED3_S\t21\n+#define E830_PRTMAC_XIF_MODE_RESERVED3_M\tMAKEMASK(0x7FF, 21)\n+#define E830_PRTTSYN_TXTIME_H(_i)\t\t(0x001E5004 + ((_i) * 64)) /* _i=0...63 */ /* Reset Source: GLOBR */\n+#define E830_PRTTSYN_TXTIME_H_MAX_INDEX\t\t63\n+#define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_S 0\n+#define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_M MAKEMASK(0xFF, 0)\n+#define E830_PRTTSYN_TXTIME_L(_i)\t\t(0x001E5000 + ((_i) * 64)) /* _i=0...63 */ /* Reset Source: GLOBR */\n+#define E830_PRTTSYN_TXTIME_L_MAX_INDEX\t\t63\n+#define E830_PRTTSYN_TXTIME_L_TX_VALID_S\t0\n+#define E830_PRTTSYN_TXTIME_L_TX_VALID_M\tBIT(0)\n+#define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_S 1\n+#define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_M MAKEMASK(0x7FFFFFFF, 1)\n+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SW_ABOVE_HW_TAIL_S 28\n+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SW_ABOVE_HW_TAIL_M BIT(28)\n+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SAME_TAIL_S 29\n+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SAME_TAIL_M BIT(29)\n+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_TAIL_GE_QLEN_S 30\n+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_TAIL_GE_QLEN_M BIT(30)\n+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_UR_S\t31\n+#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_UR_M\tBIT(31)\n+#define E830_GL_MDET_HIF_ERR_FIFO\t\t0x00096844 /* Reset Source: CORER */\n+#define E830_GL_MDET_HIF_ERR_FIFO_FUNC_NUM_S\t0\n+#define E830_GL_MDET_HIF_ERR_FIFO_FUNC_NUM_M\tMAKEMASK(0x3FF, 0)\n+#define E830_GL_MDET_HIF_ERR_FIFO_PF_NUM_S\t10\n+#define E830_GL_MDET_HIF_ERR_FIFO_PF_NUM_M\tMAKEMASK(0x7, 10)\n+#define E830_GL_MDET_HIF_ERR_FIFO_FUNC_TYPE_S\t13\n+#define E830_GL_MDET_HIF_ERR_FIFO_FUNC_TYPE_M\tMAKEMASK(0x3, 13)\n+#define E830_GL_MDET_HIF_ERR_FIFO_MAL_TYPE_S\t15\n+#define E830_GL_MDET_HIF_ERR_FIFO_MAL_TYPE_M\tMAKEMASK(0x1F, 15)\n+#define E830_GL_MDET_HIF_ERR_FIFO_FIFO_FULL_S\t20\n+#define E830_GL_MDET_HIF_ERR_FIFO_FIFO_FULL_M\tBIT(20)\n+#define E830_GL_MDET_HIF_ERR_FIFO_VALID_S\t21\n+#define E830_GL_MDET_HIF_ERR_FIFO_VALID_M\tBIT(21)\n+#define E830_GL_MDET_HIF_ERR_PF_CNT(_i)\t\t(0x00096804 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_HIF_ERR_PF_CNT_MAX_INDEX\t7\n+#define E830_GL_MDET_HIF_ERR_PF_CNT_CNT_S\t0\n+#define E830_GL_MDET_HIF_ERR_PF_CNT_CNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GL_MDET_HIF_ERR_VF(_i)\t\t(0x00096824 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GL_MDET_HIF_ERR_VF_MAX_INDEX\t7\n+#define E830_GL_MDET_HIF_ERR_VF_VF_MAL_EVENT_S\t0\n+#define E830_GL_MDET_HIF_ERR_VF_VF_MAL_EVENT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PF_MDET_HIF_ERR\t\t\t0x00096880 /* Reset Source: CORER */\n+#define E830_PF_MDET_HIF_ERR_VALID_S\t\t0\n+#define E830_PF_MDET_HIF_ERR_VALID_M\t\tBIT(0)\n+#define E830_VM_MDET_TX_TCLAN(_i)\t\t(0x000FC000 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define E830_VM_MDET_TX_TCLAN_MAX_INDEX\t\t767\n+#define E830_VM_MDET_TX_TCLAN_VALID_S\t\t0\n+#define E830_VM_MDET_TX_TCLAN_VALID_M\t\tBIT(0)\n+#define E830_VP_MDET_HIF_ERR(_VF)\t\t(0x00096C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_VP_MDET_HIF_ERR_MAX_INDEX\t\t255\n+#define E830_VP_MDET_HIF_ERR_VALID_S\t\t0\n+#define E830_VP_MDET_HIF_ERR_VALID_M\t\tBIT(0)\n+#define E830_GLNVM_FLA_GLOBAL_LOCKED_S\t\t7\n+#define E830_GLNVM_FLA_GLOBAL_LOCKED_M\t\tBIT(7)\n+#define E830_DMA_AGENT_AT0\t\t\t0x000BE268 /* Reset Source: PCIR */\n+#define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_S 0\n+#define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0)\n+#define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_S 2\n+#define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2)\n+#define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_S 4\n+#define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4)\n+#define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_S 6\n+#define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6)\n+#define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_S 8\n+#define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8)\n+#define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_S 10\n+#define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10)\n+#define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_S 12\n+#define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12)\n+#define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_S\t14\n+#define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_M\tMAKEMASK(0x3, 14)\n+#define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_S\t16\n+#define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_M\tMAKEMASK(0x3, 16)\n+#define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_S 18\n+#define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18)\n+#define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_S 20\n+#define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20)\n+#define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_S 22\n+#define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22)\n+#define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_S 24\n+#define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24)\n+#define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_S 26\n+#define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26)\n+#define E830_DMA_AGENT_AT1\t\t\t0x000BE26C /* Reset Source: PCIR */\n+#define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_S 0\n+#define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0)\n+#define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_S 2\n+#define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2)\n+#define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_S 4\n+#define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4)\n+#define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_S 6\n+#define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6)\n+#define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_S 8\n+#define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8)\n+#define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_S 10\n+#define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10)\n+#define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_S 12\n+#define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12)\n+#define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_S\t14\n+#define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_M\tMAKEMASK(0x3, 14)\n+#define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_S\t16\n+#define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_M\tMAKEMASK(0x3, 16)\n+#define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_S 18\n+#define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18)\n+#define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_S 20\n+#define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20)\n+#define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_S 22\n+#define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22)\n+#define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_S 24\n+#define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24)\n+#define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_S 26\n+#define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26)\n+#define E830_GLPCI_CAPSUP_DOE_EN_S\t\t1\n+#define E830_GLPCI_CAPSUP_DOE_EN_M\t\tBIT(1)\n+#define E830_GLPCI_CAPSUP_GEN5_EXT_EN_S\t\t12\n+#define E830_GLPCI_CAPSUP_GEN5_EXT_EN_M\t\tBIT(12)\n+#define E830_GLPCI_CAPSUP_PTM_EN_S\t\t13\n+#define E830_GLPCI_CAPSUP_PTM_EN_M\t\tBIT(13)\n+#define E830_GLPCI_CAPSUP_SNPS_RAS_EN_S\t\t14\n+#define E830_GLPCI_CAPSUP_SNPS_RAS_EN_M\t\tBIT(14)\n+#define E830_GLPCI_CAPSUP_SIOV_EN_S\t\t15\n+#define E830_GLPCI_CAPSUP_SIOV_EN_M\t\tBIT(15)\n+#define E830_GLPCI_DOE_BUSY_STATUS\t\t0x0009DF70 /* Reset Source: PCIR */\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_S\t0\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_M\tBIT(0)\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_EMPR_S\t1\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_EMPR_M\tBIT(1)\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_PCIER_S\t2\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_PCIER_M\tBIT(2)\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FLR_S\t3\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FLR_M\tBIT(3)\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_CFG_ABORT_S 4\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_CFG_ABORT_M BIT(4)\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FW_S\t5\n+#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FW_M\tBIT(5)\n+#define E830_GLPCI_DOE_CFG\t\t\t0x0009DF54 /* Reset Source: PCIR */\n+#define E830_GLPCI_DOE_CFG_ENABLE_S\t\t0\n+#define E830_GLPCI_DOE_CFG_ENABLE_M\t\tBIT(0)\n+#define E830_GLPCI_DOE_CFG_ITR_SUPPORT_S\t1\n+#define E830_GLPCI_DOE_CFG_ITR_SUPPORT_M\tBIT(1)\n+#define E830_GLPCI_DOE_CFG_POISON_CFGWR_PIOSF_EP_BIT_S 2\n+#define E830_GLPCI_DOE_CFG_POISON_CFGWR_PIOSF_EP_BIT_M BIT(2)\n+#define E830_GLPCI_DOE_CFG_POISON_CFGWR_SBIOSF_AER_MSG_S 3\n+#define E830_GLPCI_DOE_CFG_POISON_CFGWR_SBIOSF_AER_MSG_M BIT(3)\n+#define E830_GLPCI_DOE_CFG_MSIX_VECTOR_S\t8\n+#define E830_GLPCI_DOE_CFG_MSIX_VECTOR_M\tMAKEMASK(0x7FF, 8)\n+#define E830_GLPCI_DOE_CTRL\t\t\t0x0009DF60 /* Reset Source: PCIR */\n+#define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_S\t0\n+#define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_M\tBIT(0)\n+#define E830_GLPCI_DOE_CTRL_DOE_CFG_ERR_SET_S\t1\n+#define E830_GLPCI_DOE_CTRL_DOE_CFG_ERR_SET_M\tBIT(1)\n+#define E830_GLPCI_DOE_DBG\t\t\t0x0009DF6C /* Reset Source: PCIR */\n+#define E830_GLPCI_DOE_DBG_CFG_BUSY_S\t\t0\n+#define E830_GLPCI_DOE_DBG_CFG_BUSY_M\t\tBIT(0)\n+#define E830_GLPCI_DOE_DBG_CFG_DATA_OBJECT_READY_S 1\n+#define E830_GLPCI_DOE_DBG_CFG_DATA_OBJECT_READY_M BIT(1)\n+#define E830_GLPCI_DOE_DBG_CFG_ERROR_S\t\t2\n+#define E830_GLPCI_DOE_DBG_CFG_ERROR_M\t\tBIT(2)\n+#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_ENABLE_S 3\n+#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_ENABLE_M BIT(3)\n+#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_STATUS_S 4\n+#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_STATUS_M BIT(4)\n+#define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_S\t8\n+#define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_M\tMAKEMASK(0x1FF, 8)\n+#define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_S\t20\n+#define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_M\tMAKEMASK(0x1FF, 20)\n+#define E830_GLPCI_DOE_ERR_EN\t\t\t0x0009DF64 /* Reset Source: PCIR */\n+#define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_S 0\n+#define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_M BIT(0)\n+#define E830_GLPCI_DOE_ERR_EN_RD_RESP_BUF_ECC_ERR_EN_S 1\n+#define E830_GLPCI_DOE_ERR_EN_RD_RESP_BUF_ECC_ERR_EN_M BIT(1)\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_CFG_POISONED_EN_S 2\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_CFG_POISONED_EN_M BIT(2)\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_EN_S 3\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_EN_M BIT(3)\n+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_REQ_EN_S 4\n+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_REQ_EN_M BIT(4)\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_EN_S 5\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_EN_M BIT(5)\n+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_FW_EN_S 6\n+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_FW_EN_M BIT(6)\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_OVERFLOW_EN_S 7\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_OVERFLOW_EN_M BIT(7)\n+#define E830_GLPCI_DOE_ERR_EN_SW_GO_REQ_BUF_EMPTY_EN_S 8\n+#define E830_GLPCI_DOE_ERR_EN_SW_GO_REQ_BUF_EMPTY_EN_M BIT(8)\n+#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_READY_LOW_EN_S 9\n+#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_READY_LOW_EN_M BIT(9)\n+#define E830_GLPCI_DOE_ERR_EN_SW_REQ_DURING_MNG_RST_EN_S 10\n+#define E830_GLPCI_DOE_ERR_EN_SW_REQ_DURING_MNG_RST_EN_M BIT(10)\n+#define E830_GLPCI_DOE_ERR_EN_FW_SET_ERROR_EN_S\t11\n+#define E830_GLPCI_DOE_ERR_EN_FW_SET_ERROR_EN_M\tBIT(11)\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_EN_S 12\n+#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_EN_M BIT(12)\n+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_ABORT_EN_S 13\n+#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_ABORT_EN_M BIT(13)\n+#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_EN_S 14\n+#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_EN_M BIT(14)\n+#define E830_GLPCI_DOE_ERR_STATUS\t\t0x0009DF68 /* Reset Source: PCIR */\n+#define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_S 0\n+#define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_M BIT(0)\n+#define E830_GLPCI_DOE_ERR_STATUS_RD_RESP_BUF_ECC_ERR_S 1\n+#define E830_GLPCI_DOE_ERR_STATUS_RD_RESP_BUF_ECC_ERR_M BIT(1)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_CFG_POISONED_S 2\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_CFG_POISONED_M BIT(2)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_S 3\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_M BIT(3)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_REQ_S 4\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_REQ_M BIT(4)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_S 5\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_M BIT(5)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_FW_S 6\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_FW_M BIT(6)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_OVERFLOW_S 7\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_OVERFLOW_M BIT(7)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_REQ_BUF_EMPTY_S 8\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_REQ_BUF_EMPTY_M BIT(8)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_READY_LOW_S 9\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_READY_LOW_M BIT(9)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_REQ_DURING_MNG_RST_S 10\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_REQ_DURING_MNG_RST_M BIT(10)\n+#define E830_GLPCI_DOE_ERR_STATUS_FW_SET_ERROR_S 11\n+#define E830_GLPCI_DOE_ERR_STATUS_FW_SET_ERROR_M BIT(11)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_S 12\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_M BIT(12)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_ABORT_S 13\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_ABORT_M BIT(13)\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_S 14\n+#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_M BIT(14)\n+#define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_S\t24\n+#define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_M\tMAKEMASK(0x1F, 24)\n+#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS\t\t0x0009DF58 /* Reset Source: PCIR */\n+#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_S 0\n+#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0)\n+#define E830_GLPCI_DOE_RESP\t\t\t0x0009DF5C /* Reset Source: PCIR */\n+#define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_S\t0\n+#define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_M\tMAKEMASK(0x1FF, 0)\n+#define E830_GLPCI_DOE_RESP_READY_SET_S\t\t16\n+#define E830_GLPCI_DOE_RESP_READY_SET_M\t\tBIT(16)\n+#define E830_GLPCI_ERR_DBG\t\t\t0x0009DF84 /* Reset Source: PCIR */\n+#define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_S 0\n+#define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_M MAKEMASK(0x3, 0)\n+#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_SM_S\t2\n+#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_SM_M\tBIT(2)\n+#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_S 3\n+#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_M MAKEMASK(0x7, 3)\n+#define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_S 6\n+#define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_M MAKEMASK(0xF, 6)\n+#define E830_GLPCI_NPQ_CFG_HIGH_TO_S\t\t20\n+#define E830_GLPCI_NPQ_CFG_HIGH_TO_M\t\tBIT(20)\n+#define E830_GLPCI_NPQ_CFG_INC_150MS_TO_S\t21\n+#define E830_GLPCI_NPQ_CFG_INC_150MS_TO_M\tBIT(21)\n+#define E830_GLPCI_PUSH_PQM_CTRL\t\t0x0009DF74 /* Reset Source: POR */\n+#define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_S 0\n+#define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_M BIT(0)\n+#define E830_GLPCI_PUSH_PQM_CTRL_PF_TXTIME_RANGE_EN_S 1\n+#define E830_GLPCI_PUSH_PQM_CTRL_PF_TXTIME_RANGE_EN_M BIT(1)\n+#define E830_GLPCI_PUSH_PQM_CTRL_PF_4K_RANGE_EN_S 2\n+#define E830_GLPCI_PUSH_PQM_CTRL_PF_4K_RANGE_EN_M BIT(2)\n+#define E830_GLPCI_PUSH_PQM_CTRL_VF_LEGACY_RANGE_EN_S 3\n+#define E830_GLPCI_PUSH_PQM_CTRL_VF_LEGACY_RANGE_EN_M BIT(3)\n+#define E830_GLPCI_PUSH_PQM_CTRL_VF_TXTIME_RANGE_EN_S 4\n+#define E830_GLPCI_PUSH_PQM_CTRL_VF_TXTIME_RANGE_EN_M BIT(4)\n+#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_S 8\n+#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_M MAKEMASK(0xF, 8)\n+#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_DIS_S 12\n+#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_DIS_M BIT(12)\n+#define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_2DWS_ONE_CHUNK_EN_S 16\n+#define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_2DWS_ONE_CHUNK_EN_M BIT(16)\n+#define E830_GLPCI_PUSH_PQM_DBG\t\t\t0x0009DF7C /* Reset Source: PCIR */\n+#define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_S\t0\n+#define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_M\tMAKEMASK(0xFF, 0)\n+#define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_S\t8\n+#define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_M\tMAKEMASK(0xFF, 8)\n+#define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_S 16\n+#define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_M MAKEMASK(0xF, 16)\n+#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_S 20\n+#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_M MAKEMASK(0x1F, 20)\n+#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_PUSH_WHEN_FULL_ERR_S 25\n+#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_PUSH_WHEN_FULL_ERR_M BIT(25)\n+#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS\t0x0009DF78 /* Reset Source: PCIR */\n+#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_S 0\n+#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_M BIT(0)\n+#define E830_GLPCI_RDPU_CMD_DBG\t\t\t0x000BE264 /* Reset Source: PCIR */\n+#define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_S 0\n+#define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_M MAKEMASK(0xFF, 0)\n+#define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_S 8\n+#define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_M MAKEMASK(0xFF, 8)\n+#define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_S 16\n+#define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_M MAKEMASK(0xFF, 16)\n+#define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_S 24\n+#define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_M MAKEMASK(0xFF, 24)\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0\t\t0x000BE25C /* Reset Source: PCIR */\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_S 0\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0)\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_S 16\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16)\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1\t\t0x000BE260 /* Reset Source: PCIR */\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_S 0\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0)\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_S 16\n+#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16)\n+#define E830_GLPCI_RDPU_TAG\t\t\t0x000BE258 /* Reset Source: PCIR */\n+#define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_S\t0\n+#define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_M\tMAKEMASK(0xFF, 0)\n+#define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_S\t8\n+#define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_M\tMAKEMASK(0x3FF, 8)\n+#define E830_GLPCI_SB_AER_MSG_OUT\t\t0x0009DF80 /* Reset Source: PCIR */\n+#define E830_GLPCI_SB_AER_MSG_OUT_EN_S\t\t0\n+#define E830_GLPCI_SB_AER_MSG_OUT_EN_M\t\tBIT(0)\n+#define E830_GLPCI_SB_AER_MSG_OUT_ANF_SET_EN_S\t1\n+#define E830_GLPCI_SB_AER_MSG_OUT_ANF_SET_EN_M\tBIT(1)\n+#define E830_PF_FUNC_RID_HOST_S\t\t\t16\n+#define E830_PF_FUNC_RID_HOST_M\t\t\tMAKEMASK(0x3, 16)\n+#define E830_GLPES_PFRXNPECNMARKEDPKTSHI(_i)\t(0x00553004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_MAX_INDEX 127\n+#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_S 0\n+#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_M MAKEMASK(0xFFFFFF, 0)\n+#define E830_GLPES_PFRXNPECNMARKEDPKTSLO(_i)\t(0x00553000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_MAX_INDEX 127\n+#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_S 0\n+#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLPES_PFRXRPCNPHANDLED(_i)\t\t(0x00552C00 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define E830_GLPES_PFRXRPCNPHANDLED_MAX_INDEX\t127\n+#define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_S 0\n+#define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLPES_PFRXRPCNPIGNORED(_i)\t\t(0x00552800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define E830_GLPES_PFRXRPCNPIGNORED_MAX_INDEX\t127\n+#define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_S 0\n+#define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_M MAKEMASK(0xFFFFFF, 0)\n+#define E830_GLPES_PFTXNPCNPSENT(_i)\t\t(0x00553800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define E830_GLPES_PFTXNPCNPSENT_MAX_INDEX\t127\n+#define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_S\t0\n+#define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_M\tMAKEMASK(0xFFFFFF, 0)\n+#define E830_GLRPB_GBL_CFG\t\t\t0x000AD260 /* Reset Source: CORER */\n+#define E830_GLRPB_GBL_CFG_RESERVED_1_S\t\t0\n+#define E830_GLRPB_GBL_CFG_RESERVED_1_M\t\tMAKEMASK(0x3, 0)\n+#define E830_GLRPB_GBL_CFG_ALW_PE_RLS_S\t\t2\n+#define E830_GLRPB_GBL_CFG_ALW_PE_RLS_M\t\tBIT(2)\n+#define E830_GLRPB_GBL_CFG_LFSR_SHFT_S\t\t3\n+#define E830_GLRPB_GBL_CFG_LFSR_SHFT_M\t\tMAKEMASK(0x7, 3)\n+#define E830_GLQF_FLAT_HLUT(_i)\t\t\t(0x004C0000 + ((_i) * 4)) /* _i=0...8191 */ /* Reset Source: CORER */\n+#define E830_GLQF_FLAT_HLUT_MAX_INDEX\t\t8191\n+#define E830_GLQF_FLAT_HLUT_LUT0_S\t\t0\n+#define E830_GLQF_FLAT_HLUT_LUT0_M\t\tMAKEMASK(0xFF, 0)\n+#define E830_GLQF_FLAT_HLUT_LUT1_S\t\t8\n+#define E830_GLQF_FLAT_HLUT_LUT1_M\t\tMAKEMASK(0xFF, 8)\n+#define E830_GLQF_FLAT_HLUT_LUT2_S\t\t16\n+#define E830_GLQF_FLAT_HLUT_LUT2_M\t\tMAKEMASK(0xFF, 16)\n+#define E830_GLQF_FLAT_HLUT_LUT3_S\t\t24\n+#define E830_GLQF_FLAT_HLUT_LUT3_M\t\tMAKEMASK(0xFF, 24)\n+#define E830_GLQF_QGRP_CNTX(_i)\t\t\t(0x00490000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define E830_GLQF_QGRP_CNTX_MAX_INDEX\t\t2047\n+#define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_S\t0\n+#define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_M\tMAKEMASK(0x7FFF, 0)\n+#define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_S\t16\n+#define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_M\tMAKEMASK(0xF, 16)\n+#define E830_GLQF_QGRP_CNTX_VSI_S\t\t20\n+#define E830_GLQF_QGRP_CNTX_VSI_M\t\tMAKEMASK(0x3FF, 20)\n+#define E830_GLQF_QGRP_PF_OWNER(_i)\t\t(0x00484000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define E830_GLQF_QGRP_PF_OWNER_MAX_INDEX\t2047\n+#define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_S\t0\n+#define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_M\tMAKEMASK(0x7, 0)\n+#define E830_GLQF_QGRP_VSI_MODE\t\t\t0x0048E084 /* Reset Source: CORER */\n+#define E830_GLQF_QGRP_VSI_MODE_QGRP_MODE_S\t0\n+#define E830_GLQF_QGRP_VSI_MODE_QGRP_MODE_M\tBIT(0)\n+#define E830_GLQF_QTABLE_MODE\t\t\t0x0048E080 /* Reset Source: CORER */\n+#define E830_GLQF_QTABLE_MODE_SCT_MODE_S\t0\n+#define E830_GLQF_QTABLE_MODE_SCT_MODE_M\tBIT(0)\n+#define E830_GLQF_QTABLE_MODE_SCT_MODE_SET_S\t1\n+#define E830_GLQF_QTABLE_MODE_SCT_MODE_SET_M\tBIT(1)\n+#define E830_PFQF_LUT_ALLOC\t\t\t0x0048E000 /* Reset Source: CORER */\n+#define E830_PFQF_LUT_ALLOC_LUT_BASE_S\t\t0\n+#define E830_PFQF_LUT_ALLOC_LUT_BASE_M\t\tMAKEMASK(0x7FFF, 0)\n+#define E830_PFQF_LUT_ALLOC_LUT_SIZE_S\t\t16\n+#define E830_PFQF_LUT_ALLOC_LUT_SIZE_M\t\tMAKEMASK(0xF, 16)\n+#define E830_PFQF_QTABLE_ALLOC\t\t\t0x0048E040 /* Reset Source: CORER */\n+#define E830_PFQF_QTABLE_ALLOC_BASE_S\t\t0\n+#define E830_PFQF_QTABLE_ALLOC_BASE_M\t\tMAKEMASK(0x3FFF, 0)\n+#define E830_PFQF_QTABLE_ALLOC_SIZE_S\t\t16\n+#define E830_PFQF_QTABLE_ALLOC_SIZE_M\t\tMAKEMASK(0x1FFF, 16)\n+#define E830_VSILAN_FLAT_Q(_VSI)\t\t(0x00487000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define E830_VSILAN_FLAT_Q_MAX_INDEX\t\t767\n+#define E830_VSILAN_FLAT_Q_SCT_FLAT_BASE_S\t0\n+#define E830_VSILAN_FLAT_Q_SCT_FLAT_BASE_M\tMAKEMASK(0xFFF, 0)\n+#define E830_VSILAN_FLAT_Q_SCT_FLAT_SIZE_S\t16\n+#define E830_VSILAN_FLAT_Q_SCT_FLAT_SIZE_M\tMAKEMASK(0xFF, 16)\n+#define E830_VSIQF_DEF_QGRP(_VSI)\t\t(0x00486000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define E830_VSIQF_DEF_QGRP_MAX_INDEX\t\t767\n+#define E830_VSIQF_DEF_QGRP_DEF_QGRP_S\t\t0\n+#define E830_VSIQF_DEF_QGRP_DEF_QGRP_M\t\tMAKEMASK(0x7FF, 0)\n+#define E830_GLPRT_BPRCH_BPRCH_S\t\t0\n+#define E830_GLPRT_BPRCH_BPRCH_M\t\tMAKEMASK(0xFF, 0)\n+#define E830_GLPRT_BPRCL_BPRCL_S\t\t0\n+#define E830_GLPRT_BPRCL_BPRCL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLPRT_BPTCH_BPTCH_S\t\t0\n+#define E830_GLPRT_BPTCH_BPTCH_M\t\tMAKEMASK(0xFF, 0)\n+#define E830_GLPRT_BPTCL_BPTCL_S\t\t0\n+#define E830_GLPRT_BPTCL_BPTCL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLPRT_UPTCL_UPTCL_S\t\t0\n+#define E830_GLPRT_UPTCL_UPTCL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLRPB_PEAK_DOC_LOG(_i)\t\t(0x000AD178 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define E830_GLRPB_PEAK_DOC_LOG_MAX_INDEX\t15\n+#define E830_GLRPB_PEAK_DOC_LOG_PEAK_OC_S\t0\n+#define E830_GLRPB_PEAK_DOC_LOG_PEAK_OC_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLRPB_PEAK_SOC_LOG(_i)\t\t(0x000AD1B8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLRPB_PEAK_SOC_LOG_MAX_INDEX\t7\n+#define E830_GLRPB_PEAK_SOC_LOG_PEAK_OC_S\t0\n+#define E830_GLRPB_PEAK_SOC_LOG_PEAK_OC_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLPTM_ART_CTL\t\t\t0x00088B50 /* Reset Source: POR */\n+#define E830_GLPTM_ART_CTL_ACTIVE_S\t\t0\n+#define E830_GLPTM_ART_CTL_ACTIVE_M\t\tBIT(0)\n+#define E830_GLPTM_ART_CTL_TIME_OUT_S\t\t1\n+#define E830_GLPTM_ART_CTL_TIME_OUT_M\t\tBIT(1)\n+#define E830_GLPTM_ART_CTL_PTM_READY_S\t\t2\n+#define E830_GLPTM_ART_CTL_PTM_READY_M\t\tBIT(2)\n+#define E830_GLPTM_ART_CTL_PTM_AUTO_S\t\t3\n+#define E830_GLPTM_ART_CTL_PTM_AUTO_M\t\tBIT(3)\n+#define E830_GLPTM_ART_CTL_PTM_AUTO_LATCH_S\t4\n+#define E830_GLPTM_ART_CTL_PTM_AUTO_LATCH_M\tBIT(4)\n+#define E830_GLPTM_ART_TIME_H\t\t\t0x00088B54 /* Reset Source: POR */\n+#define E830_GLPTM_ART_TIME_H_ART_TIME_H_S\t0\n+#define E830_GLPTM_ART_TIME_H_ART_TIME_H_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLPTM_ART_TIME_L\t\t\t0x00088B58 /* Reset Source: POR */\n+#define E830_GLPTM_ART_TIME_L_ART_TIME_L_S\t0\n+#define E830_GLPTM_ART_TIME_L_ART_TIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_PTMTIME_H(_i)\t\t(0x00088B48 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define E830_GLTSYN_PTMTIME_H_MAX_INDEX\t\t1\n+#define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_S\t0\n+#define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_PTMTIME_L(_i)\t\t(0x00088B40 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define E830_GLTSYN_PTMTIME_L_MAX_INDEX\t\t1\n+#define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_S\t0\n+#define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_TIME_H_0_AL\t\t\t0x0008A004 /* Reset Source: CORER */\n+#define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_S\t0\n+#define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_TIME_H_1_AL\t\t\t0x0008B004 /* Reset Source: CORER */\n+#define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_S\t0\n+#define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_TIME_L_0_AL\t\t\t0x0008A000 /* Reset Source: CORER */\n+#define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_S\t0\n+#define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_TIME_L_1_AL\t\t\t0x0008B000 /* Reset Source: CORER */\n+#define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_S\t0\n+#define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_PFPTM_SEM\t\t\t\t0x00088B00 /* Reset Source: PFR */\n+#define E830_PFPTM_SEM_BUSY_S\t\t\t0\n+#define E830_PFPTM_SEM_BUSY_M\t\t\tBIT(0)\n+#define E830_PFPTM_SEM_PF_OWNER_S\t\t4\n+#define E830_PFPTM_SEM_PF_OWNER_M\t\tMAKEMASK(0x7, 4)\n+#define E830_VSI_PASID_1(_VSI)\t\t\t(0x00094000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define E830_VSI_PASID_1_MAX_INDEX\t\t767\n+#define E830_VSI_PASID_1_PASID_S\t\t0\n+#define E830_VSI_PASID_1_PASID_M\t\tMAKEMASK(0xFFFFF, 0)\n+#define E830_VSI_PASID_1_EN_S\t\t\t31\n+#define E830_VSI_PASID_1_EN_M\t\t\tBIT(31)\n+#define E830_VSI_PASID_2(_VSI)\t\t\t(0x00095000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define E830_VSI_PASID_2_MAX_INDEX\t\t767\n+#define E830_VSI_PASID_2_PASID_S\t\t0\n+#define E830_VSI_PASID_2_PASID_M\t\tMAKEMASK(0xFFFFF, 0)\n+#define E830_VSI_PASID_2_EN_S\t\t\t31\n+#define E830_VSI_PASID_2_EN_M\t\t\tBIT(31)\n+#define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_S\t15\n+#define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_M\tMAKEMASK(0x3F, 15)\n+#define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_S 29\n+#define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_M MAKEMASK(0x3, 29)\n+#define E830_VFPE_MRTEIDXMASK_MAX_INDEX\t\t255\n+#define E830_GLSWR_PMCFG_RPB_REP_DHW(_i)\t(0x0020A7A0 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_DHW_MAX_INDEX\t15\n+#define E830_GLSWR_PMCFG_RPB_REP_DHW_DHW_TCN_S\t0\n+#define E830_GLSWR_PMCFG_RPB_REP_DHW_DHW_TCN_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLSWR_PMCFG_RPB_REP_DLW(_i)\t(0x0020A7E0 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_DLW_MAX_INDEX\t15\n+#define E830_GLSWR_PMCFG_RPB_REP_DLW_DLW_TCN_S\t0\n+#define E830_GLSWR_PMCFG_RPB_REP_DLW_DLW_TCN_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLSWR_PMCFG_RPB_REP_DPS(_i)\t(0x0020A760 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_DPS_MAX_INDEX\t15\n+#define E830_GLSWR_PMCFG_RPB_REP_DPS_DPS_TCN_S\t0\n+#define E830_GLSWR_PMCFG_RPB_REP_DPS_DPS_TCN_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLSWR_PMCFG_RPB_REP_SHW(_i)\t(0x0020A720 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_SHW_MAX_INDEX\t7\n+#define E830_GLSWR_PMCFG_RPB_REP_SHW_SHW_S\t0\n+#define E830_GLSWR_PMCFG_RPB_REP_SHW_SHW_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLSWR_PMCFG_RPB_REP_SLW(_i)\t(0x0020A740 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_SLW_MAX_INDEX\t7\n+#define E830_GLSWR_PMCFG_RPB_REP_SLW_SLW_S\t0\n+#define E830_GLSWR_PMCFG_RPB_REP_SLW_SLW_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLSWR_PMCFG_RPB_REP_SPS(_i)\t(0x0020A700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_SPS_MAX_INDEX\t7\n+#define E830_GLSWR_PMCFG_RPB_REP_SPS_SPS_TCN_S\t0\n+#define E830_GLSWR_PMCFG_RPB_REP_SPS_SPS_TCN_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG(_i)\t(0x0020A980 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_MAX_INDEX 31\n+#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_D_POOL_S 0\n+#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_D_POOL_M MAKEMASK(0xFFFF, 0)\n+#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_S_POOL_S 16\n+#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_S_POOL_M MAKEMASK(0xFFFF, 16)\n+#define E830_GLSWR_PMCFG_RPB_REP_TCHW(_i)\t(0x0020A880 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_TCHW_MAX_INDEX\t31\n+#define E830_GLSWR_PMCFG_RPB_REP_TCHW_TCHW_S\t0\n+#define E830_GLSWR_PMCFG_RPB_REP_TCHW_TCHW_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLSWR_PMCFG_RPB_REP_TCLW(_i)\t(0x0020A900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define E830_GLSWR_PMCFG_RPB_REP_TCLW_MAX_INDEX\t31\n+#define E830_GLSWR_PMCFG_RPB_REP_TCLW_TCLW_S\t0\n+#define E830_GLSWR_PMCFG_RPB_REP_TCLW_TCLW_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLQF_QGRP_CFG(_VSI)\t\t(0x00492000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define E830_GLQF_QGRP_CFG_MAX_INDEX\t\t767\n+#define E830_GLQF_QGRP_CFG_VSI_QGRP_ENABLE_S\t0\n+#define E830_GLQF_QGRP_CFG_VSI_QGRP_ENABLE_M\tBIT(0)\n+#define E830_GLQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_S\t1\n+#define E830_GLQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_M\tMAKEMASK(0x7, 1)\n+#define E830_GLDCB_RTCTI_PD\t\t\t0x00122740 /* Reset Source: CORER */\n+#define E830_GLDCB_RTCTI_PD_PFCTIMEOUT_TC_S\t0\n+#define E830_GLDCB_RTCTI_PD_PFCTIMEOUT_TC_M\tMAKEMASK(0xFF, 0)\n+#define E830_GLDCB_RTCTQ_PD(_i)\t\t\t(0x00122700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLDCB_RTCTQ_PD_MAX_INDEX\t\t7\n+#define E830_GLDCB_RTCTQ_PD_RXQNUM_S\t\t0\n+#define E830_GLDCB_RTCTQ_PD_RXQNUM_M\t\tMAKEMASK(0x7FF, 0)\n+#define E830_GLDCB_RTCTQ_PD_IS_PF_Q_S\t\t16\n+#define E830_GLDCB_RTCTQ_PD_IS_PF_Q_M\t\tBIT(16)\n+#define E830_GLDCB_RTCTS_PD(_i)\t\t\t(0x00122720 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define E830_GLDCB_RTCTS_PD_MAX_INDEX\t\t7\n+#define E830_GLDCB_RTCTS_PD_PFCTIMER_S\t\t0\n+#define E830_GLDCB_RTCTS_PD_PFCTIMER_M\t\tMAKEMASK(0x3FFF, 0)\n+#define E830_GLRPB_PEAK_TC_OC_LOG(_i)\t\t(0x000AD1D8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define E830_GLRPB_PEAK_TC_OC_LOG_MAX_INDEX\t31\n+#define E830_GLRPB_PEAK_TC_OC_LOG_PEAK_OC_S\t0\n+#define E830_GLRPB_PEAK_TC_OC_LOG_PEAK_OC_M\tMAKEMASK(0x3FFFFF, 0)\n+#define E830_GLRPB_TC_TOTAL_PC(_i)\t\t(0x000ACFE0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define E830_GLRPB_TC_TOTAL_PC_MAX_INDEX\t31\n+#define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_S\t0\n+#define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_VFINT_ITRN_64(_i, _j)\t\t(0x00002C00 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...2 */ /* Reset Source: CORER */\n+#define E830_VFINT_ITRN_64_MAX_INDEX\t\t63\n+#define E830_VFINT_ITRN_64_INTERVAL_S\t\t0\n+#define E830_VFINT_ITRN_64_INTERVAL_M\t\tMAKEMASK(0xFFF, 0)\n+#define E830_GLQTX_TXTIME_DBELL_LSB1(_DBQM)\t(0x0000D000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_GLQTX_TXTIME_DBELL_LSB1_MAX_INDEX\t255\n+#define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_S 0\n+#define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLQTX_TXTIME_DBELL_MSB1(_DBQM)\t(0x0000D004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_GLQTX_TXTIME_DBELL_MSB1_MAX_INDEX\t255\n+#define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_S 0\n+#define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB(_DBQM) (0x00040000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_MAX_INDEX 255\n+#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_S 0\n+#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB(_DBQM) (0x00040004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_MAX_INDEX 255\n+#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_S 0\n+#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_TIME_H_0_AL1\t\t0x00003004 /* Reset Source: CORER */\n+#define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_S\t0\n+#define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_TIME_H_1_AL1\t\t0x0000300C /* Reset Source: CORER */\n+#define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_S\t0\n+#define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_TIME_L_0_AL1\t\t0x00003000 /* Reset Source: CORER */\n+#define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_S\t0\n+#define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_GLTSYN_TIME_L_1_AL1\t\t0x00003008 /* Reset Source: CORER */\n+#define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_S\t0\n+#define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define E830_VSI_VSI2F_LEM(_VSI)\t\t(0x006100A0 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define E830_VSI_VSI2F_LEM_MAX_INDEX\t\t767\n+#define E830_VSI_VSI2F_LEM_VFVMNUMBER_S\t\t0\n+#define E830_VSI_VSI2F_LEM_VFVMNUMBER_M\t\tMAKEMASK(0x3FF, 0)\n+#define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_S\t10\n+#define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_M\tMAKEMASK(0x3, 10)\n+#define E830_VSI_VSI2F_LEM_PFNUMBER_S\t\t12\n+#define E830_VSI_VSI2F_LEM_PFNUMBER_M\t\tMAKEMASK(0x7, 12)\n+#define E830_VSI_VSI2F_LEM_BUFFERNUMBER_S\t16\n+#define E830_VSI_VSI2F_LEM_BUFFERNUMBER_M\tMAKEMASK(0x7, 16)\n+#define E830_VSI_VSI2F_LEM_VSI_NUMBER_S\t\t20\n+#define E830_VSI_VSI2F_LEM_VSI_NUMBER_M\t\tMAKEMASK(0x3FF, 20)\n+#define E830_VSI_VSI2F_LEM_VSI_ENABLE_S\t\t31\n+#define E830_VSI_VSI2F_LEM_VSI_ENABLE_M\t\tBIT(31)\n #endif /* !_ICE_HW_AUTOGEN_H_ */\n \ndiff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nindex 229db1041c..d8ac841e46 100644\n--- a/drivers/net/ice/base/ice_lan_tx_rx.h\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -2469,5 +2469,5 @@ static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)\n #define ICE_LINK_SPEED_40000MBPS\t40000\n #define ICE_LINK_SPEED_50000MBPS\t50000\n #define ICE_LINK_SPEED_100000MBPS\t100000\n-\n+#define ICE_LINK_SPEED_200000MBPS\t200000\n #endif /* _ICE_LAN_TX_RX_H_ */\ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex cb45cb8134..6ab359af33 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -1330,14 +1330,17 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,\n \t\treturn status;\n \n \t/* Reject requests to write to read-only registers */\n-\tswitch (cmd->offset) {\n-\tcase GL_HICR_EN:\n-\tcase GLGEN_RSTAT:\n-\t\treturn ICE_ERR_OUT_OF_RANGE;\n-\tdefault:\n-\t\tbreak;\n+\tif (hw->mac_type == ICE_MAC_E830) {\n+\t\tif (cmd->offset == E830_GL_HICR_EN)\n+\t\t\treturn ICE_ERR_OUT_OF_RANGE;\n+\t} else {\n+\t\tif (cmd->offset == GL_HICR_EN)\n+\t\t\treturn ICE_ERR_OUT_OF_RANGE;\n \t}\n \n+\tif (cmd->offset == GLGEN_RSTAT)\n+\t\treturn ICE_ERR_OUT_OF_RANGE;\n+\n \tice_debug(hw, ICE_DBG_NVM, \"NVM access: writing register %08x with value %08x\\n\",\n \t\t  cmd->offset, data->regval);\n \ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 5779590a7e..576998549e 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -222,6 +222,7 @@ enum ice_set_fc_aq_failures {\n enum ice_mac_type {\n \tICE_MAC_UNKNOWN = 0,\n \tICE_MAC_E810,\n+\tICE_MAC_E830,\n \tICE_MAC_GENERIC,\n \tICE_MAC_GENERIC_3K,\n };\n",
    "prefixes": [
        "12/30"
    ]
}