Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/126580/?format=api
{ "id": 126580, "url": "http://patchwork.dpdk.org/api/patches/126580/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230427062001.478032-14-qiming.yang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-14-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-14-qiming.yang@intel.com", "date": "2023-04-27T06:19:44", "name": "[13/30] net/ice/base: add function to get rxq context", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b55675768b8663b5bda275819cba2ef8fa0beab8", "submitter": { "id": 522, "url": "http://patchwork.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230427062001.478032-14-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "http://patchwork.dpdk.org/api/series/27885/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27885/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126580/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/126580/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 02F6C42A08;\n\tThu, 27 Apr 2023 08:39:29 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C8F3642DA4;\n\tThu, 27 Apr 2023 08:38:12 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 7680B42D98\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:38:09 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:38:09 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:06 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577489; x=1714113489;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=xIYxF+vEvuia9tIbokR3uhZYxRXBrKoe5ugLWwPwXgo=;\n b=AcaVI+rpqOV1ZzqVR/BE/3fjSpAH7P/j0mrGVdh7fvhgLNxVNCvNc7fH\n NRyFAevEMXOdb6z2vDzyfNsJtJrBccPEjXite1OkddTxkP01qoqRIGxJv\n Sq6KBprljL7lkCc1QQ4tQz4mj7cuJtrWo0IWYlTY76jgy5KWYaZNnbBQb\n oNsszkZbCu0l6CUfFy8E1zUX/nUEB/4kcs3Yln+gx9bYUqwei7LxVC+Nm\n oZuBarXTsL7gae9qpvKe1cJNO5Y75hbHoktj6Kdh8hW/Cuu/+vgKbIR21\n lvjwWXQBTB+kNG1D69uiTFX9p3zyUN+bjyvEG7tCM60Kdw7l6HQhp6Bzq w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324320\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324320\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845785\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845785\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Yahui Cao <yahui.cao@intel.com>", "Subject": "[PATCH 13/30] net/ice/base: add function to get rxq context", "Date": "Thu, 27 Apr 2023 06:19:44 +0000", "Message-Id": "<20230427062001.478032-14-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch exports rxq context which is consumed by linux linve\nmigration driver to save device state.\n\nSigned-off-by: Yahui Cao <yahui.cao@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 75 +++++++++++++++++++++++++++----\n drivers/net/ice/base/ice_common.h | 7 ++-\n 2 files changed, 71 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 58da198d62..ed822afc30 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -1397,6 +1397,37 @@ ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_copy_rxq_ctx_from_hw - Copy rxq context register from HW\n+ * @hw: pointer to the hardware structure\n+ * @ice_rxq_ctx: pointer to the rxq context\n+ * @rxq_index: the index of the Rx queue\n+ *\n+ * Copies rxq context from HW register space to dense structure\n+ */\n+static enum ice_status\n+ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)\n+{\n+\tu8 i;\n+\n+\tif (!ice_rxq_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tif (rxq_index > QRX_CTRL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Copy each dword separately from HW */\n+\tfor (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {\n+\t\tu32 *ctx = (u32 *)(ice_rxq_ctx + (i * sizeof(u32)));\n+\n+\t\t*ctx = rd32(hw, QRX_CONTEXT(i, rxq_index));\n+\n+\t\tice_debug(hw, ICE_DBG_QCTX, \"qrxdata[%d]: %08X\\n\", i, *ctx);\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n /* LAN Rx Queue Context */\n static const struct ice_ctx_ele ice_rlan_ctx_info[] = {\n \t/* Field\t\tWidth\tLSB */\n@@ -1448,6 +1479,32 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n \treturn ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);\n }\n \n+/**\n+ * ice_read_rxq_ctx - Read rxq context from HW\n+ * @hw: pointer to the hardware structure\n+ * @rlan_ctx: pointer to the rxq context\n+ * @rxq_index: the index of the Rx queue\n+ *\n+ * Read rxq context from HW register space and then converts it from dense\n+ * structure to sparse\n+ */\n+enum ice_status\n+ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n+\t\t u32 rxq_index)\n+{\n+\tu8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };\n+\tenum ice_status status;\n+\n+\tif (!rlan_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tstatus = ice_copy_rxq_ctx_from_hw(hw, ctx_buf, rxq_index);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ice_get_ctx(ctx_buf, (u8 *)rlan_ctx, ice_rlan_ctx_info);\n+}\n+\n /**\n * ice_clear_rxq_ctx\n * @hw: pointer to the hardware structure\n@@ -4883,7 +4940,7 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,\n * @ce_info: a description of the struct to be filled\n */\n static void\n-ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+ice_read_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n {\n \tu8 dest_byte, mask;\n \tu8 *src, *target;\n@@ -4901,7 +4958,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n \n \tice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);\n \n-\tdest_byte &= ~(mask);\n+\tdest_byte &= mask;\n \n \tdest_byte >>= shift_width;\n \n@@ -4919,7 +4976,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n * @ce_info: a description of the struct to be filled\n */\n static void\n-ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+ice_read_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n {\n \tu16 dest_word, mask;\n \tu8 *src, *target;\n@@ -4941,7 +4998,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n \t/* the data in the memory is stored as little endian so mask it\n \t * correctly\n \t */\n-\tsrc_word &= ~(CPU_TO_LE16(mask));\n+\tsrc_word &= CPU_TO_LE16(mask);\n \n \t/* get the data back into host order before shifting */\n \tdest_word = LE16_TO_CPU(src_word);\n@@ -4962,7 +5019,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n * @ce_info: a description of the struct to be filled\n */\n static void\n-ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+ice_read_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n {\n \tu32 dest_dword, mask;\n \t__le32 src_dword;\n@@ -4992,7 +5049,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n \t/* the data in the memory is stored as little endian so mask it\n \t * correctly\n \t */\n-\tsrc_dword &= ~(CPU_TO_LE32(mask));\n+\tsrc_dword &= CPU_TO_LE32(mask);\n \n \t/* get the data back into host order before shifting */\n \tdest_dword = LE32_TO_CPU(src_dword);\n@@ -5013,7 +5070,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n * @ce_info: a description of the struct to be filled\n */\n static void\n-ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+ice_read_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n {\n \tu64 dest_qword, mask;\n \t__le64 src_qword;\n@@ -5043,7 +5100,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n \t/* the data in the memory is stored as little endian so mask it\n \t * correctly\n \t */\n-\tsrc_qword &= ~(CPU_TO_LE64(mask));\n+\tsrc_qword &= CPU_TO_LE64(mask);\n \n \t/* get the data back into host order before shifting */\n \tdest_qword = LE64_TO_CPU(src_qword);\n@@ -5064,7 +5121,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n * @ce_info: a description of the structure to be read from\n */\n enum ice_status\n-ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n {\n \tint f;\n \ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex d8fb7a6163..3e03f2e903 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -92,6 +92,9 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,\n enum ice_status\n ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n \t\t u32 rxq_index);\n+enum ice_status\n+ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n+\t\t u32 rxq_index);\n enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);\n enum ice_status\n ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);\n@@ -135,6 +138,8 @@ extern const struct ice_ctx_ele ice_tlan_ctx_info[];\n enum ice_status\n ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,\n \t const struct ice_ctx_ele *ce_info);\n+enum ice_status\n+ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);\n \n enum ice_status\n ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,\n@@ -229,8 +234,6 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw,\n \t\t\t u32 start_address, u8 *buf, u8 buf_size,\n \t\t\t struct ice_sq_cd *cd);\n \n-enum ice_status\n-ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);\n enum ice_status\n ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,\n \t\tu16 *q_handle, u16 *q_ids, u32 *q_teids,\n", "prefixes": [ "13/30" ] }