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GET /api/patches/126582/?format=api
{ "id": 126582, "url": "http://patchwork.dpdk.org/api/patches/126582/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230427062001.478032-16-qiming.yang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-16-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-16-qiming.yang@intel.com", "date": "2023-04-27T06:19:46", "name": "[15/30] net/ice/base: allow skip main timer", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ced51671d4cc19ac57057d5917a8c8c442f2892b", "submitter": { "id": 522, "url": "http://patchwork.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230427062001.478032-16-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "http://patchwork.dpdk.org/api/series/27885/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27885/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126582/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/126582/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 13A7E42A08;\n\tThu, 27 Apr 2023 08:39:41 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6E99F42DC8;\n\tThu, 27 Apr 2023 08:38:16 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id D513742DC2\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:38:12 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:38:12 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:10 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577493; x=1714113493;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=/BPk+Lf+JfMhOjxzFjkeMwfvVGWOSWScj8KPyUtYkiU=;\n b=MJnWc08BE1SYoh3K9TyHLJaQikqJVlCt370NWhGKxwwTjtdimGS54Zj8\n F0VzaVYEDQ0yW6NDEDCedn0D5MhU5c7T2wUNjb81y/EiDGCQeiYBjXIfh\n P2BM3i6xuGf3zH+7sEnSqniKeJGhRvEmy0R/G5P9XKIWSIEBvvhpTQWZW\n Ivsiallp8aQ0peQU/cOqgMBCfoi2lHp5ROutVXpJQrUQQvN7n8/kOXOc/\n tiBoqTGwW3EVJW4WwHQX0wRbakHvdENQM0iNARcBRTTd2jD818oSAAjKY\n 2gFrR52J0BCbZfnh/i+TpWAscVc5eCcdxOHiOhzI05G7uxjSMgEE3IZI/ w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324340\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324340\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845808\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845808\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Sergey Temerkhanov <sergey.temerkhanov@intel.com>", "Subject": "[PATCH 15/30] net/ice/base: allow skip main timer", "Date": "Thu, 27 Apr 2023 06:19:46 +0000", "Message-Id": "<20230427062001.478032-16-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Allow initialization functions to skip main timer programming.\n\nSigned-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 32 ++++++++++++++++++++-----------\n drivers/net/ice/base/ice_ptp_hw.h | 9 ++++++---\n drivers/net/ice/ice_ethdev.c | 2 +-\n 3 files changed, 28 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 61145262ac..43b7e313f4 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -3550,6 +3550,7 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)\n * ice_ptp_init_time - Initialize device time to provided value\n * @hw: pointer to HW struct\n * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)\n+ * @wr_main_tmr: program the main timer\n *\n * Initialize the device to the specified time provided. This requires a three\n * step process:\n@@ -3559,7 +3560,8 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)\n * 3) issue an init_time timer command to synchronously switch both the source\n * and port timers to the new init time value at the next clock cycle.\n */\n-enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)\n+enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time,\n+\t\t\t\t bool wr_main_tmr)\n {\n \tenum ice_status status;\n \tu8 tmr_idx;\n@@ -3567,9 +3569,11 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)\n \ttmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;\n \n \t/* Source timers */\n-\twr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time));\n-\twr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time));\n-\twr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);\n+\tif (wr_main_tmr) {\n+\t\twr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time));\n+\t\twr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time));\n+\t\twr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);\n+\t}\n \n \t/* PHY Clks */\n \t/* Fill Rx and Tx ports and send msg to PHY */\n@@ -3594,8 +3598,9 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)\n * ice_ptp_write_incval - Program PHC with new increment value\n * @hw: pointer to HW struct\n * @incval: Source timer increment value per clock cycle\n+ * @wr_main_tmr: Program the main timer\n *\n- * Program the PHC with a new increment value. This requires a three-step\n+ * Program the timers with a new increment value. This requires a three-step\n * process:\n *\n * 1) Write the increment value to the source timer shadow registers\n@@ -3604,16 +3609,19 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)\n * the source and port timers to the new increment value at the next clock\n * cycle.\n */\n-enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)\n+enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval,\n+\t\t\t\t bool wr_main_tmr)\n {\n \tenum ice_status status;\n \tu8 tmr_idx;\n \n \ttmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;\n \n-\t/* Shadow Adjust */\n-\twr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval));\n-\twr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));\n+\tif (wr_main_tmr) {\n+\t\t/* Shadow Adjust */\n+\t\twr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval));\n+\t\twr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));\n+\t}\n \n \tswitch (hw->phy_cfg) {\n \tcase ICE_PHY_E810:\n@@ -3636,17 +3644,19 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)\n * ice_ptp_write_incval_locked - Program new incval while holding semaphore\n * @hw: pointer to HW struct\n * @incval: Source timer increment value per clock cycle\n+ * @wr_main_tmr: Program the main timer\n *\n * Program a new PHC incval while holding the PTP semaphore.\n */\n-enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)\n+enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval,\n+\t\t\t\t\t bool wr_main_tmr)\n {\n \tenum ice_status status;\n \n \tif (!ice_ptp_lock(hw))\n \t\treturn ICE_ERR_NOT_READY;\n \n-\tstatus = ice_ptp_write_incval(hw, incval);\n+\tstatus = ice_ptp_write_incval(hw, incval, wr_main_tmr);\n \n \tice_ptp_unlock(hw);\n \ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex d2581e63f9..48a30f1f4e 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -131,9 +131,12 @@ u64 ice_ptp_read_src_incval(struct ice_hw *hw);\n bool ice_ptp_lock(struct ice_hw *hw);\n void ice_ptp_unlock(struct ice_hw *hw);\n void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);\n-enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time);\n-enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval);\n-enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);\n+enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time,\n+\t\t\t\t bool wr_main_tmr);\n+enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval,\n+\t\t\t\t bool wr_main_tmr);\n+enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval,\n+\t\t\t\t\t bool wr_main_tmr);\n enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq);\n enum ice_status\n ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj);\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 9a88cf9796..6700893bc5 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -5832,7 +5832,7 @@ ice_timesync_enable(struct rte_eth_dev *dev)\n \t\t\treturn -1;\n \t\t}\n \n-\t\tret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810);\n+\t\tret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810, 1);\n \t\tif (ret) {\n \t\t\tPMD_DRV_LOG(ERR,\n \t\t\t\t\"Failed to write PHC increment time value\");\n", "prefixes": [ "15/30" ] }