Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/126664/?format=api
{ "id": 126664, "url": "http://patchwork.dpdk.org/api/patches/126664/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230502184922.3249201-1-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230502184922.3249201-1-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230502184922.3249201-1-akozyrev@nvidia.com", "date": "2023-05-02T18:49:22", "name": "drivers: fix error CQE handling", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c08cf4d60af37a59b9801cdcdb578b2b887d32a6", "submitter": { "id": 1873, "url": "http://patchwork.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230502184922.3249201-1-akozyrev@nvidia.com/mbox/", "series": [ { "id": 27913, "url": "http://patchwork.dpdk.org/api/series/27913/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27913", "date": "2023-05-02T18:49:22", "name": "drivers: fix error CQE handling", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27913/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126664/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/126664/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E02CE42A3E;\n\tTue, 2 May 2023 20:49:54 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 75E8840EE7;\n\tTue, 2 May 2023 20:49:54 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2040.outbound.protection.outlook.com [40.107.223.40])\n by mails.dpdk.org (Postfix) with ESMTP id CAD1840ED8;\n Tue, 2 May 2023 20:49:52 +0200 (CEST)", "from DS7PR03CA0054.namprd03.prod.outlook.com (2603:10b6:5:3b5::29)\n by CH3PR12MB8282.namprd12.prod.outlook.com (2603:10b6:610:124::13) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.31; Tue, 2 May\n 2023 18:49:51 +0000", "from DM6NAM11FT023.eop-nam11.prod.protection.outlook.com\n (2603:10b6:5:3b5:cafe::ed) by DS7PR03CA0054.outlook.office365.com\n (2603:10b6:5:3b5::29) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.31 via Frontend\n Transport; Tue, 2 May 2023 18:49:51 +0000", "from mail.nvidia.com (216.228.117.161) by\n DM6NAM11FT023.mail.protection.outlook.com (10.13.173.96) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6363.20 via Frontend Transport; Tue, 2 May 2023 18:49:51 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 2 May 2023\n 11:49:38 -0700", "from pegasus01.mtr.labs.mlnx (10.126.231.37) by\n rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.986.37; Tue, 2 May 2023 11:49:36 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=Ei7NuS47vFxvV2WfuKCIWDx1mLOGV3QATv04H2yW9+tfCgHc3Ph68aAXzx+kr1ouf9H8n4ScTjPZG49CTcb7JTG+musCxnKIVCcDizhQ6mC+b9+55EwUgdeiI67TOG+PxEDdZWvRwLn6dfeyFo5sQCdbJw8AB0oKua1F/a0b7XJQuIiWMY2t8CBqkdvArHpiM6WA99dyNNYDpk4omfg9i7tEEcvxaFXlyyQj+sz9Y9J93K6R+hPR13WKHBCZP/HtsCJKLrz56qpQ9sDEm2rBFqYjO5Vw1W4H8zT30xV2leIuo/UdobrQUslu5epWoVAgG391/typrcVlVDrhKzVHGg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=egpfYqKyUd7PSByqObNyfBNKbTWZJi+HV4maul7z93Q=;\n b=ZUdqKYth+Ugp9/Y4TvSucySUf4DL8Uy0bOmN7oDDCbU4AwCE8OTXiIKIba0vEhQHPOC1P+feIQ5e7Bp6ESZsgYcYnSlR7Y4UMypvQLBSAaAbx9Q7eaMeqqxuNsa9e/JeASLdfyfKcfAqOMft9j3hOOEeUj+6AdfD+FEw+VJMv7/oz9uwlfe4iP7MpQeg1AKcE3Cw8IN1BHS29uHvjeRG29cyQt0qpw+POYP/13McI00sCHgP6fnas6N6QJhyy0vDirml+Sa5HxlI6Mu6hQXOTmG1WQEomTYTeFvDDavQXXothQ4AZXSr1obDdIKize/dd1L2kiBzbFXkEO4tKZWs9w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=egpfYqKyUd7PSByqObNyfBNKbTWZJi+HV4maul7z93Q=;\n b=WVmZNwkhicDZqxh+OVR4Z59SlxmtLmkQTI3G4/IJMKPntPmjUebgIAAU35EPSdWervT7jeRsA6Pwk5yK0//GJ3Z18vTId8ACCAN+HS8i7rPSccXlSrk2Qmxc10tArUF47R2NMw4zpEOYpvHFBevETv0E3fU8Lx+vk0MOkJlSW+DhFuFb8Ww/UbnqwIoCMbrPhHLIKtGzkjnkF6PWkRdwTjDYykxVCoMB9UylyvJUxB2p5Lfy0NH4QaieMiPprH+nevPIdN+Q+OIYfs91unhhuu8JQKt9+M1jhJrZ1+u+EA4K33gnRL41DfTW1ytBO2Oq0vaDgl2OOhB/LrCMwfofTA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<stable@dpdk.org>, <rasland@nvidia.com>, <viacheslavo@nvidia.com>,\n <matan@nvidia.com>", "Subject": "[PATCH] drivers: fix error CQE handling", "Date": "Tue, 2 May 2023 21:49:22 +0300", "Message-ID": "<20230502184922.3249201-1-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT023:EE_|CH3PR12MB8282:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6ba1f16d-ff67-4296-5589-08db4b3e02e8", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 6eq0zkTyaR6Zjixm4K/Q6n3xnOaflQj+aPWmB8kPD3B1/a0H8mYbCdar4m9j4chb09X6PEECw6yfQCuZy+3s1sq4wXvmYXIoify+/6EENpWTXMU5T8A2PkEzPcotGQOmNswXrb0KHr5rFLt2oDI6Pzs5QJmJdAssy8grbUZasrNDoh2C/jOF676iyzA3Js9ba2KoIZNKoUoBmQ2EaIMaaXTEwwVLQIT95oZwOyIWBE4sAJQb5R75Reqx4QfOI6SAc6Y2mgZoIy1avHmpRTjAP1KXZQrE6rF3mR4q3PLgiABUCf5zaHuEG7wAqyFEQffwSnwKCtHmdtg91+BXavlkuk2+oA25KjnWHUEJXG8lt6gk/RIbSzRkOtsBvoqCkaE9W2YKfKlKPNEWfTlMl7YHOJ+ExVnapMdumpuXzBGOeygdFG7nsh3PR8Kwp8ddYnk19uQ4rw5YglvkmqoHWhlSItEO7522DortI7O2Pfyz8yWBpedRFRAcI4dfn/r/7la0SxPnYVTzpyR9dZ5j7yxXapGtIQA50DQg8ihw2tn8Ld3nRfYKAYChMg8U/m+YGSApDPCdS/SDtZTrjyps+CuM9vE6k6YPBkxa1geSmGLp2QClmzP9C9b3aPI5gobscU7ZxGcdveZUshZSqkop6Pn3jlqlNnF8udw1OezsCa5yH0uXzGGznKvyuSablIFmoF1mxv8dz5I5ftFA85kbcN+j6A==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(39860400002)(136003)(376002)(396003)(346002)(451199021)(40470700004)(46966006)(36840700001)(8936002)(8676002)(478600001)(316002)(86362001)(36756003)(6666004)(4326008)(82310400005)(6916009)(41300700001)(40480700001)(70586007)(70206006)(356005)(450100002)(7636003)(5660300002)(40460700003)(82740400003)(426003)(83380400001)(107886003)(336012)(2616005)(54906003)(47076005)(26005)(186003)(16526019)(1076003)(2906002)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 May 2023 18:49:51.0330 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6ba1f16d-ff67-4296-5589-08db4b3e02e8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT023.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8282", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The completion queue element size can be independently configured\nto report either 64 or 128 bytes CQEs by programming cqe_sz parameter\nat CQ creation. This parameter depends on the cache line size and\naffects both regular CQEs and error CQEs. But the error handling\nassumes that an error CQE is 64 bytes and doesn't take the padding\ninto consideration on platforms with 128-byte cache lines.\nFix the error CQE size in all error handling routines in mlx5.\n\nFixes: 957e45fb7b (\"net/mlx5: handle Tx completion with error\")\nCc: stable@dpdk.org\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 29 ++++++++++++++++++++-\n drivers/common/mlx5/windows/mlx5_win_defs.h | 12 ---------\n drivers/compress/mlx5/mlx5_compress.c | 4 +--\n drivers/crypto/mlx5/mlx5_crypto.c | 2 +-\n drivers/net/mlx5/mlx5_flow_aso.c | 6 ++---\n drivers/net/mlx5/mlx5_rx.c | 2 +-\n drivers/net/mlx5/mlx5_tx.c | 8 +++---\n 7 files changed, 39 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex ed3d5efbb7..505ff3cc8e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -268,8 +268,12 @@\n /* Maximum number of DS in WQE. Limited by 6-bit field. */\n #define MLX5_DSEG_MAX 63\n \n-/* The 32 bit syndrome offset in struct mlx5_err_cqe. */\n+/* The 32 bit syndrome offset in struct mlx5_error_cqe. */\n+#if (RTE_CACHE_LINE_SIZE == 128)\n+#define MLX5_ERROR_CQE_SYNDROME_OFFSET 116\n+#else\n #define MLX5_ERROR_CQE_SYNDROME_OFFSET 52\n+#endif\n \n /* The completion mode offset in the WQE control segment line 2. */\n #define MLX5_COMP_MODE_OFFSET 2\n@@ -415,6 +419,29 @@ struct mlx5_wqe_mprq {\n \n #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2\n \n+struct mlx5_error_cqe {\n+#if (RTE_CACHE_LINE_SIZE == 128)\n+\tuint8_t padding[64];\n+#endif\n+\tuint8_t rsvd0[2];\n+\tuint16_t eth_wqe_id;\n+\tuint8_t\trsvd1[16];\n+\tuint16_t ib_stride_index;\n+\tuint8_t\trsvd2[10];\n+\tuint32_t srqn;\n+\tuint8_t\trsvd3[8];\n+\tuint32_t byte_cnt;\n+\tuint8_t\trsvd4[4];\n+\tuint8_t\thw_err_synd;\n+\tuint8_t\thw_synd_type;\n+\tuint8_t\tvendor_err_synd;\n+\tuint8_t\tsyndrome;\n+\tuint32_t s_wqe_opcode_qpn;\n+\tuint16_t wqe_counter;\n+\tuint8_t\tsignature;\n+\tuint8_t\top_own;\n+};\n+\n /* CQ element structure - should be equal to the cache line size */\n struct mlx5_cqe {\n #if (RTE_CACHE_LINE_SIZE == 128)\ndiff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h\nindex 65da820c5e..1ddf5c553d 100644\n--- a/drivers/common/mlx5/windows/mlx5_win_defs.h\n+++ b/drivers/common/mlx5/windows/mlx5_win_defs.h\n@@ -219,18 +219,6 @@ struct mlx5_action {\n \t} dest_tir;\n };\n \n-struct mlx5_err_cqe {\n-\tuint8_t\t\trsvd0[32];\n-\tuint32_t\tsrqn;\n-\tuint8_t\t\trsvd1[18];\n-\tuint8_t\t\tvendor_err_synd;\n-\tuint8_t\t\tsyndrome;\n-\tuint32_t\ts_wqe_opcode_qpn;\n-\tuint16_t\twqe_counter;\n-\tuint8_t\t\tsignature;\n-\tuint8_t\t\top_own;\n-};\n-\n struct mlx5_wqe_srq_next_seg {\n \tuint8_t\t\t\trsvd0[2];\n \trte_be16_t\t\tnext_wqe_index;\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 41d9752833..702108c5f9 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -602,7 +602,7 @@ mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,\n \tsize_t i;\n \n \tDRV_LOG(ERR, \"Error cqe:\");\n-\tfor (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)\n+\tfor (i = 0; i < sizeof(struct mlx5_error_cqe) >> 2; i += 4)\n \t\tDRV_LOG(ERR, \"%08X %08X %08X %08X\", cqe[i], cqe[i + 1],\n \t\t\tcqe[i + 2], cqe[i + 3]);\n \tDRV_LOG(ERR, \"\\nError wqe:\");\n@@ -620,7 +620,7 @@ mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,\n \t\t\t struct rte_comp_op *op)\n {\n \tconst uint32_t idx = qp->ci & (qp->entries_n - 1);\n-\tvolatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)\n+\tvolatile struct mlx5_error_cqe *cqe = (volatile struct mlx5_error_cqe *)\n \t\t\t\t\t\t\t &qp->cq.cqes[idx];\n \tvolatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)\n \t\t\t\t\t\t\t\t qp->qp.wqes;\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 5267f48c1e..ab2ffe6d7f 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -460,7 +460,7 @@ static __rte_noinline void\n mlx5_crypto_cqe_err_handle(struct mlx5_crypto_qp *qp, struct rte_crypto_op *op)\n {\n \tconst uint32_t idx = qp->ci & (qp->entries_n - 1);\n-\tvolatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)\n+\tvolatile struct mlx5_error_cqe *cqe = (volatile struct mlx5_error_cqe *)\n \t\t\t\t\t\t\t&qp->cq_obj.cqes[idx];\n \n \top->status = RTE_CRYPTO_OP_STATUS_ERROR;\ndiff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c\nindex 29bd7ce9e8..c2f9b2d507 100644\n--- a/drivers/net/mlx5/mlx5_flow_aso.c\n+++ b/drivers/net/mlx5/mlx5_flow_aso.c\n@@ -489,7 +489,7 @@ mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)\n \tint i;\n \n \tDRV_LOG(ERR, \"Error cqe:\");\n-\tfor (i = 0; i < 16; i += 4)\n+\tfor (i = 0; i < (int)sizeof(struct mlx5_error_cqe) / 4; i += 4)\n \t\tDRV_LOG(ERR, \"%08X %08X %08X %08X\", cqe[i], cqe[i + 1],\n \t\t\tcqe[i + 2], cqe[i + 3]);\n \tDRV_LOG(ERR, \"\\nError wqe:\");\n@@ -509,8 +509,8 @@ mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)\n {\n \tstruct mlx5_aso_cq *cq = &sq->cq;\n \tuint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);\n-\tvolatile struct mlx5_err_cqe *cqe =\n-\t\t\t(volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];\n+\tvolatile struct mlx5_error_cqe *cqe =\n+\t\t\t(volatile struct mlx5_error_cqe *)&cq->cq_obj.cqes[idx];\n \n \tcq->errors++;\n \tidx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex a2be523e9e..69fd173239 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -459,7 +459,7 @@ mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec,\n \t\t\tcontainer_of(rxq, struct mlx5_rxq_ctrl, rxq);\n \tunion {\n \t\tvolatile struct mlx5_cqe *cqe;\n-\t\tvolatile struct mlx5_err_cqe *err_cqe;\n+\t\tvolatile struct mlx5_error_cqe *err_cqe;\n \t} u = {\n \t\t.cqe = &(*rxq->cqes)[(rxq->cq_ci - vec) & cqe_mask],\n \t};\ndiff --git a/drivers/net/mlx5/mlx5_tx.c b/drivers/net/mlx5/mlx5_tx.c\nindex 14e1487e59..8b1a0ca3d3 100644\n--- a/drivers/net/mlx5/mlx5_tx.c\n+++ b/drivers/net/mlx5/mlx5_tx.c\n@@ -55,7 +55,7 @@ tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)\n \n /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */\n static int\n-check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)\n+check_err_cqe_seen(volatile struct mlx5_error_cqe *err_cqe)\n {\n \tstatic const uint8_t magic[] = \"seen\";\n \tint ret = 1;\n@@ -83,7 +83,7 @@ check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)\n */\n static int\n mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,\n-\t\t\t volatile struct mlx5_err_cqe *err_cqe)\n+\t\t\t volatile struct mlx5_error_cqe *err_cqe)\n {\n \tif (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {\n \t\tconst uint16_t wqe_m = ((1 << txq->wqe_n) - 1);\n@@ -107,7 +107,7 @@ mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\tmlx5_dump_debug_information(name, \"MLX5 Error CQ:\",\n \t\t\t\t\t\t (const void *)((uintptr_t)\n \t\t\t\t\t\t txq->cqes),\n-\t\t\t\t\t\t sizeof(struct mlx5_cqe) *\n+\t\t\t\t\t\t sizeof(struct mlx5_error_cqe) *\n \t\t\t\t\t\t (1 << txq->cqe_n));\n \t\t\tmlx5_dump_debug_information(name, \"MLX5 Error SQ:\",\n \t\t\t\t\t\t (const void *)((uintptr_t)\n@@ -206,7 +206,7 @@ mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t */\n \t\t\trte_wmb();\n \t\t\tret = mlx5_tx_error_cqe_handle\n-\t\t\t\t(txq, (volatile struct mlx5_err_cqe *)cqe);\n+\t\t\t\t(txq, (volatile struct mlx5_error_cqe *)cqe);\n \t\t\tif (unlikely(ret < 0)) {\n \t\t\t\t/*\n \t\t\t\t * Some error occurred on queue error\n", "prefixes": [] }