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GET /api/patches/127527/?format=api
{ "id": 127527, "url": "http://patchwork.dpdk.org/api/patches/127527/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230526031422.913377-7-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230526031422.913377-7-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230526031422.913377-7-suanmingm@nvidia.com", "date": "2023-05-26T03:14:18", "name": "[v2,6/9] common/mlx5: add WQE-based QP synchronous basics", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "df54f45849e775a1b18a88f2b9f904056e040337", "submitter": { "id": 1887, "url": "http://patchwork.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230526031422.913377-7-suanmingm@nvidia.com/mbox/", "series": [ { "id": 28197, "url": "http://patchwork.dpdk.org/api/series/28197/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28197", "date": "2023-05-26T03:14:12", "name": "crypto/mlx5: support AES-GCM", "version": 2, "mbox": "http://patchwork.dpdk.org/series/28197/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/127527/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/127527/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DD3A442BA3;\n\tFri, 26 May 2023 05:16:27 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D09F442D42;\n\tFri, 26 May 2023 05:15:54 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2083.outbound.protection.outlook.com [40.107.94.83])\n by mails.dpdk.org (Postfix) with ESMTP id 894A642D42\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v2 6/9] common/mlx5: add WQE-based QP synchronous basics", "Date": "Fri, 26 May 2023 06:14:18 +0300", "Message-ID": "<20230526031422.913377-7-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230526031422.913377-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>\n <20230526031422.913377-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT091:EE_|IA1PR12MB6436:EE_", "X-MS-Office365-Filtering-Correlation-Id": "375704ca-9088-48c8-decd-08db5d978227", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n CkSUqJbf7f4h/JcEezngO1G2kYAENENa0GLTYRZBEkcFEqYoTVb3p09069TnbheLOcN7F7umjcpTMlpByT6dxX06H+JOO0l0LQvd9gOzAd1zkl0Gk8lsQpD0Xcg4V+ss6hcLNTeK+KJHrv9LlECKdzRXFpv4MC/zuB7a3TzpUUO/4qkQBkbLXFzOBGMEgpUansPspuiFuvbzdCX7VK0Drv11tzcnA4kD0mcgIl7lAEsVvg/Ke9GPnM/xXnJxzzCyck/xS8u9MQEj2Wx19jBHfgF7n8B2NWd52Y5MkJajuZ/bvMqB6aXN2ajjS+rlxIov5/1C/ubfevZ/+7ymjE4A+fpftNwdbiIASLauEOB/i13HyDtJcd8mVbDwLzpzr3/lrOpJALk/j/cgi1lIMGSy7cIHkOK7GszjRyT6iBpHCrEaoStX095VidXa7K9OwzTtlD/ew1N/Npq1tFvsMDpkrk9lLzFgmbUvn6nqIUK269x0QVNrA4pnPgnkSLFPq01jyhzS4A6JY4DqQS6D1MODrKu/ZdR3xZkSqBhJmz2uh5HApeNz35I1qLZ8lewFFWoyPGBUP5E/1wCbZfZJcB/iUl7Yhn34fKT0vuuV4+v9et7jdprn2dJUCpI40epuT5azqlK1N9vOzYDGAQbXeycP1eeiWEHJ705izrrt4ONydk7jCNCcvLy+WkEs//2cNYfNltBiOnh+hMKqyHSgHM7Ip3Wv4ENJjIEamWoRzeUBSME=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199021)(46966006)(40470700004)(36840700001)(82740400003)(6666004)(7696005)(26005)(36860700001)(1076003)(6286002)(16526019)(107886003)(186003)(86362001)(110136005)(478600001)(54906003)(7636003)(356005)(336012)(47076005)(426003)(2616005)(4326008)(70586007)(70206006)(40460700003)(316002)(6636002)(5660300002)(8936002)(8676002)(2906002)(55016003)(41300700001)(40480700001)(36756003)(82310400005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 May 2023 03:15:50.6278 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 375704ca-9088-48c8-decd-08db5d978227", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT091.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6436", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Nvidia HW provides a synchronous mechanism between QPs. When\ncreating the QPs, user can set one as primary and another as\nfollower. The follower QP's WQE execution can be controlled\nby primary QP via SEND_EN WQE.\n\nThis commit introduces the SEND_EN WQE to improve the WQE\nexecution sync-up between primary and follower QPs.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++\n drivers/common/mlx5/mlx5_prm.h | 11 +++++++++++\n 3 files changed, 20 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 4332081165..ef87862a6d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -2475,6 +2475,12 @@ mlx5_devx_cmd_create_qp(void *ctx,\n \t\t\t\t attr->dbr_umem_valid);\n \t\t\tMLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);\n \t\t}\n+\t\tif (attr->cd_master)\n+\t\t\tMLX5_SET(qpc, qpc, cd_master, attr->cd_master);\n+\t\tif (attr->cd_slave_send)\n+\t\t\tMLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send);\n+\t\tif (attr->cd_slave_recv)\n+\t\t\tMLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv);\n \t\tMLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);\n \t\tMLX5_SET64(create_qp_in, in, wq_umem_offset,\n \t\t\t attr->wq_umem_offset);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex cb3f3a211b..e071cd841f 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -559,6 +559,9 @@ struct mlx5_devx_qp_attr {\n \tuint64_t wq_umem_offset;\n \tuint32_t user_index:24;\n \tuint32_t mmo:1;\n+\tuint32_t cd_master:1;\n+\tuint32_t cd_slave_send:1;\n+\tuint32_t cd_slave_recv:1;\n };\n \n struct mlx5_devx_virtio_q_couners_attr {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 3b26499a47..96d5eb8de3 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -589,6 +589,17 @@ struct mlx5_rdma_write_wqe {\n \tstruct mlx5_wqe_dseg dseg[];\n } __rte_packed;\n \n+struct mlx5_wqe_send_en_seg {\n+\tuint32_t reserve[2];\n+\tuint32_t sqnpc;\n+\tuint32_t qpn;\n+} __rte_packed;\n+\n+struct mlx5_wqe_send_en_wqe {\n+\tstruct mlx5_wqe_cseg ctr;\n+\tstruct mlx5_wqe_send_en_seg sseg;\n+} __rte_packed;\n+\n #ifdef PEDANTIC\n #pragma GCC diagnostic error \"-Wpedantic\"\n #endif\n", "prefixes": [ "v2", "6/9" ] }