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GET /api/patches/127544/?format=api
{ "id": 127544, "url": "http://patchwork.dpdk.org/api/patches/127544/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230526073850.101079-8-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230526073850.101079-8-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230526073850.101079-8-beilei.xing@intel.com", "date": "2023-05-26T07:38:44", "name": "[v4,07/13] net/cpfl: support hairpin queue configuration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8a5a5050f401066066a1fc66416c2e429c16e265", "submitter": { "id": 410, "url": "http://patchwork.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230526073850.101079-8-beilei.xing@intel.com/mbox/", "series": [ { "id": 28204, "url": "http://patchwork.dpdk.org/api/series/28204/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28204", "date": "2023-05-26T07:38:37", "name": "net/cpfl: add hairpin queue support", "version": 4, "mbox": "http://patchwork.dpdk.org/series/28204/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/127544/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/127544/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BA28342BA9;\n\tFri, 26 May 2023 10:03:25 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DF78442D46;\n\tFri, 26 May 2023 10:02:51 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 7846A42D3D\n for <dev@dpdk.org>; Fri, 26 May 2023 10:02:47 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 May 2023 01:02:47 -0700", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by fmsmga001.fm.intel.com with ESMTP; 26 May 2023 01:02:45 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1685088167; x=1716624167;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=b/OiDojAaUkroRWHkHPfxfFYkmNMWCyIWwSfrT5JPI8=;\n b=YMp7hdtxrYRr620nMTfFuLrqEN2voOoozqQ2gncRtf8FNAlQZx23f6m7\n 6GYtiVAQKPyaRoJ8juzMYh+jfhyRc+5RvVxFEjJ+ZTCfoJjJtghWwjFso\n Zwo1lHbQOQB5fk2/znHZlPEi/+oH7UunnzeturwDZdLsXa/dqrVUTcWTz\n zMWk/brORt42PKwa1+FyzAXQUo3DjBuI8kZJ2I0QjFs5Er+ua+Q5QEHVq\n +YoSA+xHmDtXog7C2tQorYVLJhujNi+h+dTcTFR8RnT2LCG1KVhRQXsq+\n OImbOgzX3H6BxNFvy+NNsiGuQB8oylskH04jt7hVq7P2eSqbOAR9zm2kA Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10721\"; a=\"338742704\"", "E=Sophos;i=\"6.00,193,1681196400\"; d=\"scan'208\";a=\"338742704\"", "E=McAfee;i=\"6600,9927,10721\"; a=\"849483889\"", "E=Sophos;i=\"6.00,193,1681196400\"; d=\"scan'208\";a=\"849483889\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>,\n Xiao Wang <xiao.w.wang@intel.com>", "Subject": "[PATCH v4 07/13] net/cpfl: support hairpin queue configuration", "Date": "Fri, 26 May 2023 07:38:44 +0000", "Message-Id": "<20230526073850.101079-8-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20230526073850.101079-1-beilei.xing@intel.com>", "References": "<20230519073116.56749-1-beilei.xing@intel.com>\n <20230526073850.101079-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nThis patch supports Rx/Tx hairpin queue configuration.\n\nSigned-off-by: Xiao Wang <xiao.w.wang@intel.com>\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c | 136 +++++++++++++++++++++++++++++++--\n drivers/net/cpfl/cpfl_rxtx.c | 80 +++++++++++++++++++\n drivers/net/cpfl/cpfl_rxtx.h | 7 ++\n 3 files changed, 217 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex b17c538ec2..a06def06d0 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -742,33 +742,157 @@ cpfl_config_rx_queues_irqs(struct rte_eth_dev *dev)\n \treturn idpf_vport_irq_map_config(vport, nb_rx_queues);\n }\n \n+/* Update hairpin_info for dev's tx hairpin queue */\n+static int\n+cpfl_txq_hairpin_info_update(struct rte_eth_dev *dev, uint16_t rx_port)\n+{\n+\tstruct cpfl_vport *cpfl_tx_vport = dev->data->dev_private;\n+\tstruct rte_eth_dev *peer_dev = &rte_eth_devices[rx_port];\n+\tstruct cpfl_vport *cpfl_rx_vport = peer_dev->data->dev_private;\n+\tstruct cpfl_txq_hairpin_info *hairpin_info;\n+\tstruct cpfl_tx_queue *cpfl_txq;\n+\tint i;\n+\n+\tfor (i = cpfl_tx_vport->nb_data_txq; i < dev->data->nb_tx_queues; i++) {\n+\t\tcpfl_txq = dev->data->tx_queues[i];\n+\t\thairpin_info = &cpfl_txq->hairpin_info;\n+\t\tif (hairpin_info->peer_rxp != rx_port) {\n+\t\t\tPMD_DRV_LOG(ERR, \"port %d is not the peer port\", rx_port);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\thairpin_info->peer_rxq_id =\n+\t\t\tcpfl_hw_qid_get(cpfl_rx_vport->p2p_q_chunks_info->rx_start_qid,\n+\t\t\t\t\thairpin_info->peer_rxq_id - cpfl_rx_vport->nb_data_rxq);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Bind Rx hairpin queue's memory zone to peer Tx hairpin queue's memory zone */\n+static void\n+cpfl_rxq_hairpin_mz_bind(struct rte_eth_dev *dev)\n+{\n+\tstruct cpfl_vport *cpfl_rx_vport = dev->data->dev_private;\n+\tstruct idpf_vport *vport = &cpfl_rx_vport->base;\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct idpf_hw *hw = &adapter->hw;\n+\tstruct cpfl_rx_queue *cpfl_rxq;\n+\tstruct cpfl_tx_queue *cpfl_txq;\n+\tstruct rte_eth_dev *peer_dev;\n+\tconst struct rte_memzone *mz;\n+\tuint16_t peer_tx_port;\n+\tuint16_t peer_tx_qid;\n+\tint i;\n+\n+\tfor (i = cpfl_rx_vport->nb_data_rxq; i < dev->data->nb_rx_queues; i++) {\n+\t\tcpfl_rxq = dev->data->rx_queues[i];\n+\t\tpeer_tx_port = cpfl_rxq->hairpin_info.peer_txp;\n+\t\tpeer_tx_qid = cpfl_rxq->hairpin_info.peer_txq_id;\n+\t\tpeer_dev = &rte_eth_devices[peer_tx_port];\n+\t\tcpfl_txq = peer_dev->data->tx_queues[peer_tx_qid];\n+\n+\t\t/* bind rx queue */\n+\t\tmz = cpfl_txq->base.mz;\n+\t\tcpfl_rxq->base.rx_ring_phys_addr = mz->iova;\n+\t\tcpfl_rxq->base.rx_ring = mz->addr;\n+\t\tcpfl_rxq->base.mz = mz;\n+\n+\t\t/* bind rx buffer queue */\n+\t\tmz = cpfl_txq->base.complq->mz;\n+\t\tcpfl_rxq->base.bufq1->rx_ring_phys_addr = mz->iova;\n+\t\tcpfl_rxq->base.bufq1->rx_ring = mz->addr;\n+\t\tcpfl_rxq->base.bufq1->mz = mz;\n+\t\tcpfl_rxq->base.bufq1->qrx_tail = hw->hw_addr +\n+\t\t\tcpfl_hw_qtail_get(cpfl_rx_vport->p2p_q_chunks_info->rx_buf_qtail_start,\n+\t\t\t\t\t0, cpfl_rx_vport->p2p_q_chunks_info->rx_buf_qtail_spacing);\n+\t}\n+}\n+\n static int\n cpfl_start_queues(struct rte_eth_dev *dev)\n {\n+\tstruct cpfl_vport *cpfl_vport = dev->data->dev_private;\n+\tstruct idpf_vport *vport = &cpfl_vport->base;\n \tstruct cpfl_rx_queue *cpfl_rxq;\n \tstruct cpfl_tx_queue *cpfl_txq;\n+\tint update_flag = 0;\n \tint err = 0;\n \tint i;\n \n+\t/* For normal data queues, configure, init and enale Txq.\n+\t * For non-manual bind hairpin queues, configure Txq.\n+\t */\n \tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n \t\tcpfl_txq = dev->data->tx_queues[i];\n \t\tif (cpfl_txq == NULL || cpfl_txq->base.tx_deferred_start)\n \t\t\tcontinue;\n-\t\terr = cpfl_tx_queue_start(dev, i);\n+\t\tif (!cpfl_txq->hairpin_info.hairpin_q) {\n+\t\t\terr = cpfl_tx_queue_start(dev, i);\n+\t\t\tif (err != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Tx queue %u\", i);\n+\t\t\t\treturn err;\n+\t\t\t}\n+\t\t} else if (!cpfl_vport->p2p_manual_bind) {\n+\t\t\tif (update_flag == 0) {\n+\t\t\t\terr = cpfl_txq_hairpin_info_update(dev,\n+\t\t\t\t\t\t\t\t cpfl_txq->hairpin_info.peer_rxp);\n+\t\t\t\tif (err != 0) {\n+\t\t\t\t\tPMD_DRV_LOG(ERR, \"Fail to update Tx hairpin queue info\");\n+\t\t\t\t\treturn err;\n+\t\t\t\t}\n+\t\t\t\tupdate_flag = 1;\n+\t\t\t}\n+\t\t\terr = cpfl_hairpin_txq_config(vport, cpfl_txq);\n+\t\t\tif (err != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Fail to configure hairpin Tx queue %u\", i);\n+\t\t\t\treturn err;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* For non-manual bind hairpin queues, configure Tx completion queue first.*/\n+\tif (!cpfl_vport->p2p_manual_bind && cpfl_vport->p2p_tx_complq != NULL) {\n+\t\terr = cpfl_hairpin_tx_complq_config(cpfl_vport);\n \t\tif (err != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Tx queue %u\", i);\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to config Tx completion queue\");\n \t\t\treturn err;\n \t\t}\n \t}\n \n+\t/* For non-manual bind hairpin queues, configure Rx buffer queue.*/\n+\tif (!cpfl_vport->p2p_manual_bind && cpfl_vport->p2p_rx_bufq != NULL) {\n+\t\tcpfl_rxq_hairpin_mz_bind(dev);\n+\t\terr = cpfl_hairpin_rx_bufq_config(cpfl_vport);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Fail to config Rx buffer queue\");\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\t/* For normal data queues, configure, init and enale Rxq.\n+\t * For non-manual bind hairpin queues, configure Rxq, and then init Rxq.\n+\t */\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\tcpfl_rxq = dev->data->rx_queues[i];\n \t\tif (cpfl_rxq == NULL || cpfl_rxq->base.rx_deferred_start)\n \t\t\tcontinue;\n-\t\terr = cpfl_rx_queue_start(dev, i);\n-\t\tif (err != 0) {\n-\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Rx queue %u\", i);\n-\t\t\treturn err;\n+\t\tif (!cpfl_rxq->hairpin_info.hairpin_q) {\n+\t\t\terr = cpfl_rx_queue_start(dev, i);\n+\t\t\tif (err != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Fail to start Rx queue %u\", i);\n+\t\t\t\treturn err;\n+\t\t\t}\n+\t\t} else if (!cpfl_vport->p2p_manual_bind) {\n+\t\t\terr = cpfl_hairpin_rxq_config(vport, cpfl_rxq);\n+\t\t\tif (err != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Fail to configure hairpin Rx queue %u\", i);\n+\t\t\t\treturn err;\n+\t\t\t}\n+\t\t\terr = cpfl_rx_queue_init(dev, i);\n+\t\t\tif (err != 0) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Fail to init hairpin Rx queue %u\", i);\n+\t\t\t\treturn err;\n+\t\t\t}\n \t\t}\n \t}\n \ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex 9625629a20..702054d1c5 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -911,6 +911,86 @@ cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \treturn 0;\n }\n \n+int\n+cpfl_hairpin_rx_bufq_config(struct cpfl_vport *cpfl_vport)\n+{\n+\tstruct idpf_rx_queue *rx_bufq = cpfl_vport->p2p_rx_bufq;\n+\tstruct virtchnl2_rxq_info rxq_info[1] = {0};\n+\n+\trxq_info[0].type = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;\n+\trxq_info[0].queue_id = rx_bufq->queue_id;\n+\trxq_info[0].ring_len = rx_bufq->nb_rx_desc;\n+\trxq_info[0].dma_ring_addr = rx_bufq->rx_ring_phys_addr;\n+\trxq_info[0].desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n+\trxq_info[0].rx_buffer_low_watermark = CPFL_RXBUF_LOW_WATERMARK;\n+\trxq_info[0].model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\trxq_info[0].data_buffer_size = rx_bufq->rx_buf_len;\n+\trxq_info[0].buffer_notif_stride = CPFL_RX_BUF_STRIDE;\n+\n+\treturn idpf_vc_rxq_config_by_info(&cpfl_vport->base, rxq_info, 1);\n+}\n+\n+int\n+cpfl_hairpin_rxq_config(struct idpf_vport *vport, struct cpfl_rx_queue *cpfl_rxq)\n+{\n+\tstruct virtchnl2_rxq_info rxq_info[1] = {0};\n+\tstruct idpf_rx_queue *rxq = &cpfl_rxq->base;\n+\n+\trxq_info[0].type = VIRTCHNL2_QUEUE_TYPE_RX;\n+\trxq_info[0].queue_id = rxq->queue_id;\n+\trxq_info[0].ring_len = rxq->nb_rx_desc;\n+\trxq_info[0].dma_ring_addr = rxq->rx_ring_phys_addr;\n+\trxq_info[0].rx_bufq1_id = rxq->bufq1->queue_id;\n+\trxq_info[0].max_pkt_size = vport->max_pkt_len;\n+\trxq_info[0].desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n+\trxq_info[0].qflags |= VIRTCHNL2_RX_DESC_SIZE_16BYTE;\n+\n+\trxq_info[0].data_buffer_size = rxq->rx_buf_len;\n+\trxq_info[0].model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\trxq_info[0].rx_buffer_low_watermark = CPFL_RXBUF_LOW_WATERMARK;\n+\n+\tPMD_DRV_LOG(NOTICE, \"hairpin: vport %u, Rxq id 0x%x\",\n+\t\tvport->vport_id, rxq_info[0].queue_id);\n+\n+\treturn idpf_vc_rxq_config_by_info(vport, rxq_info, 1);\n+}\n+\n+int\n+cpfl_hairpin_tx_complq_config(struct cpfl_vport *cpfl_vport)\n+{\n+\tstruct idpf_tx_queue *tx_complq = cpfl_vport->p2p_tx_complq;\n+\tstruct virtchnl2_txq_info txq_info[1] = {0};\n+\n+\ttxq_info[0].dma_ring_addr = tx_complq->tx_ring_phys_addr;\n+\ttxq_info[0].type = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;\n+\ttxq_info[0].queue_id = tx_complq->queue_id;\n+\ttxq_info[0].ring_len = tx_complq->nb_tx_desc;\n+\ttxq_info[0].peer_rx_queue_id = cpfl_vport->p2p_rx_bufq->queue_id;\n+\ttxq_info[0].model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\ttxq_info[0].sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n+\n+\treturn idpf_vc_txq_config_by_info(&cpfl_vport->base, txq_info, 1);\n+}\n+\n+int\n+cpfl_hairpin_txq_config(struct idpf_vport *vport, struct cpfl_tx_queue *cpfl_txq)\n+{\n+\tstruct idpf_tx_queue *txq = &cpfl_txq->base;\n+\tstruct virtchnl2_txq_info txq_info[1] = {0};\n+\n+\ttxq_info[0].dma_ring_addr = txq->tx_ring_phys_addr;\n+\ttxq_info[0].type = VIRTCHNL2_QUEUE_TYPE_TX;\n+\ttxq_info[0].queue_id = txq->queue_id;\n+\ttxq_info[0].ring_len = txq->nb_tx_desc;\n+\ttxq_info[0].tx_compl_queue_id = txq->complq->queue_id;\n+\ttxq_info[0].relative_queue_id = txq->queue_id;\n+\ttxq_info[0].peer_rx_queue_id = cpfl_txq->hairpin_info.peer_rxq_id;\n+\ttxq_info[0].model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\ttxq_info[0].sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n+\n+\treturn idpf_vc_txq_config_by_info(vport, txq_info, 1);\n+}\n+\n int\n cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nindex 06198d4aad..872ebc1bfd 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.h\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -32,12 +32,15 @@\n #define CPFL_RING_BASE_ALIGN\t128\n \n #define CPFL_DEFAULT_RX_FREE_THRESH\t32\n+#define CPFL_RXBUF_LOW_WATERMARK\t64\n \n #define CPFL_DEFAULT_TX_RS_THRESH\t32\n #define CPFL_DEFAULT_TX_FREE_THRESH\t32\n \n #define CPFL_SUPPORT_CHAIN_NUM 5\n \n+#define CPFL_RX_BUF_STRIDE 64\n+\n struct cpfl_rxq_hairpin_info {\n \tbool hairpin_q;\t\t/* if rx queue is a hairpin queue */\n \tuint16_t peer_txp;\n@@ -95,4 +98,8 @@ int cpfl_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n int cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\t\t\tuint16_t nb_desc,\n \t\t\t\tconst struct rte_eth_hairpin_conf *conf);\n+int cpfl_hairpin_tx_complq_config(struct cpfl_vport *cpfl_vport);\n+int cpfl_hairpin_txq_config(struct idpf_vport *vport, struct cpfl_tx_queue *cpfl_txq);\n+int cpfl_hairpin_rx_bufq_config(struct cpfl_vport *cpfl_vport);\n+int cpfl_hairpin_rxq_config(struct idpf_vport *vport, struct cpfl_rx_queue *cpfl_rxq);\n #endif /* _CPFL_RXTX_H_ */\n", "prefixes": [ "v4", "07/13" ] }