Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/127821/?format=api
{ "id": 127821, "url": "http://patchwork.dpdk.org/api/patches/127821/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230601080001.3310444-3-dongzhou@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230601080001.3310444-3-dongzhou@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230601080001.3310444-3-dongzhou@nvidia.com", "date": "2023-06-01T08:00:00", "name": "[2/2] net/mlx5/hws: add support for infiniband BTH match", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ec6b8aa7de389d6c44095f69ffdc409e88981b21", "submitter": { "id": 2011, "url": "http://patchwork.dpdk.org/api/people/2011/?format=api", "name": "Dong Zhou", "email": "dongzhou@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230601080001.3310444-3-dongzhou@nvidia.com/mbox/", "series": [ { "id": 28293, "url": "http://patchwork.dpdk.org/api/series/28293/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28293", "date": "2023-06-01T07:59:58", "name": "mlx5 supports InfiniBand BTH item match", "version": 1, "mbox": "http://patchwork.dpdk.org/series/28293/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/127821/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/127821/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4139B42C01;\n\tThu, 1 Jun 2023 10:00:47 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 337C642C4D;\n\tThu, 1 Jun 2023 10:00:47 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2068.outbound.protection.outlook.com [40.107.237.68])\n by mails.dpdk.org (Postfix) with ESMTP id 5122C427E9\n for <dev@dpdk.org>; Thu, 1 Jun 2023 10:00:46 +0200 (CEST)", "from MW4PR03CA0300.namprd03.prod.outlook.com (2603:10b6:303:b5::35)\n by DS7PR12MB6238.namprd12.prod.outlook.com (2603:10b6:8:96::11) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.24; Thu, 1 Jun\n 2023 08:00:44 +0000", "from CO1NAM11FT079.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:b5:cafe::a) by MW4PR03CA0300.outlook.office365.com\n (2603:10b6:303:b5::35) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.23 via Frontend\n Transport; Thu, 1 Jun 2023 08:00:44 +0000", "from mail.nvidia.com (216.228.117.161) by\n CO1NAM11FT079.mail.protection.outlook.com (10.13.175.134) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6455.23 via Frontend Transport; Thu, 1 Jun 2023 08:00:43 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Thu, 1 Jun 2023\n 01:00:22 -0700", "from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 1 Jun 2023\n 01:00:19 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=NfmYVsJglv3Q9baMPzI8fQItC3tjDTjfsw9DDSfw4HO4BxRoXl5zPwABxbsPV0JYKeG8hPihdZDJDtRHoGo6Xm34WT9crwHDxIvNTUhj5+dASjXxF76mXwdClP5372eHZncWqcOifLL8uI/R/rL58BgqUjilfrwV88TbgZRJcyEZ2t+aSmZMccdJvWxHsHS4jej0wit1mTkUvRGDlmoHY/UHiTESCGPd3XfwklZg+Dsdt5pRZ72cvAstD4aGIVETHnL/GN0TEMgiH+qfusZWvLPG79SDBcFo4l5AWMAmzEGbycna7UlHuuL5dY22tJLwbgbu51f156i+9tdqdPNU1g==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=/cAhWcDzqtUXa/rGn0ddg9WxEobXTc7QHeax3Uo5XKE=;\n b=oQ59l85PewZ9xK8iHzMVmm0vNVkIx/O7UsoFZZS/ZrNn5jeCEB+b8V/q8rUe+yofB+P5L1e55xZuYTWsY400MrHAnxxER1tvVSJP3i7MevKHkoI5Iu4jRsBWt25BeeiMjNSvflbGizOp+neAtiRWw9Yi7ajGuZpa4TkrGAl1qHD+QGgpT9b4LWtuMR1D4th9UZXWuWCsF5wCvhnnPQbxwwTiL1XCrgbrM2dAOFE3AXdEvHPOS6ts8yymz2uiXgfqs3S4VhPAiq55pPYQTLCdvw8bhCvKMeBRpTX+Yw36/J4H1P2+6mrwTFuRWuQz2kqk7v74WBmpXZGJ1bg1N8RkNA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/cAhWcDzqtUXa/rGn0ddg9WxEobXTc7QHeax3Uo5XKE=;\n b=c3OqZzvdzKx+Iaxaq5tL3m6rTnzJi7gpqZi3arAzvLCL/NUtCsXOfREGdFntikWTSc+prOJyZ8uO0ruRf+yFUPdTA7ZLjRZtQtTBDM5bGwRG88lYDukVefncvkW8wnYFMxkw9j0pI29Vri5gqujZAu4CObGadPh4Luk0kr4bgQdLyhJkDbtWg9IGdMYLq0qG6ro4oVUWsWJ131UWcmFdHSHowdI4FltfyzlaZiROk8ckt6arCFWCtfA3XUyry3EueHP33JKgks+JPa8lvJeMQJkQFZPz2bHlzTjZhJtBvQ1uMiMafY49p/QQL2ZzB6jwTiocrNzKuN6i4jjQ3PqiCw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Dong Zhou <dongzhou@nvidia.com>", "To": "<orika@nvidia.com>, <valex@nvidia.com>, <viacheslavo@nvidia.com>,\n <thomas@monjalon.net>, Matan Azrad <matan@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH 2/2] net/mlx5/hws: add support for infiniband BTH match", "Date": "Thu, 1 Jun 2023 11:00:00 +0300", "Message-ID": "<20230601080001.3310444-3-dongzhou@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230601080001.3310444-1-dongzhou@nvidia.com>", "References": "<20230601080001.3310444-1-dongzhou@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT079:EE_|DS7PR12MB6238:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3de20d95-4f64-44eb-60f4-08db62764cc9", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 9GMhq4iMYJikFbXZNyfJJvoF2cLIDvye3TJodpoaWVUeLyrSEoZIn9WrR1bFK3Tk52D7lRDtphAkw1rTx6aXiX1EuYrMWyPy7PRVgoM/kog0YFPgJTKnioClBOmZeHv6uXf4sdCiDIz1+e4HDqUHBVYSSwZfCdHMUQXBl0hsf0IifBgLZg4dnx774OIMsgXiL5a03uknq2Luyou8OIvVGPjS2YOz/72KG8j71ocmas0nbfIM5JeDFJ2ShhE3iNgIexD4o4TjPJ9lxZedqOqFErA3rmjL0qqq2/WfOcTLlZWTwQ5zX4m1JIFcwYNnDq9fDvZoJZtOEfjIlp9PnIECde+rFWpPm+sePC1yGm2to31ks2rIaEaeucjLlkQeCR67mY2cHTf33o5mOKoiSuVG1+7eVP5hgEQoGFB6wkCsaPyIyBPigzssOTbfqts7gIyT6/1tce70eJd/8ugTo7LHjP5pfIl50XI1t8tGt2z/ro6O9RUkWhzKM39SsO/6xAwcosUcodnwd5t9smgrnQ+fNrj7k5u8uEL4hHdq5Sa7inBpqJuaJKAnfXlQ3aR57qacGjEUcZn6q1yD0PYRHpWho5AQI/2mzpvigRB2e5Lx+lc8TlGramN0da1TNF4hkUatmzEcmxX+m56Jn55MA8dJtYy5VlstCydbAiouDQ6xsEbmRe1l5BK6/gdgG4W1m/vtbQphGt9Zi47lsIQ4haxE2RcLp+sEiEMxlXghAHZs7GCdJ/NnxN9rKbBdk4eI1hR9", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(39860400002)(136003)(396003)(346002)(376002)(451199021)(46966006)(40470700004)(36840700001)(54906003)(110136005)(5660300002)(8936002)(8676002)(6636002)(2906002)(4326008)(70586007)(70206006)(41300700001)(316002)(478600001)(40460700003)(107886003)(7696005)(6666004)(7636003)(1076003)(82740400003)(40480700001)(6286002)(186003)(16526019)(26005)(36756003)(426003)(83380400001)(47076005)(336012)(36860700001)(82310400005)(55016003)(356005)(86362001)(2616005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Jun 2023 08:00:43.5423 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3de20d95-4f64-44eb-60f4-08db62764cc9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT079.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB6238", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds support to match opcode and dst_qp fields in\ninfiniband BTH. Currently, only the RoCEv2 packet is supported,\nthe input BTH match item is defaulted to match one RoCEv2 packet.\n\nSigned-off-by: Dong Zhou <dongzhou@nvidia.com>\nAcked-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 76 ++++++++++++++++++++++++++-\n drivers/net/mlx5/hws/mlx5dr_definer.h | 2 +\n drivers/net/mlx5/mlx5_flow_hw.c | 1 +\n 3 files changed, 78 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex f92d3e8e1f..1a427c9b64 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -10,6 +10,7 @@\n #define ETH_TYPE_IPV6_VXLAN\t0x86DD\n #define ETH_VXLAN_DEFAULT_PORT\t4789\n #define IP_UDP_PORT_MPLS\t6635\n+#define UDP_ROCEV2_PORT\t4791\n #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS)\n \n #define STE_NO_VLAN\t0x0\n@@ -171,7 +172,9 @@ struct mlx5dr_definer_conv_data {\n \tX(SET_BE16,\tgre_opt_checksum,\tv->checksum_rsvd.checksum,\trte_flow_item_gre_opt) \\\n \tX(SET,\t\tmeter_color,\t\trte_col_2_mlx5_col(v->color),\trte_flow_item_meter_color) \\\n \tX(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \\\n-\tX(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp)\n+\tX(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) \\\n+\tX(SET,\t\tib_l4_udp_port,\t\tUDP_ROCEV2_PORT,\trte_flow_item_ib_bth) \\\n+\tX(SET,\t\tib_l4_opcode,\t\tv->hdr.opcode,\t\trte_flow_item_ib_bth)\n \n /* Item set function format */\n #define X(set_type, func_name, value, item_type) \\\n@@ -583,6 +586,16 @@ mlx5dr_definer_mpls_label_set(struct mlx5dr_definer_fc *fc,\n \tmemcpy(tag + fc->byte_off + sizeof(v->label_tc_s), &v->ttl, sizeof(v->ttl));\n }\n \n+static void\n+mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_spec,\n+\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_ib_bth *v = item_spec;\n+\n+\tmemcpy(tag + fc->byte_off, &v->hdr.dst_qp, sizeof(v->hdr.dst_qp));\n+}\n+\n static int\n mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd,\n \t\t\t struct rte_flow_item *item,\n@@ -2041,6 +2054,63 @@ mlx5dr_definer_conv_item_flex_parser(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t struct rte_flow_item *item,\n+\t\t\t int item_idx)\n+{\n+\tconst struct rte_flow_item_ib_bth *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tbool inner = cd->tunnel;\n+\n+\t/* In order to match on RoCEv2(layer4 ib), we must match\n+\t * on ip_protocol and l4_dport.\n+\t */\n+\tif (!cd->relaxed) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_udp_protocol_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, l4_type_bwc, inner);\n+\t\t}\n+\n+\t\tfc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_ib_l4_udp_port_set;\n+\t\t\tDR_CALC_SET(fc, eth_l4, destination_port, inner);\n+\t\t}\n+\t}\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (m->hdr.se || m->hdr.m || m->hdr.padcnt || m->hdr.tver ||\n+\t\tm->hdr.pkey || m->hdr.f || m->hdr.b || m->hdr.rsvd0 ||\n+\t\tm->hdr.a || m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (m->hdr.opcode) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_OPCODE];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ib_l4_opcode_set;\n+\t\tDR_CALC_SET_HDR(fc, ib_l4, opcode);\n+\t}\n+\n+\tif (!is_mem_zero(m->hdr.dst_qp, 3)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_QPN];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ib_l4_qp_set;\n+\t\tDR_CALC_SET_HDR(fc, ib_l4, qp);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_match_template *mt,\n@@ -2182,6 +2252,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\titem_flags |= MLX5_FLOW_LAYER_MPLS;\n \t\t\tcd.mpls_idx++;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n+\t\t\tret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_ITEM_IB_BTH;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDR_LOG(ERR, \"Unsupported item type %d\", items->type);\n \t\t\trte_errno = ENOTSUP;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex 90ec4ce845..6b645f4cf0 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -134,6 +134,8 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS2_I,\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS3_I,\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS4_I,\n+\tMLX5DR_DEFINER_FNAME_IB_L4_OPCODE,\n+\tMLX5DR_DEFINER_FNAME_IB_L4_QPN,\n \tMLX5DR_DEFINER_FNAME_MAX,\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 853c94af9c..f9e7f844ea 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -4969,6 +4969,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:\n \t\tcase RTE_FLOW_ITEM_TYPE_ESP:\n \t\tcase RTE_FLOW_ITEM_TYPE_FLEX:\n+\t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n \t\t\t/*\n", "prefixes": [ "2/2" ] }