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GET /api/patches/128533/?format=api
{ "id": 128533, "url": "http://patchwork.dpdk.org/api/patches/128533/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230613052810.4052102-2-bneuman@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613052810.4052102-2-bneuman@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613052810.4052102-2-bneuman@nvidia.com", "date": "2023-06-13T05:28:10", "name": "[2/2] net/mlx5: add support for send to kernel over HWS", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f0e4fafce92a6a16e2c30c904978ed8aac806894", "submitter": { "id": 3103, "url": "http://patchwork.dpdk.org/api/people/3103/?format=api", "name": "Bar Neuman", "email": "bneuman@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230613052810.4052102-2-bneuman@nvidia.com/mbox/", "series": [ { "id": 28471, "url": "http://patchwork.dpdk.org/api/series/28471/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28471", "date": "2023-06-13T05:28:09", "name": "[1/2] net/mlx5/hws: removing the table name from dest root table", "version": 1, "mbox": "http://patchwork.dpdk.org/series/28471/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/128533/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/128533/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D5EB342C9E;\n\tTue, 13 Jun 2023 07:29:13 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C3E2F4161A;\n\tTue, 13 Jun 2023 07:29:13 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2075.outbound.protection.outlook.com [40.107.244.75])\n by mails.dpdk.org (Postfix) with ESMTP id 0EF4941149\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Bar Neuman <bneuman@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <rasland@nvidia.com>, <matan@nvidia.com>,\n <viacheslavo@nvidia.com>, <mkashani@nvidia.com>", "Subject": "[PATCH 2/2] net/mlx5: add support for send to kernel over HWS", "Date": "Tue, 13 Jun 2023 05:28:10 +0000", "Message-ID": "<20230613052810.4052102-2-bneuman@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230613052810.4052102-1-bneuman@nvidia.com>", "References": "<20230613052810.4052102-1-bneuman@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT010:EE_|SA1PR12MB7295:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4216b10b-2252-4626-ace9-08db6bcf1d20", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n SbVn8R0Z7yK8ywHZN5oeKeCDiOAEk9b600m08M0f6n+cleIyOT3dhU+GQaykWHAZJNZj5H6QeqiSA3DqIkt2boObW0jt/5gxM1TUcEz/+H9g+CYuSTqvklisn6rOGJtn7Bh52MQmx5haye5vxzNGuRZV3rleee/bEXSiLquGHXep4/nUW3nOGy0VbW82mVD9Pl+AG56LS/pI+9DkonCy65Dz8GVuve2tg2Ph5uUh9TmXdRqN4qliD1VVmkLqai63ayA+md4IxRDVkfCyolG+fhZUvPKjoCrBMNeKLWPk/6k7dSJRpvw4NyKGepwVip9Gk7M7B7DozTJ794AedihcbsJ4zYxIxL5544mejF9QqzIuAsjl+7B42VTnn0DjkxaboK698V5At/H3ki5G98huA12gVIn1ufxh7oB5+e8IrD9WGFv9pM8XTNJeimKnL3I9nW47fOnT8qkRxvINxShyq3YPn5tSXCb1jUbmGWSaGyD6kTNNiRe9APxVLvBj8Nbnc9aNBrS1k6xY9CR0g0RDvaWKg+z2jKTvP+QRkgYBWrFhDe4L4DlHQ9+7rTpIwB5e8PAlf9jwqTO+8c7WeRnovkP5uaTQVxhP5MSiDkV7MMRcm0hLBxQN9GcHqSnbYtb95o3QxWnnyvP2bNpOqoq8/mQg3W+UhxKMK0bi+SkbTMp9BKmJAx1V4XlxcxHrzrCHGp+5jnsGbE9XHEROL7JrSeiEQ5jvx0noMT6qKQZlwSr1dsl3TmqhG7PQ+HTDYyBZpWKggIFIPC64z5DeQtQyKmRHzsM8r21OdX8g07PGWAQ=", "X-Forefront-Antispam-Report": "CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(396003)(39860400002)(136003)(346002)(376002)(451199021)(36840700001)(40470700004)(46966006)(186003)(40460700003)(82740400003)(6666004)(7696005)(40480700001)(26005)(107886003)(55016003)(36860700001)(83380400001)(426003)(47076005)(36756003)(336012)(1076003)(6286002)(2616005)(54906003)(316002)(86362001)(82310400005)(6916009)(70206006)(5660300002)(4326008)(8676002)(8936002)(70586007)(2906002)(356005)(41300700001)(7636003)(478600001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Jun 2023 05:29:09.2890 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4216b10b-2252-4626-ace9-08db6bcf1d20", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT010.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB7295", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added hws send to kernel action and root tbl in mlx5_priv.\nInitialized in hws configure and used in hws actions translate.\n\nSigned-off-by: Bar Neuman <bneuman@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 2 ++\n drivers/net/mlx5/mlx5_flow_hw.c | 59 +++++++++++++++++++++++++++++++--\n 2 files changed, 59 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 021049ad2b..c3f1a49f86 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1852,6 +1852,8 @@ struct mlx5_priv {\n \tstruct mlx5dr_action *hw_drop[2];\n \t/* HW steering global tag action. */\n \tstruct mlx5dr_action *hw_tag[2];\n+\t/* HW steering global send to kernel action. */\n+\tstruct mlx5dr_action *hw_send_to_kernel;\n \t/* HW steering create ongoing rte flow table list header. */\n \tLIST_HEAD(flow_hw_tbl_ongo, rte_flow_template_table) flow_hw_tbl_ongo;\n \tstruct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex f17a2a0522..74985009df 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -1620,8 +1620,18 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\trefmt_type = MLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:\n-\t\t\tDRV_LOG(ERR, \"send to kernel action is not supported in HW steering.\");\n-\t\t\tgoto err;\n+\t\t\tflow_hw_translate_group(dev, cfg, attr->group,\n+\t\t\t\t\t\t&target_grp, error);\n+\t\t\tif (target_grp == 0) {\n+\t\t\t\t__flow_hw_action_template_destroy(dev, acts);\n+\t\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\tNULL,\n+\t\t\t\t\t\t\"Send to kernel action on root table is not supported in HW steering mode\");\n+\t\t\t}\n+\t\t\taction_pos = at->actions_off[actions - at->actions];\n+\t\t\tacts->rule_acts[action_pos].action = priv->hw_send_to_kernel;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:\n \t\t\terr = flow_hw_modify_field_compile(dev, attr, action_start,\n \t\t\t\t\t\t\t actions, masks, acts, &mhdr,\n@@ -4031,6 +4041,7 @@ flow_hw_template_expand_modify_field(struct rte_flow_action actions[],\n \t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:\n \t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n \t\tcase RTE_FLOW_ACTION_TYPE_DROP:\n+\t\tcase RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:\n \t\tcase RTE_FLOW_ACTION_TYPE_JUMP:\n \t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n \t\tcase RTE_FLOW_ACTION_TYPE_RSS:\n@@ -4179,6 +4190,21 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev,\n \t\t\t/* TODO: Validation logic */\n \t\t\taction_flags |= MLX5_FLOW_ACTION_JUMP;\n \t\t\tbreak;\n+#ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE\n+\t\tcase RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL:\n+\t\t\tif (priv->shared_host)\n+\t\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\t\t action,\n+\t\t\t\t\t\t\t \"action not supported in guest port\");\n+\t\t\tif (!priv->hw_send_to_kernel)\n+\t\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n+\t\t\t\t\t\t\t action,\n+\t\t\t\t\t\t\t \"action is not available\");\n+\t\t\taction_flags |= MLX5_FLOW_ACTION_SEND_TO_KERNEL;\n+\t\t\tbreak;\n+#endif\n \t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n \t\t\t/* TODO: Validation logic */\n \t\t\taction_flags |= MLX5_FLOW_ACTION_QUEUE;\n@@ -4320,6 +4346,7 @@ static enum mlx5dr_action_type mlx5_hw_dr_action_types[] = {\n \t[RTE_FLOW_ACTION_TYPE_CONNTRACK] = MLX5DR_ACTION_TYP_ASO_CT,\n \t[RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = MLX5DR_ACTION_TYP_POP_VLAN,\n \t[RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = MLX5DR_ACTION_TYP_PUSH_VLAN,\n+\t[RTE_FLOW_ACTION_TYPE_SEND_TO_KERNEL] = MLX5DR_ACTION_TYP_DEST_ROOT,\n };\n \n static int\n@@ -5721,6 +5748,30 @@ flow_hw_free_vport_actions(struct mlx5_priv *priv)\n \tpriv->hw_vport = NULL;\n }\n \n+static void\n+flow_hw_create_send_to_kernel_actions(struct mlx5_priv *priv __rte_unused)\n+{\n+#ifdef HAVE_MLX5DV_DR_ACTION_CREATE_DEST_ROOT_TABLE\n+\tpriv->hw_send_to_kernel =\n+\t\t\tmlx5dr_action_create_dest_root(priv->dr_ctx,\n+\t\t\t\t\t\t MLX5_HW_LOWEST_PRIO_ROOT,\n+\t\t\t\t\t\t MLX5DR_ACTION_FLAG_HWS_RX);\n+\tif (!priv->hw_send_to_kernel) {\n+\t\tDRV_LOG(WARNING, \"Unable to create HWS send to kernel action\");\n+\t\treturn;\n+\t}\n+#endif\n+}\n+\n+static void\n+flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)\n+{\n+\tif (priv->hw_send_to_kernel) {\n+\t\tmlx5dr_action_destroy(priv->hw_send_to_kernel);\n+\t\tpriv->hw_send_to_kernel = NULL;\n+\t}\n+}\n+\n /**\n * Create an egress pattern template matching on source SQ.\n *\n@@ -7584,6 +7635,8 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\tgoto err;\n \t\t}\n \t}\n+\tif (!priv->shared_host)\n+\t\tflow_hw_create_send_to_kernel_actions(priv);\n \tif (port_attr->nb_conn_tracks || (host_priv && host_priv->hws_ctpool)) {\n \t\tmem_size = sizeof(struct mlx5_aso_sq) * nb_q_updated +\n \t\t\t sizeof(*priv->ct_mng);\n@@ -7646,6 +7699,7 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\tpriv->hws_cpool = NULL;\n \t}\n \tmlx5_flow_quota_destroy(dev);\n+\tflow_hw_destroy_send_to_kernel_action(priv);\n \tflow_hw_free_vport_actions(priv);\n \tfor (i = 0; i < MLX5_HW_ACTION_FLAG_MAX; i++) {\n \t\tif (priv->hw_drop[i])\n@@ -7726,6 +7780,7 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \t\t\tmlx5dr_action_destroy(priv->hw_tag[i]);\n \t}\n \tflow_hw_destroy_vlan(dev);\n+\tflow_hw_destroy_send_to_kernel_action(priv);\n \tflow_hw_free_vport_actions(priv);\n \tif (priv->acts_ipool) {\n \t\tmlx5_ipool_destroy(priv->acts_ipool);\n", "prefixes": [ "2/2" ] }