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GET /api/patches/128671/?format=api
{ "id": 128671, "url": "http://patchwork.dpdk.org/api/patches/128671/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230614130901.3245809-4-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230614130901.3245809-4-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230614130901.3245809-4-gakhil@marvell.com", "date": "2023-06-14T13:08:49", "name": "[v5,03/15] common/cnxk: add MACsec SC configuration APIs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1f8cf9a77e8b5ed844aa92b8bad687762dd4e93d", "submitter": { "id": 2094, "url": "http://patchwork.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230614130901.3245809-4-gakhil@marvell.com/mbox/", "series": [ { "id": 28508, "url": "http://patchwork.dpdk.org/api/series/28508/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28508", "date": "2023-06-14T13:08:46", "name": "net/cnxk: add MACsec support", "version": 5, "mbox": "http://patchwork.dpdk.org/series/28508/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/128671/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/128671/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8C55C42CB3;\n\tWed, 14 Jun 2023 15:09:40 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 41A6F42BB1;\n\tWed, 14 Jun 2023 15:09:24 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 69FB642BB1\n for <dev@dpdk.org>; Wed, 14 Jun 2023 15:09:22 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 35ECFkSU027153; Wed, 14 Jun 2023 06:09:21 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r7dd2r5nn-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 14 Jun 2023 06:09:21 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Wed, 14 Jun 2023 06:09:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Wed, 14 Jun 2023 06:09:19 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id A508E3F7091;\n Wed, 14 Jun 2023 06:09:14 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=PrfRwxL9G1x8/uWycJQdmX/3rDeWi3HFsV12KwEtblI=;\n b=XHgHd9StdiBlac6baVDt1g73/qyXUF1XVgcTpldxsxrtZM8M1Q13xK8ENnwWIOoCNFfB\n ZW4VVOR3ZoDJIDH1scrqA7xdVj0ppaccEGn4C3f2FsdRsMvHNdXRwiRL+ZWpNcRc2qpG\n rgdr/5a3gqEHlrCRfLUSkQKvrW+SMoMbRuJSQTujNlyckyBj8Clhkzzw/NulqguVGk4F\n gSVEOoloXcQVbQFJtxzg2rOsnATVkAXSYVjIFmrIDP+O1hJYDYWM2j7lYH+r4aUpZSLM\n 4EwlJ6KK+DPVtks5owybVZmXDo4Be+AwdvExdXayij80VI/+JVZieSTNp/ZXFKoSFElf 8A==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <vattunuru@marvell.com>, <jerinj@marvell.com>, <adwivedi@marvell.com>,\n <ndabilpuram@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v5 03/15] common/cnxk: add MACsec SC configuration APIs", "Date": "Wed, 14 Jun 2023 18:38:49 +0530", "Message-ID": "<20230614130901.3245809-4-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230614130901.3245809-1-gakhil@marvell.com>", "References": "<20230613102009.2390568-1-gakhil@marvell.com>\n <20230614130901.3245809-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Vaj3iWwEIPJnUk4M1uRVGTsgJchmSN7e", "X-Proofpoint-ORIG-GUID": "Vaj3iWwEIPJnUk4M1uRVGTsgJchmSN7e", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26\n definitions=2023-06-14_08,2023-06-14_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added ROC APIs to configure MACsec secure channel(SC)\nand its mapping with SAs for both Rx and Tx.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/roc_mbox.h | 37 ++++++\n drivers/common/cnxk/roc_mcs.h | 42 +++++++\n drivers/common/cnxk/roc_mcs_sec_cfg.c | 171 ++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 7 ++\n 4 files changed, 257 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex ab1173e805..40b761ee99 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -300,7 +300,10 @@ struct mbox_msghdr {\n \tM(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \\\n \t mcs_alloc_rsrc_rsp) \\\n \tM(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \\\n+\tM(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, msg_rsp) \\\n \tM(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \\\n+\tM(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \\\n+\tM(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \\\n \tM(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \\\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n@@ -726,6 +729,16 @@ struct mcs_free_rsrc_req {\n \tuint64_t __io rsvd;\n };\n \n+/* RX SC_CAM mapping */\n+struct mcs_rx_sc_cam_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io sci; /* SCI */\n+\tuint64_t __io secy_id; /* secy index mapped to SC */\n+\tuint8_t __io sc_id; /* SC CAM entry index */\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n struct mcs_sa_plcy_write_req {\n \tstruct mbox_msghdr hdr;\n \tuint64_t __io plcy[2][9]; /* Support 2 SA policy */\n@@ -736,6 +749,30 @@ struct mcs_sa_plcy_write_req {\n \tuint64_t __io rsvd;\n };\n \n+struct mcs_tx_sc_sa_map {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io sa_index0;\n+\tuint8_t __io sa_index1;\n+\tuint8_t __io rekey_ena;\n+\tuint8_t __io sa_index0_vld;\n+\tuint8_t __io sa_index1_vld;\n+\tuint8_t __io tx_sa_active;\n+\tuint64_t __io sectag_sci;\n+\tuint8_t __io sc_id; /* used as index for SA_MEM_MAP */\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_rx_sc_sa_map {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io sa_index;\n+\tuint8_t __io sa_in_use;\n+\tuint8_t __io sc_id;\n+\t/* an range is 0-3, sc_id + an used as index SA_MEM_MAP */\n+\tuint8_t __io an;\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n \n struct mcs_hw_info {\n \tstruct mbox_msghdr hdr;\ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nindex 6fda9308d7..1fb36b5eaa 100644\n--- a/drivers/common/cnxk/roc_mcs.h\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -32,6 +32,12 @@ struct roc_mcs_free_rsrc_req {\n \tuint8_t all; /* Free all the cam resources */\n };\n \n+/* RX SC_CAM mapping */\n+struct roc_mcs_rx_sc_cam_write_req {\n+\tuint64_t sci;\t /* SCI */\n+\tuint64_t secy_id; /* secy index mapped to SC */\n+\tuint8_t sc_id;\t /* SC CAM entry index */\n+};\n \n struct roc_mcs_sa_plcy_write_req {\n \tuint64_t plcy[2][9];\n@@ -40,6 +46,24 @@ struct roc_mcs_sa_plcy_write_req {\n \tuint8_t dir;\n };\n \n+struct roc_mcs_tx_sc_sa_map {\n+\tuint8_t sa_index0;\n+\tuint8_t sa_index1;\n+\tuint8_t rekey_ena;\n+\tuint8_t sa_index0_vld;\n+\tuint8_t sa_index1_vld;\n+\tuint8_t tx_sa_active;\n+\tuint64_t sectag_sci;\n+\tuint8_t sc_id; /* used as index for SA_MEM_MAP */\n+};\n+\n+struct roc_mcs_rx_sc_sa_map {\n+\tuint8_t sa_index;\n+\tuint8_t sa_in_use;\n+\tuint8_t sc_id;\n+\tuint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */\n+};\n+\n struct roc_mcs_hw_info {\n \tuint8_t num_mcs_blks; /* Number of MCS blocks */\n \tuint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */\n@@ -82,4 +106,22 @@ __roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs,\n __roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs,\n \t\t\t\t struct roc_mcs_sa_plcy_write_req *sa_plcy);\n \n+/* RX SC read, write and enable */\n+__roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n+__roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n+__roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n+/* RX SC-SA MAP read and write */\n+__roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map);\n+__roc_api int roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs,\n+\t\t\t\t\tstruct roc_mcs_rx_sc_sa_map *rx_sc_sa_map);\n+/* TX SC-SA MAP read and write */\n+__roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map);\n+__roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs,\n+\t\t\t\t\tstruct roc_mcs_tx_sc_sa_map *tx_sc_sa_map);\n+\n #endif /* ROC_MCS_H */\ndiff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c\nindex 041be51b4b..9b87952112 100644\n--- a/drivers/common/cnxk/roc_mcs_sec_cfg.c\n+++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c\n@@ -209,3 +209,174 @@ roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused,\n \n \treturn -ENOTSUP;\n }\n+\n+\n+int\n+roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_rx_sc_cam_write_req *rx_sc;\n+\tstruct msg_rsp *rsp;\n+\tint i, rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (rx_sc_cam == NULL)\n+\t\treturn -EINVAL;\n+\n+\trx_sc = mbox_alloc_msg_mcs_rx_sc_cam_write(mcs->mbox);\n+\tif (rx_sc == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trx_sc->sci = rx_sc_cam->sci;\n+\trx_sc->secy_id = rx_sc_cam->secy_id;\n+\trx_sc->sc_id = rx_sc_cam->sc_id;\n+\trx_sc->mcs_id = mcs->idx;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\tuint32_t set = plt_bitmap_get(priv->port_rsrc[i].secy_bmap, rx_sc_cam->secy_id);\n+\n+\t\tif (set) {\n+\t\t\tplt_bitmap_set(priv->port_rsrc[i].sc_bmap, rx_sc_cam->sc_id);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs __plt_unused,\n+\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_rx_sc_sa_map *sa_map;\n+\tstruct msg_rsp *rsp;\n+\tuint16_t sc_id;\n+\tint i, rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (rx_sc_sa_map == NULL)\n+\t\treturn -EINVAL;\n+\n+\tsc_id = rx_sc_sa_map->sc_id;\n+\tsa_map = mbox_alloc_msg_mcs_rx_sc_sa_map_write(mcs->mbox);\n+\tif (sa_map == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsa_map->sa_index = rx_sc_sa_map->sa_index;\n+\tsa_map->sa_in_use = rx_sc_sa_map->sa_in_use;\n+\tsa_map->sc_id = rx_sc_sa_map->sc_id;\n+\tsa_map->an = rx_sc_sa_map->an;\n+\tsa_map->mcs_id = mcs->idx;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\tuint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, sc_id);\n+\n+\t\tif (set) {\n+\t\t\tplt_bitmap_set(priv->port_rsrc[i].sa_bmap, rx_sc_sa_map->sa_index);\n+\t\t\tpriv->port_rsrc[i].sc_conf[sc_id].rx.sa_idx = rx_sc_sa_map->sa_index;\n+\t\t\tpriv->port_rsrc[i].sc_conf[sc_id].rx.an = rx_sc_sa_map->an;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_tx_sc_sa_map *sa_map;\n+\tstruct msg_rsp *rsp;\n+\tuint16_t sc_id;\n+\tint i, rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (tx_sc_sa_map == NULL)\n+\t\treturn -EINVAL;\n+\n+\tsa_map = mbox_alloc_msg_mcs_tx_sc_sa_map_write(mcs->mbox);\n+\tif (sa_map == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsa_map->sa_index0 = tx_sc_sa_map->sa_index0;\n+\tsa_map->sa_index1 = tx_sc_sa_map->sa_index1;\n+\tsa_map->rekey_ena = tx_sc_sa_map->rekey_ena;\n+\tsa_map->sa_index0_vld = tx_sc_sa_map->sa_index0_vld;\n+\tsa_map->sa_index1_vld = tx_sc_sa_map->sa_index1_vld;\n+\tsa_map->tx_sa_active = tx_sc_sa_map->tx_sa_active;\n+\tsa_map->sectag_sci = tx_sc_sa_map->sectag_sci;\n+\tsa_map->sc_id = tx_sc_sa_map->sc_id;\n+\tsa_map->mcs_id = mcs->idx;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tsc_id = tx_sc_sa_map->sc_id;\n+\tfor (i = 0; i < MAX_PORTS_PER_MCS; i++) {\n+\t\tuint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, sc_id + priv->sc_entries);\n+\n+\t\tif (set) {\n+\t\t\tuint32_t pos = priv->sa_entries + tx_sc_sa_map->sa_index0;\n+\n+\t\t\tplt_bitmap_set(priv->port_rsrc[i].sa_bmap, pos);\n+\t\t\tpriv->port_rsrc[i].sc_conf[sc_id].tx.sa_idx0 = tx_sc_sa_map->sa_index0;\n+\t\t\tpos = priv->sa_entries + tx_sc_sa_map->sa_index1;\n+\t\t\tplt_bitmap_set(priv->port_rsrc[i].sa_bmap, pos);\n+\t\t\tpriv->port_rsrc[i].sc_conf[sc_id].tx.sa_idx1 = tx_sc_sa_map->sa_index1;\n+\t\t\tpriv->port_rsrc[i].sc_conf[sc_id].tx.sci = tx_sc_sa_map->sectag_sci;\n+\t\t\tpriv->port_rsrc[i].sc_conf[sc_id].tx.rekey_enb = tx_sc_sa_map->rekey_ena;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex bd8a3095f9..dbfda62ad1 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -141,8 +141,15 @@ INTERNAL {\n \troc_mcs_hw_info_get;\n \troc_mcs_rsrc_alloc;\n \troc_mcs_rsrc_free;\n+\troc_mcs_rx_sc_cam_enable;\n+\troc_mcs_rx_sc_cam_read;\n+\troc_mcs_rx_sc_cam_write;\n+\troc_mcs_rx_sc_sa_map_read;\n+\troc_mcs_rx_sc_sa_map_write;\n \troc_mcs_sa_policy_read;\n \troc_mcs_sa_policy_write;\n+\troc_mcs_tx_sc_sa_map_read;\n+\troc_mcs_tx_sc_sa_map_write;\n \troc_nix_bpf_alloc;\n \troc_nix_bpf_config;\n \troc_nix_bpf_connect;\n", "prefixes": [ "v5", "03/15" ] }