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GET /api/patches/128863/?format=api
{ "id": 128863, "url": "http://patchwork.dpdk.org/api/patches/128863/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230620141115.841226-6-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230620141115.841226-6-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230620141115.841226-6-suanmingm@nvidia.com", "date": "2023-06-20T14:11:11", "name": "[v4,5/9] crypto/mlx5: add AES-GCM session configure", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "cfe41b9dbb9693dc0c3660ad404d5ccb0733bfcd", "submitter": { "id": 1887, "url": "http://patchwork.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230620141115.841226-6-suanmingm@nvidia.com/mbox/", "series": [ { "id": 28586, "url": "http://patchwork.dpdk.org/api/series/28586/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28586", "date": "2023-06-20T14:11:06", "name": "crypto/mlx5: support AES-GCM", "version": 4, "mbox": "http://patchwork.dpdk.org/series/28586/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/128863/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/128863/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C1A9742D09;\n\tTue, 20 Jun 2023 16:12:33 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0F5C842D53;\n\tTue, 20 Jun 2023 16:12:09 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2048.outbound.protection.outlook.com [40.107.92.48])\n by mails.dpdk.org (Postfix) with ESMTP id AAFA542C4D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<gakhil@marvell.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>", "CC": "<rasland@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v4 5/9] crypto/mlx5: add AES-GCM session configure", "Date": "Tue, 20 Jun 2023 17:11:11 +0300", "Message-ID": "<20230620141115.841226-6-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230620141115.841226-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>\n <20230620141115.841226-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000989E6:EE_|CY8PR12MB7635:EE_", "X-MS-Office365-Filtering-Correlation-Id": "aa837eb5-3873-469d-095d-08db71985335", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n MH/0o6RAkrHApnBLy5Z9WMnfHFbXl+LOAoWldPHCpLzatdOMUyn8Ek2hgLwbKMEP6nhxcWHhnXCbFhEJ3n9bk+BbDhxajsLEo2wjeYbVBItD81x9oxmN2c39ioI4ur3DhLY39gcxrbkUKlY/A/9EUbJOoOzBag3eVxk89+OmGEiYjYPhfk3tzlO0IFfXMox8B/QVDvSfYfvA7AjTXvq1N0NzQHc++CqXxCHc2sKQR+s5Jf8+pm9nGdyrWM9f/Qc9AuKgo6yabYKVWM5bM5CPWwhT6y5+0oCXY7bJDIi31mWys+bpaWNqChI5V9DNoA1/T5DxMGmVju2+VuXNZ2frrZhlYAxZYHM+2oDIo2hFu3OaLZiAqffEwsCQiX3jLIrv+hkw5B/zieiPTH63eFnOuUYXDMOZsy0leSeJDllUL3S7L5eCuzPmQsqyxdaZAYoCI6sopC4kl3m2ty0kZAbzKiwnbNkHtQi0/MnVfl+COQwbxBOMSKUr79AoLIQUfo4yG+R9hZ3w3iRRirD5ccKhPXnXuKGB1bCXdAbp/+p2bHTTbagAbeiSs7oSCvZeGxVcmlCwAcy9mogmJqq8OAqn7vO9yC7s8LzBiZY16x1Vnm+4+4oCB0/yCxakwgKrfkcB2e6ANrgt3bYEQ9DKn8qBKAZGPLMzgrjAdK2d+eY3a/IzIQefbkfl4op7mTsaAwh14Fa0pGOLFNhJfpLH6WtyoVNH2z0O9HzM77lC5DsdHxYeQrhI1eyLemxAukEae76E", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(376002)(136003)(39860400002)(396003)(346002)(451199021)(46966006)(36840700001)(40470700004)(40460700003)(5660300002)(2906002)(55016003)(40480700001)(82310400005)(8676002)(8936002)(7636003)(356005)(83380400001)(426003)(47076005)(36860700001)(36756003)(86362001)(82740400003)(6666004)(6636002)(4326008)(7696005)(70586007)(478600001)(70206006)(110136005)(54906003)(6286002)(186003)(26005)(16526019)(336012)(41300700001)(316002)(2616005)(1076003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jun 2023 14:12:04.7228 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n aa837eb5-3873-469d-095d-08db71985335", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000989E6.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY8PR12MB7635", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Sessions are used in symmetric transformations in order to prepare\nobjects and data for packet processing stage.\n\nThe AES-GCM session includes IV, AAD, digest(tag), DEK, operation\nmode information.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 12 +++++++\n drivers/crypto/mlx5/mlx5_crypto.h | 40 ++++++++++++++++++-----\n drivers/crypto/mlx5/mlx5_crypto_gcm.c | 47 +++++++++++++++++++++++++++\n 3 files changed, 91 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex e41b5b3528..96ce342d29 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -523,11 +523,23 @@ enum {\n \tMLX5_BLOCK_SIZE_4048B\t= 0x6,\n };\n \n+enum {\n+\tMLX5_ENCRYPTION_TYPE_AES_GCM = 0x3,\n+};\n+\n+enum {\n+\tMLX5_CRYPTO_OP_TYPE_ENCRYPTION = 0x0,\n+\tMLX5_CRYPTO_OP_TYPE_DECRYPTION = 0x1,\n+};\n+\n #define MLX5_BSF_SIZE_OFFSET\t\t30\n #define MLX5_BSF_P_TYPE_OFFSET\t\t24\n #define MLX5_ENCRYPTION_ORDER_OFFSET\t16\n #define MLX5_BLOCK_SIZE_OFFSET\t\t24\n \n+#define MLX5_CRYPTO_MMO_TYPE_OFFSET 24\n+#define MLX5_CRYPTO_MMO_OP_OFFSET 20\n+\n struct mlx5_wqe_umr_bsf_seg {\n \t/*\n \t * bs_bpt_eo_es contains:\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex bb5a557a38..6cb4d4ddec 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -72,16 +72,40 @@ struct mlx5_crypto_devarg_params {\n };\n \n struct mlx5_crypto_session {\n-\tuint32_t bs_bpt_eo_es;\n-\t/**< bsf_size, bsf_p_type, encryption_order and encryption standard,\n-\t * saved in big endian format.\n-\t */\n-\tuint32_t bsp_res;\n-\t/**< crypto_block_size_pointer and reserved 24 bits saved in big\n-\t * endian format.\n-\t */\n+\tunion {\n+\t\t/**< AES-XTS configuration. */\n+\t\tstruct {\n+\t\t\tuint32_t bs_bpt_eo_es;\n+\t\t\t/**< bsf_size, bsf_p_type, encryption_order and encryption standard,\n+\t\t\t * saved in big endian format.\n+\t\t\t */\n+\t\t\tuint32_t bsp_res;\n+\t\t\t/**< crypto_block_size_pointer and reserved 24 bits saved in big\n+\t\t\t * endian format.\n+\t\t\t */\n+\t\t};\n+\t\t/**< AES-GCM configuration. */\n+\t\tstruct {\n+\t\t\tuint32_t mmo_ctrl;\n+\t\t\t/**< Crypto control fields with algo type and op type in big\n+\t\t\t * endian format.\n+\t\t\t */\n+\t\t\tuint32_t wqe_aad_len;\n+\t\t\t/**< Crypto AAD length field in big endian format. */\n+\t\t\tuint32_t wqe_tag_len;\n+\t\t\t/**< Crypto tag length field in big endian format. */\n+\t\t\tuint16_t tag_len;\n+\t\t\t/**< AES-GCM crypto digest size in bytes. */\n+\t\t\tuint16_t aad_len;\n+\t\t\t/**< The length of the additional authenticated data (AAD) in bytes. */\n+\t\t\tuint32_t op_type;\n+\t\t\t/**< Operation type. */\n+\t\t};\n+\t};\n \tuint32_t iv_offset:16;\n \t/**< Starting point for Initialisation Vector. */\n+\tuint32_t iv_len;\n+\t/**< Initialisation Vector length. */\n \tstruct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */\n \tuint32_t dek_id; /**< DEK ID */\n } __rte_packed;\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\nindex 5b315ef42c..5f55314382 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n@@ -60,9 +60,56 @@ mlx5_crypto_dek_fill_gcm_attr(struct mlx5_crypto_dek *dek,\n \treturn 0;\n }\n \n+static int\n+mlx5_crypto_sym_gcm_session_configure(struct rte_cryptodev *dev,\n+\t\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\t\t\t struct rte_cryptodev_sym_session *session)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_session *sess_private_data = CRYPTODEV_GET_SYM_SESS_PRIV(session);\n+\tstruct rte_crypto_aead_xform *aead = &xform->aead;\n+\tuint32_t op_type;\n+\n+\tif (unlikely(xform->next != NULL)) {\n+\t\tDRV_LOG(ERR, \"Xform next is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif (aead->algo != RTE_CRYPTO_AEAD_AES_GCM) {\n+\t\tDRV_LOG(ERR, \"Only AES-GCM algorithm is supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif (aead->op == RTE_CRYPTO_AEAD_OP_ENCRYPT)\n+\t\top_type = MLX5_CRYPTO_OP_TYPE_ENCRYPTION;\n+\telse\n+\t\top_type = MLX5_CRYPTO_OP_TYPE_DECRYPTION;\n+\tsess_private_data->op_type = op_type;\n+\tsess_private_data->mmo_ctrl = rte_cpu_to_be_32\n+\t\t\t(op_type << MLX5_CRYPTO_MMO_OP_OFFSET |\n+\t\t\t MLX5_ENCRYPTION_TYPE_AES_GCM << MLX5_CRYPTO_MMO_TYPE_OFFSET);\n+\tsess_private_data->aad_len = aead->aad_length;\n+\tsess_private_data->tag_len = aead->digest_length;\n+\tsess_private_data->iv_offset = aead->iv.offset;\n+\tsess_private_data->iv_len = aead->iv.length;\n+\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, xform);\n+\tif (sess_private_data->dek == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to prepare dek.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tsess_private_data->dek_id =\n+\t\t\trte_cpu_to_be_32(sess_private_data->dek->obj->id &\n+\t\t\t\t\t 0xffffff);\n+\tDRV_LOG(DEBUG, \"Session %p was configured.\", sess_private_data);\n+\treturn 0;\n+}\n+\n int\n mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n {\n+\tstruct rte_cryptodev *crypto_dev = priv->crypto_dev;\n+\tstruct rte_cryptodev_ops *dev_ops = crypto_dev->dev_ops;\n+\n+\t/* Override AES-GCM specified ops. */\n+\tdev_ops->sym_session_configure = mlx5_crypto_sym_gcm_session_configure;\n \tpriv->caps = mlx5_crypto_gcm_caps;\n \treturn 0;\n }\n", "prefixes": [ "v4", "5/9" ] }