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GET /api/patches/128865/?format=api
{ "id": 128865, "url": "http://patchwork.dpdk.org/api/patches/128865/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230620141115.841226-8-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230620141115.841226-8-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230620141115.841226-8-suanmingm@nvidia.com", "date": "2023-06-20T14:11:13", "name": "[v4,7/9] crypto/mlx5: add queue pair setup for GCM", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7494ca993afd02489164bc7dd2c5eeed7c82a87d", "submitter": { "id": 1887, "url": "http://patchwork.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230620141115.841226-8-suanmingm@nvidia.com/mbox/", "series": [ { "id": 28586, "url": "http://patchwork.dpdk.org/api/series/28586/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28586", "date": "2023-06-20T14:11:06", "name": "crypto/mlx5: support AES-GCM", "version": 4, "mbox": "http://patchwork.dpdk.org/series/28586/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/128865/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/128865/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 00A3342D09;\n\tTue, 20 Jun 2023 16:12:50 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6E84442D65;\n\tTue, 20 Jun 2023 16:12:11 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2057.outbound.protection.outlook.com [40.107.223.57])\n by mails.dpdk.org (Postfix) with ESMTP id A505A42D51\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<gakhil@marvell.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>", "CC": "<rasland@nvidia.com>, <dev@dpdk.org>", "Subject": "[PATCH v4 7/9] crypto/mlx5: add queue pair setup for GCM", "Date": "Tue, 20 Jun 2023 17:11:13 +0300", "Message-ID": "<20230620141115.841226-8-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230620141115.841226-1-suanmingm@nvidia.com>", "References": "<20230418092325.2578712-1-suanmingm@nvidia.com>\n <20230620141115.841226-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000989E6:EE_|SJ0PR12MB7033:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9444b157-bc3e-445e-7622-08db71985404", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n CHfbc2DAd/qKJiRYqWL6Nl1rVM3yhuLMM7BpFzDZZI43AmUe96Ls2JMzFAC1y+RIZ5f9OxjUD7JhBLU2IU7V46VDZHE0yH2JeAsJdsklU7Par6WGqIVRkoYL6F+83xMYDvi+m2u5WzSuSY4b8TbLy+3xWDl/3WrkZXe1QL4GkVXUI3MYRlOV/7cX8tDHK4G+7WBdpHZAN6q66doOaZ2fAF9jOcZ4/yXiThRC4in+8n5BjveeOhCtw7hjuElBBB8Gl66DZkr6TAo0tju13WA1t4S0UdrnXaOGjKzTsdBt0MdelQlwjNmXk0JzScCP/RxRvvAaFYhuU5d9U5767nc6mpn4rQKfa/cLXY8Od2FjIWvJdBc8kzpiDrhB+7SFfQBr6EDdhPNaB9vD6NbPWLv14mxyz9PA+cwPL08jbrA+e1Fy28dIMBxornngkhYDUWY7I5P3i1M1P9LuxyFT5b6FbVfUNLSS+/y1swz2n5Z24SOWjxn5Nhbrto1U4hf1dWdnE7rLYIVBGgZxAN6s+LTZrjZTC/q2bPc1M30rb/xtzuqQJNZjaZDKhUhLoPUNXVnMqbWQX6iWVlAWw3VfCrNumUURb+fELtASiyWVhFUm8sTIWBBWq3xZjryLpsOQsX3uIXNNHO667hVwe9RM8ooN2cIIardzhlJvA8+Xn69nMWxK7kOZ5hhbpR8hK6gWCCifeNfLb60WHoPsE6xykSPiAt7iww+U9WpTUetohrKj10eGMaJy/Vmfeinp38lEVpLK", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(346002)(39860400002)(136003)(396003)(376002)(451199021)(40470700004)(36840700001)(46966006)(5660300002)(356005)(8936002)(82310400005)(86362001)(8676002)(82740400003)(7636003)(316002)(30864003)(41300700001)(336012)(6636002)(4326008)(70586007)(36860700001)(70206006)(47076005)(54906003)(426003)(83380400001)(2616005)(110136005)(186003)(36756003)(478600001)(6286002)(16526019)(1076003)(26005)(40460700003)(7696005)(2906002)(40480700001)(6666004)(55016003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jun 2023 14:12:06.0665 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9444b157-bc3e-445e-7622-08db71985404", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000989E6.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ0PR12MB7033", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Crypto queue pair is for handling the encryption/decryption operations.\n\nAs AES-GCM AEAD API provides AAD, mbuf, digest separately, low-level FW\nonly accepts the data in a single contiguous memory region, two internal\nQPs are created for AES-GCM queue pair. One for organizing the memory\nto be contiguous if they are not. The other is for crypto.\n\nIf the buffers are checked as implicitly contiguous, the buffer will be\nsent to the crypto QP directly for encryption/decryption. If not, the\nbuffers will be handled by the first UMR QP. The UMR QP will convert\nthe buffers to be contiguous one. Then the well organized \"new\" buffer\ncan be handled by crypto QP.\n\nThe crypto QP is initialized as follower, and UMR as leader. Once\ncrypto operation input buffer requires memory address space converting\nby UMR QP, the crypto QP processing will be triggered by UMR QP.\nOtherwise, the ring crypto QP doorbell directly.\n\nThe existing max_segs_num devarg is used for define how many segments\nthe chained mbuf contains same as AES-XTS before.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common_mr.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 22 +++\n drivers/common/mlx5/version.map | 2 +\n drivers/crypto/mlx5/mlx5_crypto.h | 15 ++\n drivers/crypto/mlx5/mlx5_crypto_gcm.c | 230 ++++++++++++++++++++++++++\n 5 files changed, 270 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common_mr.h b/drivers/common/mlx5/mlx5_common_mr.h\nindex 66623868a2..8789d403b1 100644\n--- a/drivers/common/mlx5/mlx5_common_mr.h\n+++ b/drivers/common/mlx5/mlx5_common_mr.h\n@@ -254,6 +254,7 @@ __rte_internal\n void\n mlx5_common_verbs_dereg_mr(struct mlx5_pmd_mr *pmd_mr);\n \n+__rte_internal\n void\n mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, mlx5_dereg_mr_t *dereg_mr_cb);\n \ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 4990bcaacd..4f6925733a 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -470,6 +470,15 @@ struct mlx5_wqe_rseg {\n #define MLX5_UMRC_KO_OFFSET 16u\n #define MLX5_UMRC_TO_BS_OFFSET 0u\n \n+/*\n+ * As PRM describes, the address of the UMR pointer must be\n+ * aligned to 2KB.\n+ */\n+#define MLX5_UMR_KLM_PTR_ALIGN (1 << 11)\n+\n+#define MLX5_UMR_KLM_NUM_ALIGN \\\n+\t(MLX5_UMR_KLM_PTR_ALIGN / sizeof(struct mlx5_klm))\n+\n struct mlx5_wqe_umr_cseg {\n \tuint32_t if_cf_toe_cq_res;\n \tuint32_t ko_to_bs;\n@@ -674,6 +683,19 @@ union mlx5_gga_compress_opaque {\n \tuint32_t data[64];\n };\n \n+union mlx5_gga_crypto_opaque {\n+\tstruct {\n+\t\tuint32_t syndrome;\n+\t\tuint32_t reserved0[2];\n+\t\tstruct {\n+\t\t\tuint32_t iv[3];\n+\t\t\tuint32_t tag_size;\n+\t\t\tuint32_t aad_size;\n+\t\t} cp __rte_packed;\n+\t} __rte_packed;\n+\tuint8_t data[64];\n+};\n+\n struct mlx5_ifc_regexp_mmo_control_bits {\n \tuint8_t reserved_at_31[0x2];\n \tuint8_t le[0x1];\ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex f860b069de..0758ba76de 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -159,5 +159,7 @@ INTERNAL {\n \n \tmlx5_os_interrupt_handler_create; # WINDOWS_NO_EXPORT\n \tmlx5_os_interrupt_handler_destroy; # WINDOWS_NO_EXPORT\n+\n+\tmlx5_os_set_reg_mr_cb;\n \tlocal: *;\n };\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 6cb4d4ddec..88a09a6b1c 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -28,8 +28,11 @@ struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\n \tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\n \tstruct rte_cryptodev *crypto_dev;\n+\tmlx5_reg_mr_t reg_mr_cb; /* Callback to reg_mr func */\n+\tmlx5_dereg_mr_t dereg_mr_cb; /* Callback to dereg_mr func */\n \tstruct mlx5_uar uar; /* User Access Region. */\n \tuint32_t max_segs_num; /* Maximum supported data segs. */\n+\tuint32_t max_klm_num; /* Maximum supported klm. */\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n \tconst struct rte_cryptodev_capabilities *caps;\n \tstruct rte_cryptodev_config dev_config;\n@@ -46,15 +49,27 @@ struct mlx5_crypto_qp {\n \tstruct mlx5_crypto_priv *priv;\n \tstruct mlx5_devx_cq cq_obj;\n \tstruct mlx5_devx_qp qp_obj;\n+\tstruct mlx5_devx_qp umr_qp_obj;\n \tstruct rte_cryptodev_stats stats;\n \tstruct rte_crypto_op **ops;\n \tstruct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */\n+\tstruct mlx5_klm *klm_array;\n+\tunion mlx5_gga_crypto_opaque *opaque_addr;\n \tstruct mlx5_mr_ctrl mr_ctrl;\n+\tstruct mlx5_pmd_mr mr;\n+\t/* Crypto QP. */\n \tuint8_t *wqe;\n \tuint16_t entries_n;\n+\tuint16_t cq_entries_n;\n \tuint16_t pi;\n \tuint16_t ci;\n \tuint16_t db_pi;\n+\t/* UMR QP. */\n+\tuint8_t *umr_wqe;\n+\tuint16_t umr_wqbbs;\n+\tuint16_t umr_pi;\n+\tuint16_t umr_ci;\n+\tuint32_t umr_errors;\n };\n \n struct mlx5_crypto_dek {\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\nindex 5f55314382..c3859547ee 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c\n@@ -18,6 +18,20 @@\n #include \"mlx5_crypto_utils.h\"\n #include \"mlx5_crypto.h\"\n \n+/*\n+ * AES-GCM uses indirect KLM mode. The UMR WQE comprises of WQE control +\n+ * UMR control + mkey context + indirect KLM. The WQE size is aligned to\n+ * be 3 WQEBBS.\n+ */\n+#define MLX5_UMR_GCM_WQE_SIZE \\\n+\t(RTE_ALIGN(sizeof(struct mlx5_umr_wqe) + sizeof(struct mlx5_wqe_dseg), \\\n+\t\t\tMLX5_SEND_WQE_BB))\n+\n+#define MLX5_UMR_GCM_WQE_SET_SIZE \\\n+\t(MLX5_UMR_GCM_WQE_SIZE + \\\n+\t RTE_ALIGN(sizeof(struct mlx5_wqe_send_en_wqe), \\\n+\t MLX5_SEND_WQE_BB))\n+\n static struct rte_cryptodev_capabilities mlx5_crypto_gcm_caps[] = {\n \t{\n \t\t.op = RTE_CRYPTO_OP_TYPE_UNDEFINED,\n@@ -86,6 +100,8 @@ mlx5_crypto_sym_gcm_session_configure(struct rte_cryptodev *dev,\n \tsess_private_data->mmo_ctrl = rte_cpu_to_be_32\n \t\t\t(op_type << MLX5_CRYPTO_MMO_OP_OFFSET |\n \t\t\t MLX5_ENCRYPTION_TYPE_AES_GCM << MLX5_CRYPTO_MMO_TYPE_OFFSET);\n+\tsess_private_data->wqe_aad_len = rte_cpu_to_be_32((uint32_t)aead->aad_length);\n+\tsess_private_data->wqe_tag_len = rte_cpu_to_be_32((uint32_t)aead->digest_length);\n \tsess_private_data->aad_len = aead->aad_length;\n \tsess_private_data->tag_len = aead->digest_length;\n \tsess_private_data->iv_offset = aead->iv.offset;\n@@ -102,6 +118,216 @@ mlx5_crypto_sym_gcm_session_configure(struct rte_cryptodev *dev,\n \treturn 0;\n }\n \n+static void *\n+mlx5_crypto_gcm_mkey_klm_update(struct mlx5_crypto_priv *priv,\n+\t\t\t\tstruct mlx5_crypto_qp *qp __rte_unused,\n+\t\t\t\tuint32_t idx)\n+{\n+\treturn &qp->klm_array[idx * priv->max_klm_num];\n+}\n+\n+static int\n+mlx5_crypto_gcm_qp_release(struct rte_cryptodev *dev, uint16_t qp_id)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\tif (qp->umr_qp_obj.qp != NULL)\n+\t\tmlx5_devx_qp_destroy(&qp->umr_qp_obj);\n+\tif (qp->qp_obj.qp != NULL)\n+\t\tmlx5_devx_qp_destroy(&qp->qp_obj);\n+\tif (qp->cq_obj.cq != NULL)\n+\t\tmlx5_devx_cq_destroy(&qp->cq_obj);\n+\tif (qp->mr.obj != NULL) {\n+\t\tvoid *opaq = qp->mr.addr;\n+\n+\t\tpriv->dereg_mr_cb(&qp->mr);\n+\t\trte_free(opaq);\n+\t}\n+\tmlx5_crypto_indirect_mkeys_release(qp, qp->entries_n);\n+\tmlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);\n+\trte_free(qp);\n+\tdev->data->queue_pairs[qp_id] = NULL;\n+\treturn 0;\n+}\n+\n+static void\n+mlx5_crypto_gcm_init_qp(struct mlx5_crypto_qp *qp)\n+{\n+\tvolatile struct mlx5_gga_wqe *restrict wqe =\n+\t\t\t\t (volatile struct mlx5_gga_wqe *)qp->qp_obj.wqes;\n+\tvolatile union mlx5_gga_crypto_opaque *opaq = qp->opaque_addr;\n+\tconst uint32_t sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | 4u);\n+\tconst uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n+\t\t\t\t\tMLX5_COMP_MODE_OFFSET);\n+\tconst uint32_t opaq_lkey = rte_cpu_to_be_32(qp->mr.lkey);\n+\tint i;\n+\n+\t/* All the next fields state should stay constant. */\n+\tfor (i = 0; i < qp->entries_n; ++i, ++wqe) {\n+\t\twqe->sq_ds = sq_ds;\n+\t\twqe->flags = flags;\n+\t\twqe->opaque_lkey = opaq_lkey;\n+\t\twqe->opaque_vaddr = rte_cpu_to_be_64((uint64_t)(uintptr_t)&opaq[i]);\n+\t}\n+}\n+\n+static inline int\n+mlx5_crypto_gcm_umr_qp_setup(struct rte_cryptodev *dev, struct mlx5_crypto_qp *qp,\n+\t\t\t int socket_id)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_devx_qp_attr attr = {0};\n+\tuint32_t ret;\n+\tuint32_t log_wqbb_n;\n+\n+\t/* Set UMR + SEND_EN WQE as maximum same with crypto. */\n+\tlog_wqbb_n = rte_log2_u32(qp->entries_n *\n+\t\t\t(MLX5_UMR_GCM_WQE_SET_SIZE / MLX5_SEND_WQE_BB));\n+\tattr.pd = priv->cdev->pdn;\n+\tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj);\n+\tattr.cqn = qp->cq_obj.cq->id;\n+\tattr.num_of_receive_wqes = 0;\n+\tattr.num_of_send_wqbbs = RTE_BIT32(log_wqbb_n);\n+\tattr.ts_format =\n+\t\tmlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);\n+\tattr.cd_master = 1;\n+\tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->umr_qp_obj,\n+\t\t\t\t attr.num_of_send_wqbbs * MLX5_SEND_WQE_BB,\n+\t\t\t\t &attr, socket_id);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to create UMR QP.\");\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_qp2rts(&qp->umr_qp_obj, qp->umr_qp_obj.qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to change UMR QP state to RTS.\");\n+\t\treturn -1;\n+\t}\n+\t/* Save the UMR WQEBBS for checking the WQE boundary. */\n+\tqp->umr_wqbbs = attr.num_of_send_wqbbs;\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_gcm_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\t\t const struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t\t int socket_id)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hca_attr *attr = &priv->cdev->config.hca_attr;\n+\tstruct mlx5_crypto_qp *qp;\n+\tstruct mlx5_devx_cq_attr cq_attr = {\n+\t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj),\n+\t};\n+\tstruct mlx5_devx_qp_attr qp_attr = {\n+\t\t.pd = priv->cdev->pdn,\n+\t\t.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj),\n+\t\t.user_index = qp_id,\n+\t};\n+\tstruct mlx5_devx_mkey_attr mkey_attr = {\n+\t\t.pd = priv->cdev->pdn,\n+\t\t.umr_en = 1,\n+\t\t.klm_num = priv->max_klm_num,\n+\t};\n+\tuint32_t log_ops_n = rte_log2_u32(qp_conf->nb_descriptors);\n+\tuint32_t entries = RTE_BIT32(log_ops_n);\n+\tuint32_t alloc_size = sizeof(*qp);\n+\tsize_t mr_size, opaq_size;\n+\tvoid *mr_buf;\n+\tint ret;\n+\n+\talloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);\n+\talloc_size += (sizeof(struct rte_crypto_op *) +\n+\t\t sizeof(struct mlx5_devx_obj *)) * entries;\n+\tqp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,\n+\t\t\t\tsocket_id);\n+\tif (qp == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate qp memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tqp->priv = priv;\n+\tqp->entries_n = entries;\n+\tif (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen,\n+\t\t\t\t priv->dev_config.socket_id)) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate MR Btree for qp %u.\",\n+\t\t\t(uint32_t)qp_id);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\t/*\n+\t * The following KLM pointer must be aligned with\n+\t * MLX5_UMR_KLM_PTR_ALIGN. Aligned opaq_size here\n+\t * to make the KLM pointer with offset be aligned.\n+\t */\n+\topaq_size = RTE_ALIGN(sizeof(union mlx5_gga_crypto_opaque) * entries,\n+\t\t\t MLX5_UMR_KLM_PTR_ALIGN);\n+\tmr_size = (priv->max_klm_num * sizeof(struct mlx5_klm) * entries) + opaq_size;\n+\tmr_buf = rte_calloc(__func__, (size_t)1, mr_size, MLX5_UMR_KLM_PTR_ALIGN);\n+\tif (mr_buf == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate mr memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\tif (priv->reg_mr_cb(priv->cdev->pd, mr_buf, mr_size, &qp->mr) != 0) {\n+\t\trte_free(mr_buf);\n+\t\tDRV_LOG(ERR, \"Failed to register opaque MR.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\tqp->opaque_addr = qp->mr.addr;\n+\tqp->klm_array = RTE_PTR_ADD(qp->opaque_addr, opaq_size);\n+\t/*\n+\t * Triple the CQ size as UMR QP which contains UMR and SEND_EN WQE\n+\t * will share this CQ .\n+\t */\n+\tqp->cq_entries_n = rte_align32pow2(entries * 3);\n+\tret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq_obj,\n+\t\t\t\t rte_log2_u32(qp->cq_entries_n),\n+\t\t\t\t &cq_attr, socket_id);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n+\t\tgoto err;\n+\t}\n+\tqp_attr.cqn = qp->cq_obj.cq->id;\n+\tqp_attr.ts_format = mlx5_ts_format_conv(attr->qp_ts_format);\n+\tqp_attr.num_of_receive_wqes = 0;\n+\tqp_attr.num_of_send_wqbbs = entries;\n+\tqp_attr.mmo = attr->crypto_mmo.crypto_mmo_qp;\n+\t/* Set MMO QP as follower as the input data may depend on UMR. */\n+\tqp_attr.cd_slave_send = 1;\n+\tret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj,\n+\t\t\t\t qp_attr.num_of_send_wqbbs * MLX5_WQE_SIZE,\n+\t\t\t\t &qp_attr, socket_id);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create QP.\");\n+\t\tgoto err;\n+\t}\n+\tmlx5_crypto_gcm_init_qp(qp);\n+\tret = mlx5_devx_qp2rts(&qp->qp_obj, 0);\n+\tif (ret)\n+\t\tgoto err;\n+\tqp->ops = (struct rte_crypto_op **)(qp + 1);\n+\tqp->mkey = (struct mlx5_devx_obj **)(qp->ops + entries);\n+\tif (mlx5_crypto_gcm_umr_qp_setup(dev, qp, socket_id)) {\n+\t\tDRV_LOG(ERR, \"Failed to setup UMR QP.\");\n+\t\tgoto err;\n+\t}\n+\tDRV_LOG(INFO, \"QP %u: SQN=0x%X CQN=0x%X entries num = %u\",\n+\t\t(uint32_t)qp_id, qp->qp_obj.qp->id, qp->cq_obj.cq->id, entries);\n+\tif (mlx5_crypto_indirect_mkeys_prepare(priv, qp, &mkey_attr,\n+\t\t\t\t\t mlx5_crypto_gcm_mkey_klm_update)) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate indirect memory regions.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto err;\n+\t}\n+\tdev->data->queue_pairs[qp_id] = qp;\n+\treturn 0;\n+err:\n+\tmlx5_crypto_gcm_qp_release(dev, qp_id);\n+\treturn -1;\n+}\n+\n int\n mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n {\n@@ -110,6 +336,10 @@ mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv)\n \n \t/* Override AES-GCM specified ops. */\n \tdev_ops->sym_session_configure = mlx5_crypto_sym_gcm_session_configure;\n+\tmlx5_os_set_reg_mr_cb(&priv->reg_mr_cb, &priv->dereg_mr_cb);\n+\tdev_ops->queue_pair_setup = mlx5_crypto_gcm_qp_setup;\n+\tdev_ops->queue_pair_release = mlx5_crypto_gcm_qp_release;\n+\tpriv->max_klm_num = RTE_ALIGN((priv->max_segs_num + 1) * 2 + 1, MLX5_UMR_KLM_NUM_ALIGN);\n \tpriv->caps = mlx5_crypto_gcm_caps;\n \treturn 0;\n }\n", "prefixes": [ "v4", "7/9" ] }