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GET /api/patches/129017/?format=api
{ "id": 129017, "url": "http://patchwork.dpdk.org/api/patches/129017/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230627082746.2466304-2-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230627082746.2466304-2-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230627082746.2466304-2-dsosnowski@nvidia.com", "date": "2023-06-27T08:27:45", "name": "[1/2] net/mlx5: fix queue used to deallocate counter", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d877ac3bb4c2f73dad3b704f83b946c8d7b556aa", "submitter": { "id": 2386, "url": "http://patchwork.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230627082746.2466304-2-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 28661, "url": "http://patchwork.dpdk.org/api/series/28661/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28661", "date": "2023-06-27T08:27:44", "name": "net/mlx5: fix counter object leaks", "version": 1, "mbox": "http://patchwork.dpdk.org/series/28661/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129017/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/129017/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8755E42D70;\n\tTue, 27 Jun 2023 10:28:29 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7A58042BC9;\n\tTue, 27 Jun 2023 10:28:29 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2076.outbound.protection.outlook.com [40.107.243.76])\n by mails.dpdk.org (Postfix) with ESMTP id C08F642B8B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 1/2] net/mlx5: fix queue used to deallocate counter", "Date": "Tue, 27 Jun 2023 11:27:45 +0300", "Message-ID": "<20230627082746.2466304-2-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230627082746.2466304-1-dsosnowski@nvidia.com>", "References": "<20230627082746.2466304-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT060:EE_|DM6PR12MB4354:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0b8f7b50-c5ac-48a8-861b-08db76e87a56", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n gwY7TFSz8KRm+BsjQFzpl/irnU3rO6F3cuTF8qZhRtBCqIxQG5WY6Sfs3XLI8rTWp7LMsmAzkDDGRtQWBv8NoLln8imsTcnEmuDah6B5pdzllPr2neH2NinO2J4prmqCDJ8KyUQUiu+TJxwI1Hx7Vf2Tw9BdaWx3yni1MlD+7WpU1SulTSYcSFv/duQlNkK5j8zT8NzsDp8xBD/uX2zMiCn10GwXc/+KtpvgIoRbvqICYBeaNPGVjTdQGGtvXde+M4gl0UWyhVlyWagk78FQsCSdG3w4tcGaKhLfDDv0Ki2yB9PKgjt0r2hpDyUIYgyzatbCBRWJUvNXK1Jysa7jN55wY4JbQQoRCtLykRX1PCaLmhSLmPSwrKejfXx/OSS3e1spTjmhgwoMkFHCyzDZo45bmwm8bWn4G4xrhM6B1GuYBaGGGz0UlJXszb62Zq/pyUMjMwxdYnyIY48792SgVSegb2WaQaGgGjz3/sycnFn1bZ5gP6XnHQCM2X6ez1yL3WRN+80kW5Uk0dzU9WfeT50TiT7U7S3vjwhIK9rDJ9vK6woJ5DmsiPbQxStL/o7Kyxs9caAjjBUTx8hlFduE8Z4mrjVJGQfkT03y7EMzzidKNXZf0gCxaVLMbGxE5IfmK3ZVzqnwvFsXHFG+FdVTAq9pMrIBoJRtM52aWbp/9KhVkXKvgn0DXQ0zG5vJK93bOG9lJnuBtGuxSf62tte8nnPVUGf9V5ZGUHPl3/XTHbZerFICeTquIJAFRU1lRe4x", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(346002)(136003)(396003)(376002)(39860400002)(451199021)(46966006)(40470700004)(36840700001)(6286002)(110136005)(40480700001)(478600001)(55016003)(7696005)(40460700003)(26005)(1076003)(6666004)(4326008)(82310400005)(5660300002)(2906002)(36756003)(6636002)(70586007)(70206006)(86362001)(8936002)(83380400001)(41300700001)(8676002)(316002)(36860700001)(336012)(426003)(47076005)(186003)(82740400003)(2616005)(16526019)(7636003)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Jun 2023 08:28:25.8475 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0b8f7b50-c5ac-48a8-861b-08db76e87a56", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT060.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4354", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "When ports are configured to share flow engine resources\n(configured through rte_flow_configure()),\ncounter objects used during flow rule creation are pulled\ndirectly from the shared counter pool.\nThis is done by calling mlx5_hws_cnt_pool_get() with NULL pointer\npassed as queue pointer.\n\nWhen a flow rule was destroyed on the host port,\ncounter object was not returned to the pool, because\nmlx5_hws_cnt_pool_put() was always called with a pointer\nto the currently used queue.\nThis forced placing the counter in the local queue cache.\nAs a result, during the application runtime, some counter objects\nbecame inaccessible, since this queue is never fully flushed.\n\nThis patch fixes that behavior, by changing the flow rule destroying\nlogic. If port is configured to use shared resources,\nmlx5_hws_cnt_pool_put() is called with NULL pointer\npassed as queue pointer.\n\nFixes: 13ea6bdcc7ee (\"net/mlx5: support counters in cross port shared mode\")\nCc: viacheslavo@nvidia.com\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_hw.c | 14 +++++++++-----\n drivers/net/mlx5/mlx5_hws_cnt.h | 16 ++++++++++++++++\n 2 files changed, 25 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex b5137a822a..a0c7956626 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2273,6 +2273,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\tstruct mlx5_hrxq *hrxq;\n \t\tuint32_t ct_idx;\n \t\tcnt_id_t cnt_id;\n+\t\tuint32_t *cnt_queue;\n \t\tuint32_t mtr_id;\n \n \t\taction = &actions[act_data->action_src];\n@@ -2429,10 +2430,9 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\tbreak;\n \t\t\t/* Fall-through. */\n \t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n-\t\t\tret = mlx5_hws_cnt_pool_get(priv->hws_cpool,\n-\t\t\t\t\t(priv->shared_refcnt ||\n-\t\t\t\t\t priv->hws_cpool->cfg.host_cpool) ?\n-\t\t\t\t\tNULL : &queue, &cnt_id, age_idx);\n+\t\t\t/* If the port is engaged in resource sharing, do not use queue cache. */\n+\t\t\tcnt_queue = mlx5_hws_cnt_is_pool_shared(priv) ? NULL : &queue;\n+\t\t\tret = mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &cnt_id, age_idx);\n \t\t\tif (ret != 0)\n \t\t\t\treturn ret;\n \t\t\tret = mlx5_hws_cnt_pool_get_action_offset\n@@ -3014,6 +3014,8 @@ flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,\n \t\t\t struct rte_flow_hw *flow,\n \t\t\t struct rte_flow_error *error)\n {\n+\tuint32_t *cnt_queue;\n+\n \tif (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {\n \t\tif (flow->age_idx && !mlx5_hws_age_is_indirect(flow->age_idx)) {\n \t\t\t/* Remove this AGE parameter from indirect counter. */\n@@ -3024,8 +3026,10 @@ flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,\n \t\t}\n \t\treturn;\n \t}\n+\t/* If the port is engaged in resource sharing, do not use queue cache. */\n+\tcnt_queue = mlx5_hws_cnt_is_pool_shared(priv) ? NULL : &queue;\n \t/* Put the counter first to reduce the race risk in BG thread. */\n-\tmlx5_hws_cnt_pool_put(priv->hws_cpool, &queue, &flow->cnt_id);\n+\tmlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);\n \tflow->cnt_id = 0;\n \tif (flow->age_idx) {\n \t\tif (mlx5_hws_age_is_indirect(flow->age_idx)) {\ndiff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h\nindex b4f3db0533..f37a7d6151 100644\n--- a/drivers/net/mlx5/mlx5_hws_cnt.h\n+++ b/drivers/net/mlx5/mlx5_hws_cnt.h\n@@ -553,6 +553,22 @@ mlx5_hws_cnt_pool_get(struct mlx5_hws_cnt_pool *cpool, uint32_t *queue,\n \treturn 0;\n }\n \n+/**\n+ * Check if counter pool allocated for HWS is shared between ports.\n+ *\n+ * @param[in] priv\n+ * Pointer to the port private data structure.\n+ *\n+ * @return\n+ * True if counter pools is shared between ports. False otherwise.\n+ */\n+static __rte_always_inline bool\n+mlx5_hws_cnt_is_pool_shared(struct mlx5_priv *priv)\n+{\n+\treturn priv && priv->hws_cpool &&\n+\t (priv->shared_refcnt || priv->hws_cpool->cfg.host_cpool != NULL);\n+}\n+\n static __rte_always_inline unsigned int\n mlx5_hws_cnt_pool_get_size(struct mlx5_hws_cnt_pool *cpool)\n {\n", "prefixes": [ "1/2" ] }