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GET /api/patches/129198/?format=api
{ "id": 129198, "url": "http://patchwork.dpdk.org/api/patches/129198/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230702045758.23244-5-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230702045758.23244-5-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230702045758.23244-5-igozlan@nvidia.com", "date": "2023-07-02T04:57:58", "name": "[v2,5/5] net/mlx5/hws: support default miss action on FDB", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "9f4ce0c9b4463fd0404ed191ed4f75f12e2ba776", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230702045758.23244-5-igozlan@nvidia.com/mbox/", "series": [ { "id": 28775, "url": "http://patchwork.dpdk.org/api/series/28775/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28775", "date": "2023-07-02T04:57:54", "name": "[v2,1/5] net/mlx5: support indirect list METER_MARK action", "version": 2, "mbox": "http://patchwork.dpdk.org/series/28775/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129198/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/129198/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0D14542DA8;\n\tMon, 3 Jul 2023 11:21:32 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id ED38E42D29;\n\tMon, 3 Jul 2023 11:21:17 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2067.outbound.protection.outlook.com [40.107.92.67])\n by mails.dpdk.org (Postfix) with ESMTP id 94A4C40DFD\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Itamar Gozlan <igozlan@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <matan@nvidia.com>,\n <thomas@monjalon.net>, <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v2 5/5] net/mlx5/hws: support default miss action on FDB", "Date": "Sun, 2 Jul 2023 07:57:58 +0300", "Message-ID": "<20230702045758.23244-5-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20230702045758.23244-1-igozlan@nvidia.com>", "References": "<20230629072125.20369-5-igozlan@nvidia.com>\n <20230702045758.23244-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT088:EE_|CH2PR12MB4890:EE_", "X-MS-Office365-Filtering-Correlation-Id": "11d8b1ed-270b-48cb-a9b3-08db7ab8fbdc", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 0rA+khJog3yQeJhc76J9jPStumVGJdaWoeHzsp7puXx/YMSz9zGwjyeD4iFpYtIIy2VXsBsVUCjEJNSGh29jke0+ip3HYPerCcMFzzRdep6byNgwJs4TsCtsoCjibT5PV4EXdS6GJBGxev8CqYnAqFxqRZ2/NbBMUQLZv0ryfnWhD78nl+CBph1uag/XvoDgYNbMo79EIDcsVYsdRU37djXYcAasRSUmY9W6Us1rJJuT/aANC0iKJDEBkn00EI58lDiiYxd/CJm+nFNDRv+fXt7jQ8knBZGlnCFdyHQ9AAqYeHA1IhnzKj3R/c13002xIuN8ODZ8rnliSVtQiu/iq4jZVMLEjdP7nhnAEe2hdBSZWmJ1u6XbWBOEREkjDnS1b9V/k2nhjNzY4T+8gZcm1k1d2kiF+KDAsSyFvzsC2AuvBDUYzmg6YC3NuWupKZMOmJibYSSzZyBQP+NcdLLDDbX2hccQr3vnZ0XpEESyenYk04HJ5V9ExJH09c4HUwh4UTEptlr8YlLNjnhaJCuvOJ7nQgHIE1UcgefShsoKMMQO8tYz7FmBHXoEKJ8N0C+X0vzvTgJrRRYRyjDISguBQBuBFjnVTc2cbTKD1hXWyI3oygkPaJRY0mQAzslWRaLtbe+uxTMgzNJx5np5BdGTafqmRvfJ78xeiuEHD8O6HIBKev8EcjJWizgZ8F3EYZLUqGJCyowYDWkSTTm6BhuD0rG3WI8fpN4wmbae9E+tNHFcD9IFRShuVGHHOcFSNUAL", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(136003)(346002)(376002)(396003)(39860400002)(451199021)(40470700004)(46966006)(36840700001)(107886003)(26005)(478600001)(1076003)(82740400003)(6666004)(86362001)(2616005)(186003)(6286002)(36860700001)(7636003)(54906003)(6636002)(70586007)(4326008)(83380400001)(356005)(336012)(110136005)(426003)(7696005)(70206006)(316002)(47076005)(5660300002)(8676002)(8936002)(40460700003)(41300700001)(2906002)(40480700001)(55016003)(82310400005)(36756003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Jul 2023 04:58:31.9608 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 11d8b1ed-270b-48cb-a9b3-08db7ab8fbdc", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT088.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB4890", "X-Mailman-Approved-At": "Mon, 03 Jul 2023 11:21:13 +0200", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Alex Vesker <valex@nvidia.com>\n\nAdd the support for default miss on HWS FDB, this implementation\nwas missing until now. Default miss can be used for more efficient\nmiss flow instead of going to an empty matcher or some defecated\nempty table.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_action.c | 27 ++++++++++++++++++++-------\n drivers/net/mlx5/hws/mlx5dr_table.c | 8 ++------\n 2 files changed, 22 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c\nindex a514b82fec..96c0c10cd9 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_action.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_action.c\n@@ -327,10 +327,12 @@ int mlx5dr_action_root_build_attr(struct mlx5dr_rule_action rule_actions[],\n \treturn 0;\n }\n \n-static bool mlx5dr_action_fixup_stc_attr(struct mlx5dr_cmd_stc_modify_attr *stc_attr,\n-\t\t\t\t\t struct mlx5dr_cmd_stc_modify_attr *fixup_stc_attr,\n-\t\t\t\t\t enum mlx5dr_table_type table_type,\n-\t\t\t\t\t bool is_mirror)\n+static bool\n+mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_cmd_stc_modify_attr *stc_attr,\n+\t\t\t struct mlx5dr_cmd_stc_modify_attr *fixup_stc_attr,\n+\t\t\t enum mlx5dr_table_type table_type,\n+\t\t\t bool is_mirror)\n {\n \tstruct mlx5dr_devx_obj *devx_obj;\n \tbool use_fixup = false;\n@@ -353,6 +355,17 @@ static bool mlx5dr_action_fixup_stc_attr(struct mlx5dr_cmd_stc_modify_attr *stc_\n \t\tuse_fixup = true;\n \t\tbreak;\n \n+\tcase MLX5_IFC_STC_ACTION_TYPE_ALLOW:\n+\t\tif (fw_tbl_type == FS_FT_FDB_TX || fw_tbl_type == FS_FT_FDB_RX) {\n+\t\t\tfixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT;\n+\t\t\tfixup_stc_attr->action_offset = stc_attr->action_offset;\n+\t\t\tfixup_stc_attr->stc_offset = stc_attr->stc_offset;\n+\t\t\tfixup_stc_attr->vport.esw_owner_vhca_id = ctx->caps->vhca_id;\n+\t\t\tfixup_stc_attr->vport.vport_num = ctx->caps->eswitch_manager_vport_number;\n+\t\t\tuse_fixup = true;\n+\t\t}\n+\t\tbreak;\n+\n \tcase MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT:\n \t\tif (stc_attr->vport.vport_num != WIRE_PORT)\n \t\t\tbreak;\n@@ -402,7 +415,7 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx,\n \tdevx_obj_0 = mlx5dr_pool_chunk_get_base_devx_obj(stc_pool, stc);\n \n \t/* According to table/action limitation change the stc_attr */\n-\tuse_fixup = mlx5dr_action_fixup_stc_attr(stc_attr, &fixup_stc_attr, table_type, false);\n+\tuse_fixup = mlx5dr_action_fixup_stc_attr(ctx, stc_attr, &fixup_stc_attr, table_type, false);\n \tret = mlx5dr_cmd_stc_modify(devx_obj_0, use_fixup ? &fixup_stc_attr : stc_attr);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to modify STC action_type %d tbl_type %d\",\n@@ -416,7 +429,8 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx,\n \n \t\tdevx_obj_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(stc_pool, stc);\n \n-\t\tuse_fixup = mlx5dr_action_fixup_stc_attr(stc_attr, &fixup_stc_attr,\n+\t\tuse_fixup = mlx5dr_action_fixup_stc_attr(ctx, stc_attr,\n+\t\t\t\t\t\t\t &fixup_stc_attr,\n \t\t\t\t\t\t\t table_type, true);\n \t\tret = mlx5dr_cmd_stc_modify(devx_obj_1, use_fixup ? &fixup_stc_attr : stc_attr);\n \t\tif (ret) {\n@@ -496,7 +510,6 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action,\n \tcase MLX5DR_ACTION_TYP_MISS:\n \t\tattr->action_type = MLX5_IFC_STC_ACTION_TYPE_ALLOW;\n \t\tattr->action_offset = MLX5DR_ACTION_OFFSET_HIT;\n-\t\t/* TODO Need to support default miss for FDB */\n \t\tbreak;\n \tcase MLX5DR_ACTION_TYP_CTR:\n \t\tattr->id = obj->id;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_table.c b/drivers/net/mlx5/hws/mlx5dr_table.c\nindex 46c2a47015..2c8b7a2b9e 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_table.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_table.c\n@@ -25,8 +25,6 @@ mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl)\n \tstruct mlx5dr_cmd_set_fte_dest dest = {0};\n \tstruct mlx5dr_context *ctx = tbl->ctx;\n \tuint8_t tbl_type = tbl->type;\n-\tuint32_t vport;\n-\n \tif (tbl->type != MLX5DR_TABLE_TYPE_FDB)\n \t\treturn 0;\n \n@@ -39,11 +37,9 @@ mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl)\n \tft_attr.level = tbl->ctx->caps->fdb_ft.max_level; /* The last level */\n \tft_attr.rtc_valid = false;\n \n-\tassert(ctx->caps->eswitch_manager);\n-\tvport = ctx->caps->eswitch_manager_vport_number;\n-\n \tdest.destination_type = MLX5_FLOW_DESTINATION_TYPE_VPORT;\n-\tdest.destination_id = vport;\n+\tdest.destination_id = ctx->caps->eswitch_manager_vport_number;\n+\n \tfte_attr.action_flags = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;\n \tfte_attr.dests_num = 1;\n \tfte_attr.dests = &dest;\n", "prefixes": [ "v2", "5/5" ] }