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GET /api/patches/129200/?format=api
{ "id": 129200, "url": "http://patchwork.dpdk.org/api/patches/129200/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230703092434.3424624-1-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230703092434.3424624-1-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230703092434.3424624-1-junfeng.guo@intel.com", "date": "2023-07-03T09:24:34", "name": "doc: update BIOS setting and supported HW list for NTB", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b41a340311158a94ddb5cad8cff77d63b53a932a", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230703092434.3424624-1-junfeng.guo@intel.com/mbox/", "series": [ { "id": 28776, "url": "http://patchwork.dpdk.org/api/series/28776/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28776", "date": "2023-07-03T09:24:34", "name": "doc: update BIOS setting and supported HW list for NTB", "version": 1, "mbox": "http://patchwork.dpdk.org/series/28776/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129200/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/129200/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CBC5F42DA8;\n\tMon, 3 Jul 2023 11:24:47 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5282B40ED5;\n\tMon, 3 Jul 2023 11:24:47 +0200 (CEST)", "from mga06.intel.com (mga06b.intel.com [134.134.136.31])\n by mails.dpdk.org (Postfix) with ESMTP id 813BF40156;\n Mon, 3 Jul 2023 11:24:45 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 Jul 2023 02:24:44 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.149])\n by fmsmga005.fm.intel.com with ESMTP; 03 Jul 2023 02:24:42 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1688376285; x=1719912285;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=9pVzrTnohk6f0ugKUNqLQ8xBmoCbHLTXYpyJ4sTuTJw=;\n b=Bh1YG4kDAihVgn6jUTJ2PDnfUSmM+oTLIUaT9ImQ1YDTRbXWxJVlaODJ\n lddPRaTFYEGYEDftS0uo68J53bs/zhx2D/fCnMuO98cE5hz+1ucnp3ERj\n VY+PazKJiAXgnjqiOkZOJXZfFYUjL8RDpUOuDZBGl+w6N+k4zP0pgFhQ/\n 1rpr+p32GHxlCoLnPPK/L5i81Z/XA6vtrJUTSSpF1F8vXz40XHjpWvUQu\n 9oKYFyJuH2koVziNTIGn+S14iidAH4bGuk1wj4zl81FqMJp+GKZcscdy2\n iBTA/Y47ljlCechCiJ+4BS4/dr9hLXBhjeNwP0xpxNsVTNACCaU9REyAT A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10759\"; a=\"426521277\"", "E=Sophos;i=\"6.01,177,1684825200\"; d=\"scan'208\";a=\"426521277\"", "E=McAfee;i=\"6600,9927,10759\"; a=\"1049012298\"", "E=Sophos;i=\"6.01,177,1684825200\"; d=\"scan'208\";a=\"1049012298\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org,\n\tstable@dpdk.org,\n\tJunfeng Guo <junfeng.guo@intel.com>", "Subject": "[PATCH] doc: update BIOS setting and supported HW list for NTB", "Date": "Mon, 3 Jul 2023 17:24:34 +0800", "Message-Id": "<20230703092434.3424624-1-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Update BIOS settings and supported platform list for Intel NTB.\n\nFixes: f5057be340e4 (\"raw/ntb: support Intel Ice Lake\")\nCc: stable@dpdk.org\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n doc/guides/rawdevs/ntb.rst | 32 ++++++++++++++++++++------------\n 1 file changed, 20 insertions(+), 12 deletions(-)", "diff": "diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst\nindex 2bb115d13f..c34512177a 100644\n--- a/doc/guides/rawdevs/ntb.rst\n+++ b/doc/guides/rawdevs/ntb.rst\n@@ -17,18 +17,22 @@ some information by using scratchpad registers.\n BIOS setting on Intel Xeon\n --------------------------\n \n-Intel Non-transparent Bridge needs special BIOS setting. The reference for\n-Skylake is https://www.intel.com/content/dam/support/us/en/documents/server-products/Intel_Xeon_Processor_Scalable_Family_BIOS_User_Guide.pdf\n-\n-- Set the needed PCIe port as NTB to NTB mode on both hosts.\n-- Enable NTB bars and set bar size of bar 23 and bar 45 as 12-29 (4K-512M)\n- on both hosts (for Ice Lake, bar size can be set as 12-51, namely 4K-128PB).\n- Note that bar size on both hosts should be the same.\n-- Disable split bars for both hosts.\n-- Set crosslink control override as DSD/USP on one host, USD/DSP on\n+Intel Non-transparent Bridge (NTB) needs special BIOS settings on both systems.\n+Note that for 4th Generation Intel® Xeon® Scalable Processors, option ``Port\n+Subsystem Mode`` should be changed from ``Gen5`` to ``Gen4 Only``, then reboot.\n+\n+- Set ``Non-Transparent Bridge PCIe Port Definition`` for needed PCIe ports as\n+ ``NTB to NTB`` mode, on both hosts.\n+- Set ``Enable NTB BARs`` as ``Enabled``, on both hosts.\n+- Set ``Enable SPLIT BARs`` as ``Disabled``, on both hosts.\n+- Set ``Imbar1 Size``, ``Imbar2 Size``, ``Embar1 Size`` and ``Embar2 Size``, as\n+ 12-29 (i.e., 4K-512M) for 2nd Generation Intel® Xeon® Scalable Processors; as\n+ 12-51 (i.e., 4K-128PB) for 3rd and 4th Generation Intel® Xeon® Scalable\n+ Processors. Note that those bar sizes on both hosts should be the same.\n+- Set ``Crosslink Control override`` as ``DSD/USP`` on one host, ``USD/DSP`` on\n another host.\n-- Disable PCIe PII SSC (Spread Spectrum Clocking) for both hosts. This\n- is a hardware requirement.\n+- Set ``PCIe PLL SSC (Spread Spectrum Clocking)`` as ``Disabled``, on both\n+ hosts. This is a hardware requirement when using Re-timer Cards.\n \n \n Device Setup\n@@ -145,4 +149,8 @@ like the following:\n Limitation\n ----------\n \n-- This PMD only supports Intel Skylake and Ice Lake platforms.\n+This PMD is only supported on Intel Xeon Platforms:\n+\n+- 4th Generation Intel® Xeon® Scalable Processors.\n+- 3rd Generation Intel® Xeon® Scalable Processors.\n+- 2nd Generation Intel® Xeon® Scalable Processors.\n", "prefixes": [] }