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GET /api/patches/129257/?format=api
{ "id": 129257, "url": "http://patchwork.dpdk.org/api/patches/129257/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230704160454.4187-5-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230704160454.4187-5-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230704160454.4187-5-igozlan@nvidia.com", "date": "2023-07-04T16:04:53", "name": "[v3,5/5] net/mlx5/hws: support default miss action on FDB", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e9dd28fc19bd9672151bb5a892c9276939621055", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230704160454.4187-5-igozlan@nvidia.com/mbox/", "series": [ { "id": 28810, "url": "http://patchwork.dpdk.org/api/series/28810/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28810", "date": "2023-07-04T16:04:49", "name": "[v3,1/5] net/mlx5/hws: remove unneeded new line for DR_LOG", "version": 3, "mbox": "http://patchwork.dpdk.org/series/28810/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129257/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/129257/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6698D42DAE;\n\tTue, 4 Jul 2023 18:06:38 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B16B242C54;\n\tTue, 4 Jul 2023 18:06:34 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2068.outbound.protection.outlook.com [40.107.244.68])\n by mails.dpdk.org (Postfix) with ESMTP id 6A87542D31\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Itamar Gozlan <igozlan@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <matan@nvidia.com>,\n <thomas@monjalon.net>, <suanmingm@nvidia.com>, Ori Kam <orika@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[v3 5/5] net/mlx5/hws: support default miss action on FDB", "Date": "Tue, 4 Jul 2023 19:04:53 +0300", "Message-ID": "<20230704160454.4187-5-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20230704160454.4187-1-igozlan@nvidia.com>", "References": "<20230704104645.19800-5-igozlan@nvidia.com>\n <20230704160454.4187-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT077:EE_|DS7PR12MB5981:EE_", "X-MS-Office365-Filtering-Correlation-Id": "db8049c8-a888-4ff4-ca0e-08db7ca8a130", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n /+b+dAh0bkfz4jDGkfg3XTkXlyHmqMgNQffoyCO75NvNZz9XX5oQvq1whGidoMwGnBKBdSVhNTQ8JKsEOEEiGtSDeXBHRf6T6Zpj5XoAkaxvE/DECIb1z0CUOfLkQN1Zsw51nO7OQiqX3AubH216e5v6B6FFpw+xp78WIBPxow7Tdk3f3Djw9XnV/NhL1Ai7oRMMlpuI5aOqJV+dX46vXmnncGBfmUJo7vQgATQSNnVqwqFz62OEWZPYVloKqowCBSKjmrlpL3kfyFnJ61XXeK0DvOZN8zh5fr0T4dKRIVYYUUsT5zwC7XdWBEGqc7YycJ/ackk3MzKyDLhMKNU3W3qAaWV8rFwmAkpYHu9YHLsRv4MkUVri/qIpekii5ZQnuDBPRGkZk9p4nbviFeAMJfHFqohDfGF0yW4mM0mrpWGt1+zVvtgUV7RY++Q+B9MMl5w3iDzAxrrMzHABfS48A86k6P5t9ZS6bukD/BKgH51sze6HL5k7f759ksuxocOhhFlgpXfMUIaoar6sO/R/XciGtS0eAjP+PJVgcJMi5qxFW4KL/gkXn5dkpWU6ZQsuR8OeudYcSqITH/NJcba6QlkfZSkevmZz7N38pQL2+ufi7RAK6LOHO8qGkmYVsMqtgG+zlNeTSVb/6CwD1wRE+LvYtwgcsbai08ZOupVOtx4TnvLjNFuwpS+SfLL/0DtN+eSwBZSIeMWO+F8oeKD0Muehf8YaDE5fpbHhfLCTd9VIP9gDO4IVUohutEqzZ3mT", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(39860400002)(136003)(346002)(396003)(376002)(451199021)(46966006)(40470700004)(36840700001)(8676002)(110136005)(8936002)(478600001)(26005)(6666004)(41300700001)(36756003)(5660300002)(2906002)(7696005)(86362001)(4326008)(316002)(40460700003)(55016003)(6636002)(70206006)(70586007)(82740400003)(7636003)(40480700001)(356005)(47076005)(2616005)(6286002)(186003)(83380400001)(82310400005)(336012)(426003)(1076003)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Jul 2023 16:06:30.2173 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n db8049c8-a888-4ff4-ca0e-08db7ca8a130", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT077.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB5981", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Alex Vesker <valex@nvidia.com>\n\nAdd the support for default miss on HWS FDB, this implementation\nwas missing until now. Default miss can be used for more efficient\nmiss flow instead of going to an empty matcher or some defecated\nempty table.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_action.c | 27 ++++++++++++++++++++-------\n drivers/net/mlx5/hws/mlx5dr_table.c | 6 +-----\n 2 files changed, 21 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c\nindex 74f4e60863..920099ba5b 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_action.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_action.c\n@@ -322,10 +322,12 @@ int mlx5dr_action_root_build_attr(struct mlx5dr_rule_action rule_actions[],\n \treturn 0;\n }\n \n-static bool mlx5dr_action_fixup_stc_attr(struct mlx5dr_cmd_stc_modify_attr *stc_attr,\n-\t\t\t\t\t struct mlx5dr_cmd_stc_modify_attr *fixup_stc_attr,\n-\t\t\t\t\t enum mlx5dr_table_type table_type,\n-\t\t\t\t\t bool is_mirror)\n+static bool\n+mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_cmd_stc_modify_attr *stc_attr,\n+\t\t\t struct mlx5dr_cmd_stc_modify_attr *fixup_stc_attr,\n+\t\t\t enum mlx5dr_table_type table_type,\n+\t\t\t bool is_mirror)\n {\n \tstruct mlx5dr_devx_obj *devx_obj;\n \tbool use_fixup = false;\n@@ -348,6 +350,17 @@ static bool mlx5dr_action_fixup_stc_attr(struct mlx5dr_cmd_stc_modify_attr *stc_\n \t\tuse_fixup = true;\n \t\tbreak;\n \n+\tcase MLX5_IFC_STC_ACTION_TYPE_ALLOW:\n+\t\tif (fw_tbl_type == FS_FT_FDB_TX || fw_tbl_type == FS_FT_FDB_RX) {\n+\t\t\tfixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT;\n+\t\t\tfixup_stc_attr->action_offset = stc_attr->action_offset;\n+\t\t\tfixup_stc_attr->stc_offset = stc_attr->stc_offset;\n+\t\t\tfixup_stc_attr->vport.esw_owner_vhca_id = ctx->caps->vhca_id;\n+\t\t\tfixup_stc_attr->vport.vport_num = ctx->caps->eswitch_manager_vport_number;\n+\t\t\tuse_fixup = true;\n+\t\t}\n+\t\tbreak;\n+\n \tcase MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT:\n \t\tif (stc_attr->vport.vport_num != WIRE_PORT)\n \t\t\tbreak;\n@@ -397,7 +410,7 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx,\n \tdevx_obj_0 = mlx5dr_pool_chunk_get_base_devx_obj(stc_pool, stc);\n \n \t/* According to table/action limitation change the stc_attr */\n-\tuse_fixup = mlx5dr_action_fixup_stc_attr(stc_attr, &fixup_stc_attr, table_type, false);\n+\tuse_fixup = mlx5dr_action_fixup_stc_attr(ctx, stc_attr, &fixup_stc_attr, table_type, false);\n \tret = mlx5dr_cmd_stc_modify(devx_obj_0, use_fixup ? &fixup_stc_attr : stc_attr);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to modify STC action_type %d tbl_type %d\",\n@@ -411,7 +424,8 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx,\n \n \t\tdevx_obj_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(stc_pool, stc);\n \n-\t\tuse_fixup = mlx5dr_action_fixup_stc_attr(stc_attr, &fixup_stc_attr,\n+\t\tuse_fixup = mlx5dr_action_fixup_stc_attr(ctx, stc_attr,\n+\t\t\t\t\t\t\t &fixup_stc_attr,\n \t\t\t\t\t\t\t table_type, true);\n \t\tret = mlx5dr_cmd_stc_modify(devx_obj_1, use_fixup ? &fixup_stc_attr : stc_attr);\n \t\tif (ret) {\n@@ -491,7 +505,6 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action,\n \tcase MLX5DR_ACTION_TYP_MISS:\n \t\tattr->action_type = MLX5_IFC_STC_ACTION_TYPE_ALLOW;\n \t\tattr->action_offset = MLX5DR_ACTION_OFFSET_HIT;\n-\t\t/* TODO Need to support default miss for FDB */\n \t\tbreak;\n \tcase MLX5DR_ACTION_TYP_CTR:\n \t\tattr->id = obj->id;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_table.c b/drivers/net/mlx5/hws/mlx5dr_table.c\nindex c18ee7c552..f91f04d924 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_table.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_table.c\n@@ -24,7 +24,6 @@ mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl)\n \tstruct mlx5dr_cmd_forward_tbl *default_miss;\n \tstruct mlx5dr_context *ctx = tbl->ctx;\n \tuint8_t tbl_type = tbl->type;\n-\tuint32_t vport;\n \n \tif (tbl->type != MLX5DR_TABLE_TYPE_FDB)\n \t\treturn 0;\n@@ -38,12 +37,9 @@ mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl)\n \tft_attr.level = tbl->ctx->caps->fdb_ft.max_level; /* The last level */\n \tft_attr.rtc_valid = false;\n \n-\tassert(ctx->caps->eswitch_manager);\n-\tvport = ctx->caps->eswitch_manager_vport_number;\n-\n \tfte_attr.action_flags = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;\n \tfte_attr.destination_type = MLX5_FLOW_DESTINATION_TYPE_VPORT;\n-\tfte_attr.destination_id = vport;\n+\tfte_attr.destination_id = ctx->caps->eswitch_manager_vport_number;\n \n \tdefault_miss = mlx5dr_cmd_forward_tbl_create(mlx5dr_context_get_local_ibv(ctx),\n \t\t\t\t\t\t &ft_attr, &fte_attr);\n", "prefixes": [ "v3", "5/5" ] }