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GET /api/patches/129291/?format=api
{ "id": 129291, "url": "http://patchwork.dpdk.org/api/patches/129291/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230705111038.9935-2-viacheslavo@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230705111038.9935-2-viacheslavo@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230705111038.9935-2-viacheslavo@nvidia.com", "date": "2023-07-05T11:10:35", "name": "[v4,1/4] net/mlx5: introduce tracepoints for mlx5 drivers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "20370009808fe955a0abe43952f24482f60565ac", "submitter": { "id": 1926, "url": "http://patchwork.dpdk.org/api/people/1926/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230705111038.9935-2-viacheslavo@nvidia.com/mbox/", "series": [ { "id": 28833, "url": "http://patchwork.dpdk.org/api/series/28833/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28833", "date": "2023-07-05T11:10:34", "name": "net/mlx5: introduce Tx datapath tracing", "version": 4, "mbox": "http://patchwork.dpdk.org/series/28833/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129291/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/129291/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 60CF042DD9;\n\tWed, 5 Jul 2023 13:11:25 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9906142BDA;\n\tWed, 5 Jul 2023 13:11:15 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2053.outbound.protection.outlook.com [40.107.237.53])\n by mails.dpdk.org (Postfix) with ESMTP id 532F540ED8\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <rasland@nvidia.com>", "Subject": "[PATCH v4 1/4] net/mlx5: introduce tracepoints for mlx5 drivers", "Date": "Wed, 5 Jul 2023 14:10:35 +0300", "Message-ID": "<20230705111038.9935-2-viacheslavo@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20230705111038.9935-1-viacheslavo@nvidia.com>", "References": "<20230420100803.494-1-viacheslavo@nvidia.com>\n <20230705111038.9935-1-viacheslavo@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT033:EE_|CH3PR12MB8935:EE_", "X-MS-Office365-Filtering-Correlation-Id": "516fb499-43e6-41a6-a881-08db7d4888ef", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 7dRXy2wmMittVAINbK+sknKbn7xzQ1Twjj10PTVKR5obAYdgpz4DUJzCoP8gFnGBWV7ahIamIjb9DST7ZdK+FoenrQOL8Wfi9zRrsyZAZNPZXRTVD3wB4HVxJf4E45jyQ4SYZthjTQ8uTHoZe5MePuD6d0OA5+mnylwFbMa6PlfVi8Y0Oxj56NR60KRWnltfB6ssBXsBRzaZpIe23iyVk8u9wcBKkvlu4vPXqmH+u5101jS0bAE8JlMXiWQKH7DGzOp9WZtaOKwdT1lJCPFtfZ8GRSCtqBFlONyoEXNLWRWnzZcMsewo03vfyso+8e3bREj/cgKqEHd6I95BvU8pHyTcSDsTFvZHtHv3iU8ve+akYG2VcmuDtJOcKi5s0LfLQyKPeJsb8GHnXsV8a2mXiyMlPZ+HUwFcfpwhZRG1XcAggF+PjCFYtJgxVF2GR1GdpvMM4NCawzj2lAgf0QR9efDxqOZl+jf9x1n4301GqXSBK9aEjZs8aKdJ/Ah3Lcj2+JiB3bOrdylBbHoCAIJMU9gKz+TgyngDmlfzKWY76BiT1MYHdZ6hPXbqBCTBGhhAqU4X3kNNS/04GYP/4LXK7EQ+KxiZoavxzsgS9ORLI6F3FvMRNUzq7kkQLbpt4zBRmlwkfkNklVgh6ipcHaG/cLnBIwxkTSMVtflOX+5kAHVXRm5p9b8B0gRjUD2xsFATPaV47rvEulP4oeofsXyGnby/LvfGQDvcMMIZ+6Wswp+isGyo6IkS+cP0XZrtElv0", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199021)(36840700001)(46966006)(40470700004)(6666004)(7696005)(478600001)(70586007)(54906003)(36860700001)(2616005)(83380400001)(47076005)(426003)(336012)(36756003)(86362001)(55016003)(40480700001)(30864003)(2906002)(82310400005)(16526019)(6286002)(70206006)(186003)(1076003)(26005)(107886003)(7636003)(356005)(82740400003)(6916009)(4326008)(40460700003)(316002)(41300700001)(8936002)(8676002)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Jul 2023 11:11:08.9550 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 516fb499-43e6-41a6-a881-08db7d4888ef", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT033.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8935", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "There is an intention to engage DPDK tracing capabilities\nfor mlx5 PMDs monitoring and profiling in various modes.\nThe patch introduces tracepoints for the Tx datapath in\nthe ethernet device driver.\n\nTo engage this tracing capability the following steps\nshould be taken:\n\n- meson option -Denable_trace_fp=true\n- meson option -Dc_args='-DALLOW_EXPERIMENTAL_API'\n- EAL command line parameter --trace=pmd.net.mlx5.tx.*\n\nThe Tx datapath tracing allows to get information how packets\nare pushed into hardware descriptors, time stamping for\nscheduled wait and send completions, etc.\n\nTo provide the human readable form of trace results the\ndedicated post-processing script is presumed.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rx.h | 19 ----------\n drivers/net/mlx5/mlx5_rxtx.h | 19 ++++++++++\n drivers/net/mlx5/mlx5_tx.c | 29 +++++++++++++++\n drivers/net/mlx5/mlx5_tx.h | 72 +++++++++++++++++++++++++++++++++++-\n 4 files changed, 118 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 3514edd84e..f42607dce4 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -377,25 +377,6 @@ mlx5_rx_mb2mr(struct mlx5_rxq_data *rxq, struct rte_mbuf *mb)\n \treturn mlx5_mr_mempool2mr_bh(mr_ctrl, mb->pool, addr);\n }\n \n-/**\n- * Convert timestamp from HW format to linear counter\n- * from Packet Pacing Clock Queue CQE timestamp format.\n- *\n- * @param sh\n- * Pointer to the device shared context. Might be needed\n- * to convert according current device configuration.\n- * @param ts\n- * Timestamp from CQE to convert.\n- * @return\n- * UTC in nanoseconds\n- */\n-static __rte_always_inline uint64_t\n-mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)\n-{\n-\tRTE_SET_USED(sh);\n-\treturn (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;\n-}\n-\n /**\n * Set timestamp in mbuf dynamic field.\n *\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 876aa14ae6..b109d50758 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -43,4 +43,23 @@ int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,\n int mlx5_queue_state_modify(struct rte_eth_dev *dev,\n \t\t\t struct mlx5_mp_arg_queue_state_modify *sm);\n \n+/**\n+ * Convert timestamp from HW format to linear counter\n+ * from Packet Pacing Clock Queue CQE timestamp format.\n+ *\n+ * @param sh\n+ * Pointer to the device shared context. Might be needed\n+ * to convert according current device configuration.\n+ * @param ts\n+ * Timestamp from CQE to convert.\n+ * @return\n+ * UTC in nanoseconds\n+ */\n+static __rte_always_inline uint64_t\n+mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)\n+{\n+\tRTE_SET_USED(sh);\n+\treturn (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;\n+}\n+\n #endif /* RTE_PMD_MLX5_RXTX_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_tx.c b/drivers/net/mlx5/mlx5_tx.c\nindex 14e1487e59..13e2d90e03 100644\n--- a/drivers/net/mlx5/mlx5_tx.c\n+++ b/drivers/net/mlx5/mlx5_tx.c\n@@ -7,6 +7,7 @@\n #include <string.h>\n #include <stdlib.h>\n \n+#include <rte_trace_point_register.h>\n #include <rte_mbuf.h>\n #include <rte_mempool.h>\n #include <rte_prefetch.h>\n@@ -232,6 +233,15 @@ mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,\n \t\tMLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==\n \t\t\t cqe->wqe_counter);\n #endif\n+\t\tif (__rte_trace_point_fp_is_enabled()) {\n+\t\t\tuint64_t ts = rte_be_to_cpu_64(cqe->timestamp);\n+\t\t\tuint16_t wqe_id = rte_be_to_cpu_16(cqe->wqe_counter);\n+\n+\t\t\tif (txq->rt_timestamp)\n+\t\t\t\tts = mlx5_txpp_convert_rx_ts(NULL, ts);\n+\t\t\trte_pmd_mlx5_trace_tx_complete(txq->port_id, txq->idx,\n+\t\t\t\t\t\t wqe_id, ts);\n+\t\t}\n \t\tring_doorbell = true;\n \t\t++txq->cq_ci;\n \t\tlast_cqe = cqe;\n@@ -752,3 +762,22 @@ mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,\n \t}\n \treturn -EINVAL;\n }\n+\n+/* TX burst subroutines trace points. */\n+RTE_TRACE_POINT_REGISTER(rte_pmd_mlx5_trace_tx_entry,\n+\tpmd.net.mlx5.tx.entry)\n+\n+RTE_TRACE_POINT_REGISTER(rte_pmd_mlx5_trace_tx_exit,\n+\tpmd.net.mlx5.tx.exit)\n+\n+RTE_TRACE_POINT_REGISTER(rte_pmd_mlx5_trace_tx_wqe,\n+\tpmd.net.mlx5.tx.wqe)\n+\n+RTE_TRACE_POINT_REGISTER(rte_pmd_mlx5_trace_tx_wait,\n+\tpmd.net.mlx5.tx.wait)\n+\n+RTE_TRACE_POINT_REGISTER(rte_pmd_mlx5_trace_tx_push,\n+\tpmd.net.mlx5.tx.push)\n+\n+RTE_TRACE_POINT_REGISTER(rte_pmd_mlx5_trace_tx_complete,\n+\tpmd.net.mlx5.tx.complete)\ndiff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h\nindex cc8f7e98aa..b90cdf1fcc 100644\n--- a/drivers/net/mlx5/mlx5_tx.h\n+++ b/drivers/net/mlx5/mlx5_tx.h\n@@ -13,12 +13,61 @@\n #include <rte_mempool.h>\n #include <rte_common.h>\n #include <rte_spinlock.h>\n+#include <rte_trace_point.h>\n \n #include <mlx5_common.h>\n #include <mlx5_common_mr.h>\n \n #include \"mlx5.h\"\n #include \"mlx5_autoconf.h\"\n+#include \"mlx5_rxtx.h\"\n+\n+/* TX burst subroutines trace points. */\n+RTE_TRACE_POINT_FP(\n+\trte_pmd_mlx5_trace_tx_entry,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+)\n+\n+RTE_TRACE_POINT_FP(\n+\trte_pmd_mlx5_trace_tx_exit,\n+\tRTE_TRACE_POINT_ARGS(uint16_t nb_sent, uint16_t nb_req),\n+\trte_trace_point_emit_u16(nb_sent);\n+\trte_trace_point_emit_u16(nb_req);\n+)\n+\n+RTE_TRACE_POINT_FP(\n+\trte_pmd_mlx5_trace_tx_wqe,\n+\tRTE_TRACE_POINT_ARGS(uint32_t opcode),\n+\trte_trace_point_emit_u32(opcode);\n+)\n+\n+RTE_TRACE_POINT_FP(\n+\trte_pmd_mlx5_trace_tx_wait,\n+\tRTE_TRACE_POINT_ARGS(uint64_t ts),\n+\trte_trace_point_emit_u64(ts);\n+)\n+\n+\n+RTE_TRACE_POINT_FP(\n+\trte_pmd_mlx5_trace_tx_push,\n+\tRTE_TRACE_POINT_ARGS(const struct rte_mbuf *mbuf, uint16_t wqe_id),\n+\trte_trace_point_emit_ptr(mbuf);\n+\trte_trace_point_emit_u32(mbuf->pkt_len);\n+\trte_trace_point_emit_u16(mbuf->nb_segs);\n+\trte_trace_point_emit_u16(wqe_id);\n+)\n+\n+RTE_TRACE_POINT_FP(\n+\trte_pmd_mlx5_trace_tx_complete,\n+\tRTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id,\n+\t\t\t uint16_t wqe_id, uint64_t ts),\n+\trte_trace_point_emit_u16(port_id);\n+\trte_trace_point_emit_u16(queue_id);\n+\trte_trace_point_emit_u64(ts);\n+\trte_trace_point_emit_u16(wqe_id);\n+)\n \n /* TX burst subroutines return codes. */\n enum mlx5_txcmp_code {\n@@ -764,6 +813,9 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,\n \tcs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<\n \t\t\t MLX5_COMP_MODE_OFFSET);\n \tcs->misc = RTE_BE32(0);\n+\tif (__rte_trace_point_fp_is_enabled() && !loc->pkts_sent)\n+\t\trte_pmd_mlx5_trace_tx_entry(txq->port_id, txq->idx);\n+\trte_pmd_mlx5_trace_tx_wqe((txq->wqe_ci << 8) | opcode);\n }\n \n /**\n@@ -1692,6 +1744,7 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,\n \t\tif (txq->wait_on_time) {\n \t\t\t/* The wait on time capability should be used. */\n \t\t\tts -= sh->txpp.skew;\n+\t\t\trte_pmd_mlx5_trace_tx_wait(ts);\n \t\t\tmlx5_tx_cseg_init(txq, loc, wqe,\n \t\t\t\t\t 1 + sizeof(struct mlx5_wqe_wseg) /\n \t\t\t\t\t MLX5_WSEG_SIZE,\n@@ -1706,6 +1759,7 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,\n \t\t\tif (unlikely(wci < 0))\n \t\t\t\treturn MLX5_TXCMP_CODE_SINGLE;\n \t\t\t/* Build the WAIT WQE with specified completion. */\n+\t\t\trte_pmd_mlx5_trace_tx_wait(ts - sh->txpp.skew);\n \t\t\tmlx5_tx_cseg_init(txq, loc, wqe,\n \t\t\t\t\t 1 + sizeof(struct mlx5_wqe_qseg) /\n \t\t\t\t\t MLX5_WSEG_SIZE,\n@@ -1810,6 +1864,7 @@ mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,\n \twqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);\n \tloc->wqe_last = wqe;\n \tmlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);\n+\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \tds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);\n \twqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);\n \ttxq->wqe_ci += (ds + 3) / 4;\n@@ -1892,6 +1947,7 @@ mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,\n \twqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);\n \tloc->wqe_last = wqe;\n \tmlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);\n+\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \tmlx5_tx_eseg_none(txq, loc, wqe, olx);\n \tdseg = &wqe->dseg[0];\n \tdo {\n@@ -2115,6 +2171,7 @@ mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,\n \twqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);\n \tloc->wqe_last = wqe;\n \tmlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);\n+\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \tds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);\n \twqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);\n \ttxq->wqe_ci += (ds + 3) / 4;\n@@ -2318,8 +2375,8 @@ mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,\n \t\t */\n \t\twqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);\n \t\tloc->wqe_last = wqe;\n-\t\tmlx5_tx_cseg_init(txq, loc, wqe, ds,\n-\t\t\t\t MLX5_OPCODE_TSO, olx);\n+\t\tmlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_TSO, olx);\n+\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\tdseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);\n \t\tdptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;\n \t\tdlen -= hlen - vlan;\n@@ -2688,6 +2745,7 @@ mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t/* Update sent data bytes counter. */\n \t\t\tslen += dlen;\n #endif\n+\t\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\t\tmlx5_tx_dseg_ptr\n \t\t\t\t(txq, loc, dseg,\n \t\t\t\t rte_pktmbuf_mtod(loc->mbuf, uint8_t *),\n@@ -2926,6 +2984,7 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t\ttlen += sizeof(struct rte_vlan_hdr);\n \t\t\t\tif (room < tlen)\n \t\t\t\t\tbreak;\n+\t\t\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\t\t\tdseg = mlx5_tx_dseg_vlan(txq, loc, dseg,\n \t\t\t\t\t\t\t dptr, dlen, olx);\n #ifdef MLX5_PMD_SOFT_COUNTERS\n@@ -2935,6 +2994,7 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t} else {\n \t\t\t\tif (room < tlen)\n \t\t\t\t\tbreak;\n+\t\t\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\t\t\tdseg = mlx5_tx_dseg_empw(txq, loc, dseg,\n \t\t\t\t\t\t\t dptr, dlen, olx);\n \t\t\t}\n@@ -2980,6 +3040,7 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\tif (MLX5_TXOFF_CONFIG(VLAN))\n \t\t\t\tMLX5_ASSERT(!(loc->mbuf->ol_flags &\n \t\t\t\t\t RTE_MBUF_F_TX_VLAN));\n+\t\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\t\tmlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);\n \t\t\t/* We have to store mbuf in elts.*/\n \t\t\ttxq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;\n@@ -3194,6 +3255,7 @@ mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t\tloc->wqe_last = wqe;\n \t\t\t\tmlx5_tx_cseg_init(txq, loc, wqe, seg_n,\n \t\t\t\t\t\t MLX5_OPCODE_SEND, olx);\n+\t\t\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\t\t\tmlx5_tx_eseg_data(txq, loc, wqe,\n \t\t\t\t\t\t vlan, inlen, 0, olx);\n \t\t\t\ttxq->wqe_ci += wqe_n;\n@@ -3256,6 +3318,7 @@ mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t\tloc->wqe_last = wqe;\n \t\t\t\tmlx5_tx_cseg_init(txq, loc, wqe, ds,\n \t\t\t\t\t\t MLX5_OPCODE_SEND, olx);\n+\t\t\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\t\t\tdseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,\n \t\t\t\t\t\t\t txq->inlen_mode,\n \t\t\t\t\t\t\t 0, olx);\n@@ -3297,6 +3360,7 @@ mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\t\tloc->wqe_last = wqe;\n \t\t\t\tmlx5_tx_cseg_init(txq, loc, wqe, 4,\n \t\t\t\t\t\t MLX5_OPCODE_SEND, olx);\n+\t\t\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\t\t\tmlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);\n \t\t\t\tdptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +\n \t\t\t\t MLX5_ESEG_MIN_INLINE_SIZE - vlan;\n@@ -3338,6 +3402,7 @@ mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,\n \t\t\tloc->wqe_last = wqe;\n \t\t\tmlx5_tx_cseg_init(txq, loc, wqe, 3,\n \t\t\t\t\t MLX5_OPCODE_SEND, olx);\n+\t\t\trte_pmd_mlx5_trace_tx_push(loc->mbuf, txq->wqe_ci);\n \t\t\tmlx5_tx_eseg_none(txq, loc, wqe, olx);\n \t\t\tmlx5_tx_dseg_ptr\n \t\t\t\t(txq, loc, &wqe->dseg[0],\n@@ -3707,6 +3772,9 @@ mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,\n #endif\n \tif (MLX5_TXOFF_CONFIG(INLINE) && loc.mbuf_free)\n \t\t__mlx5_tx_free_mbuf(txq, pkts, loc.mbuf_free, olx);\n+\t/* Trace productive bursts only. */\n+\tif (__rte_trace_point_fp_is_enabled() && loc.pkts_sent)\n+\t\trte_pmd_mlx5_trace_tx_exit(loc.pkts_sent, pkts_n);\n \treturn loc.pkts_sent;\n }\n \n", "prefixes": [ "v4", "1/4" ] }