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GET /api/patches/129444/?format=api
{ "id": 129444, "url": "http://patchwork.dpdk.org/api/patches/129444/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230711102448.11627-5-liudongdong3@huawei.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230711102448.11627-5-liudongdong3@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230711102448.11627-5-liudongdong3@huawei.com", "date": "2023-07-11T10:24:47", "name": "[4/5] net/hns3: optimize the rearm mbuf function for SVE Rx", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "80d99ba4f1e3d1adf604ea2649cb125ee5335661", "submitter": { "id": 2718, "url": "http://patchwork.dpdk.org/api/people/2718/?format=api", "name": "Dongdong Liu", "email": "liudongdong3@huawei.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230711102448.11627-5-liudongdong3@huawei.com/mbox/", "series": [ { "id": 28901, "url": "http://patchwork.dpdk.org/api/series/28901/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28901", "date": "2023-07-11T10:24:43", "name": "net/hns3: some performance optimizations", "version": 1, "mbox": "http://patchwork.dpdk.org/series/28901/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129444/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/129444/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 31C6742E44;\n\tTue, 11 Jul 2023 12:28:17 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8188042D38;\n\tTue, 11 Jul 2023 12:28:01 +0200 (CEST)", "from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187])\n by mails.dpdk.org (Postfix) with ESMTP id 0FAC34003C;\n Tue, 11 Jul 2023 12:27:56 +0200 (CEST)", "from kwepemi500017.china.huawei.com (unknown [172.30.72.54])\n by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4R0cSS18bCztRF1;\n Tue, 11 Jul 2023 18:24:56 +0800 (CST)", "from localhost.localdomain (10.28.79.22) by\n kwepemi500017.china.huawei.com (7.221.188.110) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.2507.27; Tue, 11 Jul 2023 18:27:54 +0800" ], "From": "Dongdong Liu <liudongdong3@huawei.com>", "To": "<dev@dpdk.org>, <ferruh.yigit@amd.com>, <thomas@monjalon.net>,\n <andrew.rybchenko@oktetlabs.ru>", "CC": "<stable@dpdk.org>", "Subject": "[PATCH 4/5] net/hns3: optimize the rearm mbuf function for SVE Rx", "Date": "Tue, 11 Jul 2023 18:24:47 +0800", "Message-ID": "<20230711102448.11627-5-liudongdong3@huawei.com>", "X-Mailer": "git-send-email 2.22.0", "In-Reply-To": "<20230711102448.11627-1-liudongdong3@huawei.com>", "References": "<20230711102448.11627-1-liudongdong3@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.28.79.22]", "X-ClientProxiedBy": "dggems701-chm.china.huawei.com (10.3.19.178) To\n kwepemi500017.china.huawei.com (7.221.188.110)", "X-CFilter-Loop": "Reflected", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Huisong Li <lihuisong@huawei.com>\n\nUse hns3_rxq_rearm_mbuf() to replace the hns3_rxq_rearm_mbuf_sve()\nto optimize the performance of SVE Rx.\n\nOn the rxonly forwarding mode, the performance of a single queue\nfor 64B packet is improved by ~15%.\n\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\nSigned-off-by: Dongdong Liu <liudongdong3@huawei.com>\n---\n drivers/net/hns3/hns3_rxtx_vec.c | 51 ---------------------------\n drivers/net/hns3/hns3_rxtx_vec.h | 51 +++++++++++++++++++++++++++\n drivers/net/hns3/hns3_rxtx_vec_sve.c | 52 ++--------------------------\n 3 files changed, 53 insertions(+), 101 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_rxtx_vec.c b/drivers/net/hns3/hns3_rxtx_vec.c\nindex cd9264d91b..9708ec614e 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec.c\n+++ b/drivers/net/hns3/hns3_rxtx_vec.c\n@@ -55,57 +55,6 @@ hns3_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \treturn nb_tx;\n }\n \n-static inline void\n-hns3_rxq_rearm_mbuf(struct hns3_rx_queue *rxq)\n-{\n-#define REARM_LOOP_STEP_NUM\t4\n-\tstruct hns3_entry *rxep = &rxq->sw_ring[rxq->rx_rearm_start];\n-\tstruct hns3_desc *rxdp = rxq->rx_ring + rxq->rx_rearm_start;\n-\tuint64_t dma_addr;\n-\tint i;\n-\n-\tif (unlikely(rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,\n-\t\t\t\t\t HNS3_DEFAULT_RXQ_REARM_THRESH) < 0)) {\n-\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n-\t\treturn;\n-\t}\n-\n-\tfor (i = 0; i < HNS3_DEFAULT_RXQ_REARM_THRESH; i += REARM_LOOP_STEP_NUM,\n-\t\trxep += REARM_LOOP_STEP_NUM, rxdp += REARM_LOOP_STEP_NUM) {\n-\t\tif (likely(i <\n-\t\t\tHNS3_DEFAULT_RXQ_REARM_THRESH - REARM_LOOP_STEP_NUM)) {\n-\t\t\trte_prefetch_non_temporal(rxep[4].mbuf);\n-\t\t\trte_prefetch_non_temporal(rxep[5].mbuf);\n-\t\t\trte_prefetch_non_temporal(rxep[6].mbuf);\n-\t\t\trte_prefetch_non_temporal(rxep[7].mbuf);\n-\t\t}\n-\n-\t\tdma_addr = rte_mbuf_data_iova_default(rxep[0].mbuf);\n-\t\trxdp[0].addr = rte_cpu_to_le_64(dma_addr);\n-\t\trxdp[0].rx.bd_base_info = 0;\n-\n-\t\tdma_addr = rte_mbuf_data_iova_default(rxep[1].mbuf);\n-\t\trxdp[1].addr = rte_cpu_to_le_64(dma_addr);\n-\t\trxdp[1].rx.bd_base_info = 0;\n-\n-\t\tdma_addr = rte_mbuf_data_iova_default(rxep[2].mbuf);\n-\t\trxdp[2].addr = rte_cpu_to_le_64(dma_addr);\n-\t\trxdp[2].rx.bd_base_info = 0;\n-\n-\t\tdma_addr = rte_mbuf_data_iova_default(rxep[3].mbuf);\n-\t\trxdp[3].addr = rte_cpu_to_le_64(dma_addr);\n-\t\trxdp[3].rx.bd_base_info = 0;\n-\t}\n-\n-\trxq->rx_rearm_start += HNS3_DEFAULT_RXQ_REARM_THRESH;\n-\tif (rxq->rx_rearm_start >= rxq->nb_rx_desc)\n-\t\trxq->rx_rearm_start = 0;\n-\n-\trxq->rx_rearm_nb -= HNS3_DEFAULT_RXQ_REARM_THRESH;\n-\n-\thns3_write_reg_opt(rxq->io_head_reg, HNS3_DEFAULT_RXQ_REARM_THRESH);\n-}\n-\n uint16_t\n hns3_recv_pkts_vec(void *__restrict rx_queue,\n \t\t struct rte_mbuf **__restrict rx_pkts,\ndiff --git a/drivers/net/hns3/hns3_rxtx_vec.h b/drivers/net/hns3/hns3_rxtx_vec.h\nindex 2c8a91921e..a9a6774294 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec.h\n+++ b/drivers/net/hns3/hns3_rxtx_vec.h\n@@ -94,4 +94,55 @@ hns3_rx_reassemble_pkts(struct rte_mbuf **rx_pkts,\n \n \treturn count;\n }\n+\n+static inline void\n+hns3_rxq_rearm_mbuf(struct hns3_rx_queue *rxq)\n+{\n+#define REARM_LOOP_STEP_NUM\t4\n+\tstruct hns3_entry *rxep = &rxq->sw_ring[rxq->rx_rearm_start];\n+\tstruct hns3_desc *rxdp = rxq->rx_ring + rxq->rx_rearm_start;\n+\tuint64_t dma_addr;\n+\tint i;\n+\n+\tif (unlikely(rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,\n+\t\t\t\t\t HNS3_DEFAULT_RXQ_REARM_THRESH) < 0)) {\n+\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < HNS3_DEFAULT_RXQ_REARM_THRESH; i += REARM_LOOP_STEP_NUM,\n+\t\trxep += REARM_LOOP_STEP_NUM, rxdp += REARM_LOOP_STEP_NUM) {\n+\t\tif (likely(i <\n+\t\t\tHNS3_DEFAULT_RXQ_REARM_THRESH - REARM_LOOP_STEP_NUM)) {\n+\t\t\trte_prefetch_non_temporal(rxep[4].mbuf);\n+\t\t\trte_prefetch_non_temporal(rxep[5].mbuf);\n+\t\t\trte_prefetch_non_temporal(rxep[6].mbuf);\n+\t\t\trte_prefetch_non_temporal(rxep[7].mbuf);\n+\t\t}\n+\n+\t\tdma_addr = rte_mbuf_data_iova_default(rxep[0].mbuf);\n+\t\trxdp[0].addr = rte_cpu_to_le_64(dma_addr);\n+\t\trxdp[0].rx.bd_base_info = 0;\n+\n+\t\tdma_addr = rte_mbuf_data_iova_default(rxep[1].mbuf);\n+\t\trxdp[1].addr = rte_cpu_to_le_64(dma_addr);\n+\t\trxdp[1].rx.bd_base_info = 0;\n+\n+\t\tdma_addr = rte_mbuf_data_iova_default(rxep[2].mbuf);\n+\t\trxdp[2].addr = rte_cpu_to_le_64(dma_addr);\n+\t\trxdp[2].rx.bd_base_info = 0;\n+\n+\t\tdma_addr = rte_mbuf_data_iova_default(rxep[3].mbuf);\n+\t\trxdp[3].addr = rte_cpu_to_le_64(dma_addr);\n+\t\trxdp[3].rx.bd_base_info = 0;\n+\t}\n+\n+\trxq->rx_rearm_start += HNS3_DEFAULT_RXQ_REARM_THRESH;\n+\tif (rxq->rx_rearm_start >= rxq->nb_rx_desc)\n+\t\trxq->rx_rearm_start = 0;\n+\n+\trxq->rx_rearm_nb -= HNS3_DEFAULT_RXQ_REARM_THRESH;\n+\n+\thns3_write_reg_opt(rxq->io_head_reg, HNS3_DEFAULT_RXQ_REARM_THRESH);\n+}\n #endif /* HNS3_RXTX_VEC_H */\ndiff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c\nindex 5011544e07..54aef7db8d 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec_sve.c\n+++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c\n@@ -237,54 +237,6 @@ hns3_recv_burst_vec_sve(struct hns3_rx_queue *__restrict rxq,\n \treturn nb_rx;\n }\n \n-static inline void\n-hns3_rxq_rearm_mbuf_sve(struct hns3_rx_queue *rxq)\n-{\n-#define REARM_LOOP_STEP_NUM\t4\n-\tstruct hns3_entry *rxep = &rxq->sw_ring[rxq->rx_rearm_start];\n-\tstruct hns3_desc *rxdp = rxq->rx_ring + rxq->rx_rearm_start;\n-\tstruct hns3_entry *rxep_tmp = rxep;\n-\tint i;\n-\n-\tif (unlikely(rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,\n-\t\t\t\t\t HNS3_DEFAULT_RXQ_REARM_THRESH) < 0)) {\n-\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n-\t\treturn;\n-\t}\n-\n-\tfor (i = 0; i < HNS3_DEFAULT_RXQ_REARM_THRESH; i += REARM_LOOP_STEP_NUM,\n-\t\trxep_tmp += REARM_LOOP_STEP_NUM) {\n-\t\tsvuint64_t prf = svld1_u64(PG64_256BIT, (uint64_t *)rxep_tmp);\n-\t\tsvprfd_gather_u64base(PG64_256BIT, prf, SV_PLDL1STRM);\n-\t}\n-\n-\tfor (i = 0; i < HNS3_DEFAULT_RXQ_REARM_THRESH; i += REARM_LOOP_STEP_NUM,\n-\t\trxep += REARM_LOOP_STEP_NUM, rxdp += REARM_LOOP_STEP_NUM) {\n-\t\tuint64_t iova[REARM_LOOP_STEP_NUM];\n-\t\tiova[0] = rte_mbuf_iova_get(rxep[0].mbuf);\n-\t\tiova[1] = rte_mbuf_iova_get(rxep[1].mbuf);\n-\t\tiova[2] = rte_mbuf_iova_get(rxep[2].mbuf);\n-\t\tiova[3] = rte_mbuf_iova_get(rxep[3].mbuf);\n-\t\tsvuint64_t siova = svld1_u64(PG64_256BIT, iova);\n-\t\tsiova = svadd_n_u64_z(PG64_256BIT, siova, RTE_PKTMBUF_HEADROOM);\n-\t\tsvuint64_t ol_base = svdup_n_u64(0);\n-\t\tsvst1_scatter_u64offset_u64(PG64_256BIT,\n-\t\t\t(uint64_t *)&rxdp[0].addr,\n-\t\t\tsvindex_u64(BD_FIELD_ADDR_OFFSET, BD_SIZE), siova);\n-\t\tsvst1_scatter_u64offset_u64(PG64_256BIT,\n-\t\t\t(uint64_t *)&rxdp[0].addr,\n-\t\t\tsvindex_u64(BD_FIELD_OL_OFFSET, BD_SIZE), ol_base);\n-\t}\n-\n-\trxq->rx_rearm_start += HNS3_DEFAULT_RXQ_REARM_THRESH;\n-\tif (rxq->rx_rearm_start >= rxq->nb_rx_desc)\n-\t\trxq->rx_rearm_start = 0;\n-\n-\trxq->rx_rearm_nb -= HNS3_DEFAULT_RXQ_REARM_THRESH;\n-\n-\thns3_write_reg_opt(rxq->io_head_reg, HNS3_DEFAULT_RXQ_REARM_THRESH);\n-}\n-\n uint16_t\n hns3_recv_pkts_vec_sve(void *__restrict rx_queue,\n \t\t struct rte_mbuf **__restrict rx_pkts,\n@@ -300,7 +252,7 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue,\n \tnb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_SVE_DEFAULT_DESCS_PER_LOOP);\n \n \tif (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)\n-\t\thns3_rxq_rearm_mbuf_sve(rxq);\n+\t\thns3_rxq_rearm_mbuf(rxq);\n \n \tif (unlikely(!(rxdp->rx.bd_base_info &\n \t\t\trte_cpu_to_le_32(1u << HNS3_RXD_VLD_B))))\n@@ -331,7 +283,7 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue,\n \t\t\tbreak;\n \n \t\tif (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)\n-\t\t\thns3_rxq_rearm_mbuf_sve(rxq);\n+\t\t\thns3_rxq_rearm_mbuf(rxq);\n \t}\n \n \treturn nb_rx;\n", "prefixes": [ "4/5" ] }