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{
    "id": 129445,
    "url": "http://patchwork.dpdk.org/api/patches/129445/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230711102448.11627-3-liudongdong3@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230711102448.11627-3-liudongdong3@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230711102448.11627-3-liudongdong3@huawei.com",
    "date": "2023-07-11T10:24:45",
    "name": "[2/5] net/hns3: fix the order of NEON Rx code",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "9cefb041e029258ed249b61ef32b5cc1e6e74c3b",
    "submitter": {
        "id": 2718,
        "url": "http://patchwork.dpdk.org/api/people/2718/?format=api",
        "name": "Dongdong Liu",
        "email": "liudongdong3@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patchwork.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230711102448.11627-3-liudongdong3@huawei.com/mbox/",
    "series": [
        {
            "id": 28901,
            "url": "http://patchwork.dpdk.org/api/series/28901/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28901",
            "date": "2023-07-11T10:24:43",
            "name": "net/hns3: some performance optimizations",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/28901/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/129445/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/129445/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 72E2D42E44;\n\tTue, 11 Jul 2023 12:28:23 +0200 (CEST)",
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        ],
        "From": "Dongdong Liu <liudongdong3@huawei.com>",
        "To": "<dev@dpdk.org>, <ferruh.yigit@amd.com>, <thomas@monjalon.net>,\n <andrew.rybchenko@oktetlabs.ru>",
        "CC": "<stable@dpdk.org>",
        "Subject": "[PATCH 2/5] net/hns3: fix the order of NEON Rx code",
        "Date": "Tue, 11 Jul 2023 18:24:45 +0800",
        "Message-ID": "<20230711102448.11627-3-liudongdong3@huawei.com>",
        "X-Mailer": "git-send-email 2.22.0",
        "In-Reply-To": "<20230711102448.11627-1-liudongdong3@huawei.com>",
        "References": "<20230711102448.11627-1-liudongdong3@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.28.79.22]",
        "X-ClientProxiedBy": "dggems701-chm.china.huawei.com (10.3.19.178) To\n kwepemi500017.china.huawei.com (7.221.188.110)",
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        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Huisong Li <lihuisong@huawei.com>\n\nThis patch reorders the order of the NEON Rx for better maintenance\nand easier understanding.\n\nFixes: a3d4f4d291d7 (\"net/hns3: support NEON Rx\")\nCc: stable@dpdk.org\n\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\nSigned-off-by: Dongdong Liu <liudongdong3@huawei.com>\n---\n drivers/net/hns3/hns3_rxtx_vec_neon.h | 78 +++++++++++----------------\n 1 file changed, 31 insertions(+), 47 deletions(-)",
    "diff": "diff --git a/drivers/net/hns3/hns3_rxtx_vec_neon.h b/drivers/net/hns3/hns3_rxtx_vec_neon.h\nindex 564d831a48..0dc6b9f0a2 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec_neon.h\n+++ b/drivers/net/hns3/hns3_rxtx_vec_neon.h\n@@ -180,19 +180,12 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq,\n \t\tbd_vld = vset_lane_u16(rxdp[2].rx.bdtype_vld_udp0, bd_vld, 2);\n \t\tbd_vld = vset_lane_u16(rxdp[3].rx.bdtype_vld_udp0, bd_vld, 3);\n \n-\t\t/* load 2 mbuf pointer */\n-\t\tmbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);\n-\n \t\tbd_vld = vshl_n_u16(bd_vld,\n \t\t\t\t    HNS3_UINT16_BIT - 1 - HNS3_RXD_VLD_B);\n \t\tbd_vld = vreinterpret_u16_s16(\n \t\t\t\tvshr_n_s16(vreinterpret_s16_u16(bd_vld),\n \t\t\t\t\t   HNS3_UINT16_BIT - 1));\n \t\tstat = ~vget_lane_u64(vreinterpret_u64_u16(bd_vld), 0);\n-\n-\t\t/* load 2 mbuf pointer again */\n-\t\tmbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);\n-\n \t\tif (likely(stat == 0))\n \t\t\tbd_valid_num = HNS3_DEFAULT_DESCS_PER_LOOP;\n \t\telse\n@@ -200,20 +193,20 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq,\n \t\tif (bd_valid_num == 0)\n \t\t\tbreak;\n \n-\t\t/* use offset to control below data load oper ordering */\n-\t\toffset = rxq->offset_table[bd_valid_num];\n+\t\t/* load 4 mbuf pointer */\n+\t\tmbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);\n+\t\tmbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);\n \n-\t\t/* store 2 mbuf pointer into rx_pkts */\n+\t\t/* store 4 mbuf pointer into rx_pkts */\n \t\tvst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);\n \n-\t\t/* read first two descs */\n+\t\t/* use offset to control below data load oper ordering */\n+\t\toffset = rxq->offset_table[bd_valid_num];\n+\n+\t\t/* read 4 descs */\n \t\tdescs[0] = vld2q_u64((uint64_t *)(rxdp + offset));\n \t\tdescs[1] = vld2q_u64((uint64_t *)(rxdp + offset + 1));\n-\n-\t\t/* store 2 mbuf pointer into rx_pkts again */\n-\t\tvst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);\n-\n-\t\t/* read remains two descs */\n \t\tdescs[2] = vld2q_u64((uint64_t *)(rxdp + offset + 2));\n \t\tdescs[3] = vld2q_u64((uint64_t *)(rxdp + offset + 3));\n \n@@ -221,56 +214,47 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq,\n \t\tpkt_mbuf1.val[1] = vreinterpretq_u8_u64(descs[0].val[1]);\n \t\tpkt_mbuf2.val[0] = vreinterpretq_u8_u64(descs[1].val[0]);\n \t\tpkt_mbuf2.val[1] = vreinterpretq_u8_u64(descs[1].val[1]);\n+\t\tpkt_mbuf3.val[0] = vreinterpretq_u8_u64(descs[2].val[0]);\n+\t\tpkt_mbuf3.val[1] = vreinterpretq_u8_u64(descs[2].val[1]);\n+\t\tpkt_mbuf4.val[0] = vreinterpretq_u8_u64(descs[3].val[0]);\n+\t\tpkt_mbuf4.val[1] = vreinterpretq_u8_u64(descs[3].val[1]);\n \n-\t\t/* pkt 1,2 convert format from desc to pktmbuf */\n+\t\t/* 4 packets convert format from desc to pktmbuf */\n \t\tpkt_mb1 = vqtbl2q_u8(pkt_mbuf1, shuf_desc_fields_msk);\n \t\tpkt_mb2 = vqtbl2q_u8(pkt_mbuf2, shuf_desc_fields_msk);\n+\t\tpkt_mb3 = vqtbl2q_u8(pkt_mbuf3, shuf_desc_fields_msk);\n+\t\tpkt_mb4 = vqtbl2q_u8(pkt_mbuf4, shuf_desc_fields_msk);\n \n-\t\t/* store the first 8 bytes of pkt 1,2 mbuf's rearm_data */\n-\t\t*(uint64_t *)&sw_ring[pos + 0].mbuf->rearm_data =\n-\t\t\trxq->mbuf_initializer;\n-\t\t*(uint64_t *)&sw_ring[pos + 1].mbuf->rearm_data =\n-\t\t\trxq->mbuf_initializer;\n-\n-\t\t/* pkt 1,2 remove crc */\n+\t\t/* 4 packets remove crc */\n \t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);\n \t\tpkt_mb1 = vreinterpretq_u8_u16(tmp);\n \t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);\n \t\tpkt_mb2 = vreinterpretq_u8_u16(tmp);\n+\t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);\n+\t\tpkt_mb3 = vreinterpretq_u8_u16(tmp);\n+\t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);\n+\t\tpkt_mb4 = vreinterpretq_u8_u16(tmp);\n \n-\t\tpkt_mbuf3.val[0] = vreinterpretq_u8_u64(descs[2].val[0]);\n-\t\tpkt_mbuf3.val[1] = vreinterpretq_u8_u64(descs[2].val[1]);\n-\t\tpkt_mbuf4.val[0] = vreinterpretq_u8_u64(descs[3].val[0]);\n-\t\tpkt_mbuf4.val[1] = vreinterpretq_u8_u64(descs[3].val[1]);\n-\n-\t\t/* pkt 3,4 convert format from desc to pktmbuf */\n-\t\tpkt_mb3 = vqtbl2q_u8(pkt_mbuf3, shuf_desc_fields_msk);\n-\t\tpkt_mb4 = vqtbl2q_u8(pkt_mbuf4, shuf_desc_fields_msk);\n-\n-\t\t/* pkt 1,2 save to rx_pkts mbuf */\n+\t\t/* save packet info to rx_pkts mbuf */\n \t\tvst1q_u8((void *)&sw_ring[pos + 0].mbuf->rx_descriptor_fields1,\n \t\t\t pkt_mb1);\n \t\tvst1q_u8((void *)&sw_ring[pos + 1].mbuf->rx_descriptor_fields1,\n \t\t\t pkt_mb2);\n+\t\tvst1q_u8((void *)&sw_ring[pos + 2].mbuf->rx_descriptor_fields1,\n+\t\t\t pkt_mb3);\n+\t\tvst1q_u8((void *)&sw_ring[pos + 3].mbuf->rx_descriptor_fields1,\n+\t\t\t pkt_mb4);\n \n-\t\t/* pkt 3,4 remove crc */\n-\t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);\n-\t\tpkt_mb3 = vreinterpretq_u8_u16(tmp);\n-\t\ttmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);\n-\t\tpkt_mb4 = vreinterpretq_u8_u16(tmp);\n-\n-\t\t/* store the first 8 bytes of pkt 3,4 mbuf's rearm_data */\n+\t\t/* store the first 8 bytes of packets mbuf's rearm_data */\n+\t\t*(uint64_t *)&sw_ring[pos + 0].mbuf->rearm_data =\n+\t\t\trxq->mbuf_initializer;\n+\t\t*(uint64_t *)&sw_ring[pos + 1].mbuf->rearm_data =\n+\t\t\trxq->mbuf_initializer;\n \t\t*(uint64_t *)&sw_ring[pos + 2].mbuf->rearm_data =\n \t\t\trxq->mbuf_initializer;\n \t\t*(uint64_t *)&sw_ring[pos + 3].mbuf->rearm_data =\n \t\t\trxq->mbuf_initializer;\n \n-\t\t/* pkt 3,4 save to rx_pkts mbuf */\n-\t\tvst1q_u8((void *)&sw_ring[pos + 2].mbuf->rx_descriptor_fields1,\n-\t\t\t pkt_mb3);\n-\t\tvst1q_u8((void *)&sw_ring[pos + 3].mbuf->rx_descriptor_fields1,\n-\t\t\t pkt_mb4);\n-\n \t\trte_prefetch_non_temporal(rxdp + HNS3_DEFAULT_DESCS_PER_LOOP);\n \n \t\tparse_retcode = hns3_desc_parse_field(rxq, &sw_ring[pos],\n",
    "prefixes": [
        "2/5"
    ]
}