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{
    "id": 129493,
    "url": "http://patchwork.dpdk.org/api/patches/129493/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230712074215.3249336-4-qiming.yang@intel.com/",
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        "name": "DPDK",
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        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
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    "msgid": "<20230712074215.3249336-4-qiming.yang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230712074215.3249336-4-qiming.yang@intel.com",
    "date": "2023-07-12T07:42:15",
    "name": "[3/3] net/e1000: fix Rx and Tx queue status",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "079bc645da1634f997ff702df4bcefc49df022cc",
    "submitter": {
        "id": 522,
        "url": "http://patchwork.dpdk.org/api/people/522/?format=api",
        "name": "Qiming Yang",
        "email": "qiming.yang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patchwork.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230712074215.3249336-4-qiming.yang@intel.com/mbox/",
    "series": [
        {
            "id": 28918,
            "url": "http://patchwork.dpdk.org/api/series/28918/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28918",
            "date": "2023-07-12T07:42:12",
            "name": "fix Rx and Tx queue status get",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/28918/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/129493/comments/",
    "check": "fail",
    "checks": "http://patchwork.dpdk.org/api/patches/129493/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        ],
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        "X-ExtLoop1": "1",
        "From": "Qiming Yang <qiming.yang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "beilei.xing@intel.com, qi.z.zhang@intel.com,\n Qiming Yang <qiming.yang@intel.com>, Mingjin Ye <mingjinx.ye@intel.com>",
        "Subject": "[PATCH 3/3] net/e1000: fix Rx and Tx queue status",
        "Date": "Wed, 12 Jul 2023 07:42:15 +0000",
        "Message-Id": "<20230712074215.3249336-4-qiming.yang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20230712074215.3249336-1-qiming.yang@intel.com>",
        "References": "<20230712074215.3249336-1-qiming.yang@intel.com>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Igb driver don't enable queue start/stop functions, queue status is not\nupdated when the HW queue enabled or disabled. It caused application can't\nget correct queue status.\nThis patch fixes the issue by updating the queue states when the queue is\ndisabled or enabled.\n\nFixes: be2d648a2dd3 (\"igb: add PF support\")\n\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\nSigned-off-by: Mingjin Ye <mingjinx.ye@intel.com>\n---\n drivers/net/e1000/igb_rxtx.c | 4 ++++\n 1 file changed, 4 insertions(+)",
    "diff": "diff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c\nindex 25ad9eb4e5..61c6394310 100644\n--- a/drivers/net/e1000/igb_rxtx.c\n+++ b/drivers/net/e1000/igb_rxtx.c\n@@ -1854,6 +1854,7 @@ igb_dev_clear_queues(struct rte_eth_dev *dev)\n \t\tif (txq != NULL) {\n \t\t\tigb_tx_queue_release_mbufs(txq);\n \t\t\tigb_reset_tx_queue(txq, dev);\n+\t\t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n \t\t}\n \t}\n \n@@ -1862,6 +1863,7 @@ igb_dev_clear_queues(struct rte_eth_dev *dev)\n \t\tif (rxq != NULL) {\n \t\t\tigb_rx_queue_release_mbufs(rxq);\n \t\t\tigb_reset_rx_queue(rxq);\n+\t\t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n \t\t}\n \t}\n }\n@@ -2442,6 +2444,7 @@ eth_igb_rx_init(struct rte_eth_dev *dev)\n \t\trxdctl |= ((rxq->hthresh & 0x1F) << 8);\n \t\trxdctl |= ((rxq->wthresh & 0x1F) << 16);\n \t\tE1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);\n+\t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n \t}\n \n \tif (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) {\n@@ -2606,6 +2609,7 @@ eth_igb_tx_init(struct rte_eth_dev *dev)\n \t\ttxdctl |= ((txq->wthresh & 0x1F) << 16);\n \t\ttxdctl |= E1000_TXDCTL_QUEUE_ENABLE;\n \t\tE1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);\n+\t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n \t}\n \n \t/* Program the Transmit Control Register. */\n",
    "prefixes": [
        "3/3"
    ]
}