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GET /api/patches/129496/?format=api
{ "id": 129496, "url": "http://patchwork.dpdk.org/api/patches/129496/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230712083153.3250798-3-qiming.yang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230712083153.3250798-3-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230712083153.3250798-3-qiming.yang@intel.com", "date": "2023-07-12T08:31:52", "name": "[v2,2/3] net/igc: fix Rx and Tx queue status get", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5c736e70761f6e4b527427be37004ac35c01e69b", "submitter": { "id": 522, "url": "http://patchwork.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230712083153.3250798-3-qiming.yang@intel.com/mbox/", "series": [ { "id": 28919, "url": "http://patchwork.dpdk.org/api/series/28919/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=28919", "date": "2023-07-12T08:31:50", "name": "fix Rx and Tx queue status get", "version": 2, "mbox": "http://patchwork.dpdk.org/series/28919/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129496/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/129496/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9059842E52;\n\tWed, 12 Jul 2023 10:50:03 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9BAE142B8E;\n\tWed, 12 Jul 2023 10:50:00 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id B26A2427EE;\n Wed, 12 Jul 2023 10:49:57 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Jul 2023 01:49:33 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga001.fm.intel.com with ESMTP; 12 Jul 2023 01:49:32 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1689151799; x=1720687799;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=1lUAwfe/IJgchFBu0N8bXaeZwmFbfVjcY6RfR5TJwW4=;\n b=NrkTde/8+a932uEKph32OMi6xD31Hs4eyHEGgiEXiizMXjjyCg7SgcCc\n P5T/CpIvekGknB9ZO3HRhsnR/KfgvAqd7liqSyP+lnC8iGQ+2zqqF9NUt\n 58H58JALKkQoYfTckxQRjtNq5m3w74kWmlWdBm8M+ryqaWM3FWSWqVxWn\n PvS9zn4iAj7wgQtVkgQQOvBWbY2CYGbqcYYXutrq+n2RUiuCyBQrqKw2y\n n+sUg/d5pm5KrotRnAOA3n/jCHJd/F4DlaOoEbp3dVccZMG4GeCWjfjfm\n KYnCoDUGkcVD4mfoRadrnEoYAbUh2hxJHWAY+N1aTurVZNBmbnW8aXZ82 A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10768\"; a=\"345152458\"", "E=Sophos;i=\"6.01,199,1684825200\"; d=\"scan'208\";a=\"345152458\"", "E=McAfee;i=\"6600,9927,10768\"; a=\"866036713\"", "E=Sophos;i=\"6.01,199,1684825200\"; d=\"scan'208\";a=\"866036713\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "beilei.xing@intel.com, qi.z.zhang@intel.com,\n Qiming Yang <qiming.yang@intel.com>, stable@dpdk.org,\n Mingjin Ye <mingjinx.ye@intel.com>", "Subject": "[PATCH v2 2/3] net/igc: fix Rx and Tx queue status get", "Date": "Wed, 12 Jul 2023 08:31:52 +0000", "Message-Id": "<20230712083153.3250798-3-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230712083153.3250798-1-qiming.yang@intel.com>", "References": "<20230712083153.3250798-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Igc driver don't enable queue start/stop functions, queue status is not\nupdated when the HW queue enabled or disabled. It caused application can't\nget correct queue status.\nThis patch fixes the issue by updating the queue states when the queue is\ndisabled or enabled.\n\nFixes: a5aeb2b9e225 (\"net/igc: support Rx and Tx\")\nCc: stable@dpdk.org\n\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\nSigned-off-by: Mingjin Ye <mingjinx.ye@intel.com>\n---\n drivers/net/igc/igc_txrx.c | 4 ++++\n 1 file changed, 4 insertions(+)", "diff": "diff --git a/drivers/net/igc/igc_txrx.c b/drivers/net/igc/igc_txrx.c\nindex c11b6f7f25..5c60e3e997 100644\n--- a/drivers/net/igc/igc_txrx.c\n+++ b/drivers/net/igc/igc_txrx.c\n@@ -1215,6 +1215,7 @@ igc_rx_init(struct rte_eth_dev *dev)\n \t\t\tdvmolr |= IGC_DVMOLR_STRCRC;\n \n \t\tIGC_WRITE_REG(hw, IGC_DVMOLR(rxq->reg_idx), dvmolr);\n+\t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n \t}\n \n \treturn 0;\n@@ -1888,6 +1889,7 @@ igc_dev_clear_queues(struct rte_eth_dev *dev)\n \t\tif (txq != NULL) {\n \t\t\tigc_tx_queue_release_mbufs(txq);\n \t\t\tigc_reset_tx_queue(txq);\n+\t\t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n \t\t}\n \t}\n \n@@ -1896,6 +1898,7 @@ igc_dev_clear_queues(struct rte_eth_dev *dev)\n \t\tif (rxq != NULL) {\n \t\t\tigc_rx_queue_release_mbufs(rxq);\n \t\t\tigc_reset_rx_queue(rxq);\n+\t\t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n \t\t}\n \t}\n }\n@@ -2143,6 +2146,7 @@ igc_tx_init(struct rte_eth_dev *dev)\n \t\t\t\tIGC_TXDCTL_WTHRESH_MSK;\n \t\ttxdctl |= IGC_TXDCTL_QUEUE_ENABLE;\n \t\tIGC_WRITE_REG(hw, IGC_TXDCTL(txq->reg_idx), txdctl);\n+\t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n \t}\n \n \tif (offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) {\n", "prefixes": [ "v2", "2/3" ] }