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GET /api/patches/129825/?format=api
{ "id": 129825, "url": "http://patchwork.dpdk.org/api/patches/129825/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230802081106.2340406-6-caowenbo@mucse.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230802081106.2340406-6-caowenbo@mucse.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230802081106.2340406-6-caowenbo@mucse.com", "date": "2023-08-02T08:11:03", "name": "[v2,5/8] net/rnp add reset code for Chip Init process", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8261db48642117084ad5287f7aeab319fe84a6e6", "submitter": { "id": 2142, "url": "http://patchwork.dpdk.org/api/people/2142/?format=api", "name": "11", "email": "caowenbo@mucse.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230802081106.2340406-6-caowenbo@mucse.com/mbox/", "series": [ { "id": 29092, "url": "http://patchwork.dpdk.org/api/series/29092/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29092", "date": "2023-08-02T08:10:58", "name": "*** Add Support New Pmd Driver ***", "version": 2, "mbox": "http://patchwork.dpdk.org/series/29092/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129825/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/129825/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E3AB042FB8;\n\tWed, 2 Aug 2023 10:13:03 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6F2EA43267;\n\tWed, 2 Aug 2023 10:12:53 +0200 (CEST)", "from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130])\n by mails.dpdk.org (Postfix) with ESMTP id D31AD410DC\n for <dev@dpdk.org>; Wed, 2 Aug 2023 10:12:51 +0200 (CEST)", "from steven.localdomain ( [183.81.182.182])\n by bizesmtp.qq.com (ESMTP) with\n id ; Wed, 02 Aug 2023 16:12:39 +0800 (CST)" ], "X-QQ-mid": "bizesmtp91t1690963962tcm3bqv4", "X-QQ-SSF": "01400000000000D0E000000B0000000", "X-QQ-FEAT": "DJycbILCmkba1JfDi3ogxOmnnBdlID2RHO3F4LWvVsjjo+81FhLWZ4qkgNMeH\n JvVlPfqkDpfSNzUvg9pJC7Ra+umTNuvHRUAC6UDVUJyycNEtt5OM+7PermZTvZivvooEt6C\n dL4cUChnrsccpRj0dwHsnz7uRqNFhrmGoKFhGOnEqLA8VxYyrbt0v2JqUvChzKnAywUiPa6\n P+dx3nuyGXx/MO81spEPtsAPkNkBd8hwUbDRZr/s6YwYdj97h0CJCJaD9UcQx7vIqXBhTp9\n 3W4xb92MqDgXix+cqrI06iUX1E4tfx7wb/PkrW0eKEY2H+mPMa7fDIWO/GvAW4FrLtns1hL\n xMpZPw/qOrOCLjG+A9zZwFaIaIn21OHeQrz6X9pE+3b4v85/jDOkPiHq3Sng9NbyjNNQfFd\n kMVG7yeFUTg=", "X-QQ-GoodBg": "2", "X-BIZMAIL-ID": "16232346795387656203", "From": "Wenbo Cao <caowenbo@mucse.com>", "To": "Wenbo Cao <caowenbo@mucse.com>", "Cc": "dev@dpdk.org,\n\tferruh.yigit@intel.com,\n\tandrew.rybchenko@oktetlabs.ru", "Subject": "[PATCH v2 5/8] net/rnp add reset code for Chip Init process", "Date": "Wed, 2 Aug 2023 08:11:03 +0000", "Message-Id": "<20230802081106.2340406-6-caowenbo@mucse.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230802081106.2340406-1-caowenbo@mucse.com>", "References": "<20230802081106.2340406-1-caowenbo@mucse.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:mucse.com:qybglogicsvrgz:qybglogicsvrgz5a-0", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "we must get the shape info of nic from Firmware for\nreset. so the related codes is first get firmware info\nand then reset the chip\n\nSigned-off-by: Wenbo Cao <caowenbo@mucse.com>\n---\n drivers/net/rnp/base/rnp_api.c | 23 +++\n drivers/net/rnp/base/rnp_api.h | 7 +\n drivers/net/rnp/base/rnp_cfg.h | 7 +\n drivers/net/rnp/base/rnp_dma_regs.h | 73 ++++++++\n drivers/net/rnp/base/rnp_eth_regs.h | 124 +++++++++++++\n drivers/net/rnp/base/rnp_hw.h | 46 +++++\n drivers/net/rnp/meson.build | 3 +\n drivers/net/rnp/rnp.h | 28 ++-\n drivers/net/rnp/rnp_ethdev.c | 93 +++++++++-\n drivers/net/rnp/rnp_mbx_fw.c | 272 ++++++++++++++++++++++++++++\n drivers/net/rnp/rnp_mbx_fw.h | 163 ++++++++++++++++-\n 11 files changed, 836 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/rnp/base/rnp_api.c\n create mode 100644 drivers/net/rnp/base/rnp_api.h\n create mode 100644 drivers/net/rnp/base/rnp_cfg.h\n create mode 100644 drivers/net/rnp/base/rnp_dma_regs.h\n create mode 100644 drivers/net/rnp/base/rnp_eth_regs.h\n create mode 100644 drivers/net/rnp/rnp_mbx_fw.c", "diff": "diff --git a/drivers/net/rnp/base/rnp_api.c b/drivers/net/rnp/base/rnp_api.c\nnew file mode 100644\nindex 0000000000..550da6217d\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_api.c\n@@ -0,0 +1,23 @@\n+#include \"rnp.h\"\n+#include \"rnp_api.h\"\n+\n+int\n+rnp_init_hw(struct rte_eth_dev *dev)\n+{\n+\tconst struct rnp_mac_api *ops = RNP_DEV_TO_MAC_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\n+\tif (ops->init_hw)\n+\t\treturn ops->init_hw(hw);\n+\treturn -EOPNOTSUPP;\n+}\n+\n+int\n+rnp_reset_hw(struct rte_eth_dev *dev, struct rnp_hw *hw)\n+{\n+\tconst struct rnp_mac_api *ops = RNP_DEV_TO_MAC_OPS(dev);\n+\n+\tif (ops->reset_hw)\n+\t\treturn ops->reset_hw(hw);\n+\treturn -EOPNOTSUPP;\n+}\ndiff --git a/drivers/net/rnp/base/rnp_api.h b/drivers/net/rnp/base/rnp_api.h\nnew file mode 100644\nindex 0000000000..df574dab77\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_api.h\n@@ -0,0 +1,7 @@\n+#ifndef __RNP_API_H__\n+#define __RNP_API_H__\n+int\n+rnp_init_hw(struct rte_eth_dev *dev);\n+int\n+rnp_reset_hw(struct rte_eth_dev *dev, struct rnp_hw *hw);\n+#endif /* __RNP_API_H__ */\ndiff --git a/drivers/net/rnp/base/rnp_cfg.h b/drivers/net/rnp/base/rnp_cfg.h\nnew file mode 100644\nindex 0000000000..90f25268ad\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_cfg.h\n@@ -0,0 +1,7 @@\n+#ifndef __RNP_CFG_H__\n+#define __RNP_CFG_H__\n+#include \"rnp_osdep.h\"\n+\n+#define RNP_NIC_RESET\t\t_NIC_(0x0010)\n+#define RNP_TX_QINQ_WORKAROUND\t_NIC_(0x801c)\n+#endif /* __RNP_CFG_H__ */\ndiff --git a/drivers/net/rnp/base/rnp_dma_regs.h b/drivers/net/rnp/base/rnp_dma_regs.h\nnew file mode 100644\nindex 0000000000..bfe87e534d\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_dma_regs.h\n@@ -0,0 +1,73 @@\n+#ifndef __RNP_REGS_H__\n+#define __RNP_REGS_H__\n+\n+#include \"rnp_osdep.h\"\n+\n+/* mac address offset */\n+#define RNP_DMA_CTRL\t\t\t\t(0x4)\n+#define RNP_VEB_BYPASS_EN\t\t\tBIT(4)\n+#define RNP_DMA_MEM_CFG_LE\t\t\t(0 << 5)\n+#define TSNR10_DMA_MEM_CFG_BE\t\t\t(1 << 5)\n+#define RNP_DMA_SCATTER_MEM_SHIFT\t\t(16)\n+\n+#define RNP_FIRMWARE_SYNC\t\t\t(0xc)\n+#define RNP_FIRMWARE_SYNC_MASK\t\t\tGENMASK(31, 16)\n+#define RNP_FIRMWARE_SYNC_MAGIC\t\t\t(0xa5a40000)\n+#define RNP_DRIVER_REMOVE\t\t\t(0x5a000000)\n+/* 1BIT <-> 16 bytes Dma Addr Size*/\n+#define RNP_DMA_SCATTER_MEM_MASK\t\tGENMASK(31, 16)\n+#define RNP_DMA_TX_MAP_MODE_SHIFT\t\t(12)\n+#define RNP_DMA_TX_MAP_MODE_MASK\t\tGENMASK(15, 12)\n+#define RNP_DMA_RX_MEM_PAD_EN\t\t\tBIT(8)\n+/* === queue register ===== */\n+/* enable */\n+#define RNP_DMA_RXQ_START(qid)\t\t\t_RING_(0x0010 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_READY(qid)\t\t\t_RING_(0x0014 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_START(qid)\t\t\t_RING_(0x0018 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_READY(qid)\t\t\t_RING_(0x001c + 0x100 * (qid))\n+\n+#define RNP_DMA_INT_STAT(qid)\t\t\t_RING_(0x0020 + 0x100 * (qid))\n+#define RNP_DMA_INT_MASK(qid)\t\t\t_RING_(0x0024 + 0x100 * (qid))\n+#define RNP_TX_INT_MASK\t\t\t\tBIT(1)\n+#define RNP_RX_INT_MASK\t\t\t\tBIT(0)\n+#define RNP_DMA_INT_CLER(qid)\t\t\t_RING_(0x0028 + 0x100 * (qid))\n+\n+/* rx-queue */\n+#define RNP_DMA_RXQ_BASE_ADDR_HI(qid)\t\t_RING_(0x0030 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_BASE_ADDR_LO(qid)\t\t_RING_(0x0034 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_LEN(qid)\t\t\t_RING_(0x0038 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_HEAD(qid)\t\t\t_RING_(0x003c + 0x100 * (qid))\n+#define RNP_DMA_RXQ_TAIL(qid)\t\t\t_RING_(0x0040 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_DESC_FETCH_CTRL(qid)\t_RING_(0x0044 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_INT_DELAY_TIMER(qid)\t_RING_(0x0048 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_INT_DELAY_PKTCNT(qidx)\t_RING_(0x004c + 0x100 * (qid))\n+#define RNP_DMA_RXQ_RX_PRI_LVL(qid)\t\t_RING_(0x0050 + 0x100 * (qid))\n+#define RNP_DMA_RXQ_DROP_TIMEOUT_TH(qid)\t_RING_(0x0054 + 0x100 * (qid))\n+/* tx-queue */\n+#define RNP_DMA_TXQ_BASE_ADDR_HI(qid)\t\t_RING_(0x0060 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_BASE_ADDR_LO(qid)\t\t_RING_(0x0064 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_LEN(qid)\t\t\t_RING_(0x0068 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_HEAD(qid)\t\t\t_RING_(0x006c + 0x100 * (qid))\n+#define RNP_DMA_TXQ_TAIL(qid)\t\t\t_RING_(0x0070 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_DESC_FETCH_CTRL(qid)\t_RING_(0x0074 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_INT_DELAY_TIMER(qid)\t_RING_(0x0078 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_INT_DELAY_PKTCNT(qid)\t_RING_(0x007c + 0x100 * (qid))\n+\n+#define RNP_DMA_TXQ_PRI_LVL(qid)\t\t_RING_(0x0080 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_RATE_CTRL_TH(qid)\t\t_RING_(0x0084 + 0x100 * (qid))\n+#define RNP_DMA_TXQ_RATE_CTRL_TM(qid)\t\t_RING_(0x0088 + 0x100 * (qid))\n+\n+/* VEB Table Register */\n+#define RNP_VBE_MAC_LO(port, nr)\t\t_RING_(0x00a0 + (4 * (port)) + \\\n+\t\t\t\t\t\t(0x100 * (nr)))\n+#define RNP_VBE_MAC_HI(port, nr)\t\t_RING_(0x00b0 + (4 * (port)) + \\\n+\t\t\t\t\t\t(0x100 * (nr)))\n+#define RNP_VEB_VID_CFG(port, nr)\t\t_RING_(0x00c0 + (4 * (port)) + \\\n+\t\t\t\t\t\t(0x100 * (nr)))\n+#define RNP_VEB_VF_RING(port, nr)\t\t_RING_(0x00d0 + (4 * (port)) + \\\n+\t\t\t\t\t\t(0x100 * (nr)))\n+#define RNP_MAX_VEB_TB\t\t\t\t(64)\n+#define RNP_VEB_RING_CFG_OFFSET\t\t\t(8)\n+#define RNP_VEB_SWITCH_VF_EN\t\t\tBIT(7)\n+#define MAX_VEB_TABLES_NUM\t\t\t(4)\n+#endif /* RNP_DMA_REGS_H_ */\ndiff --git a/drivers/net/rnp/base/rnp_eth_regs.h b/drivers/net/rnp/base/rnp_eth_regs.h\nnew file mode 100644\nindex 0000000000..88e8e1e552\n--- /dev/null\n+++ b/drivers/net/rnp/base/rnp_eth_regs.h\n@@ -0,0 +1,124 @@\n+#ifndef _RNP_ETH_REGS_H_\n+#define _RNP_ETH_REGS_H_\n+\n+#include \"rnp_osdep.h\"\n+\n+/* PTP 1588 TM Offload */\n+#define RNP_ETH_PTP_TX_STATUS(n)\t_ETH_(0x0400 + ((n) * 0x14))\n+#define RNP_ETH_PTP_TX_HTIMES(n)\t_ETH_(0x0404 + ((n) * 0x14))\n+#define RNP_ETH_PTP_TX_LTIMES(n)\t_ETH_(0x0408 + ((n) * 0x14))\n+#define RNP_ETH_PTP_TX_TS_ST(n)\t\t_ETH_(0x040c + ((n) * 0x14))\n+#define RNP_ETH_PTP_TX_CLEAR(n)\t\t_ETH_(0x0410 + ((n) * 0x14))\n+\n+#define RNP_ETH_ENGINE_BYPASS\t\t_ETH_(0x8000)\n+#define RNP_EN_TUNNEL_VXLAN_PARSE\t_ETH_(0x8004)\n+#define RNP_ETH_MAC_LOOPBACK\t\t_ETH_(0x8008)\n+#define RNP_ETH_FIFO_CTRL\t\t_ETH_(0x800c)\n+#define RNP_ETH_FOUR_FIFO\t\tBIT(0)\n+#define RNP_ETH_TWO_FIFO\t\tBIT(1)\n+#define RNP_ETH_ONE_FIFO\t\tBIT(2)\n+#define RNP_FIFO_CFG_EN\t\t\t(0x1221)\n+#define RNP_ETH_VXLAN_PORT_CTRL\t\t_ETH_(0x8010)\n+#define RNP_ETH_VXLAN_DEF_PORT\t\t(4789)\n+#define RNP_HOST_FILTER_EN\t\t_ETH_(0x801c)\n+#define RNP_HW_SCTP_CKSUM_CTRL\t\t_ETH_(0x8038)\n+#define RNP_HW_CHECK_ERR_CTRL\t\t_ETH_(0x8060)\n+#define RNP_HW_ERR_HDR_LEN\t\tBIT(0)\n+#define RNP_HW_ERR_PKTLEN\t\tBIT(1)\n+#define RNP_HW_L3_CKSUM_ERR\t\tBIT(2)\n+#define RNP_HW_L4_CKSUM_ERR\t\tBIT(3)\n+#define RNP_HW_SCTP_CKSUM_ERR\t\tBIT(4)\n+#define RNP_HW_INNER_L3_CKSUM_ERR\tBIT(5)\n+#define RNP_HW_INNER_L4_CKSUM_ERR\tBIT(6)\n+#define RNP_HW_CKSUM_ERR_MASK\t\tGENMASK(6, 2)\n+#define RNP_HW_CHECK_ERR_MASK\t\tGENMASK(6, 0)\n+#define RNP_HW_ERR_RX_ALL_MASK\t\tGENMASK(1, 0)\n+\n+#define RNP_REDIR_CTRL\t\t\t_ETH_(0x8030)\n+#define RNP_VLAN_Q_STRIP_CTRL(n)\t_ETH_(0x8040 + 0x4 * ((n) / 32))\n+/* This Just VLAN Master Switch */\n+#define RNP_VLAN_TUNNEL_STRIP_EN\t_ETH_(0x8050)\n+#define RNP_VLAN_TUNNEL_STRIP_MODE\t_ETH_(0x8054)\n+#define RNP_VLAN_TUNNEL_STRIP_OUTER\t(0)\n+#define RNP_VLAN_TUNNEL_STRIP_INNER\t(1)\n+#define RNP_RSS_INNER_CTRL\t\t_ETH_(0x805c)\n+#define RNP_INNER_RSS_EN\t\t(1)\n+\n+#define RNP_ETH_DEFAULT_RX_RING\t\t_ETH_(0x806c)\n+#define RNP_RX_FC_HI_WATER(n)\t\t_ETH_(0x80c0 + ((n) * 0x8))\n+#define RNP_RX_FC_LO_WATER(n)\t\t_ETH_(0x80c4 + ((n) * 0x8))\n+\n+#define RNP_RX_FIFO_FULL_THRETH(n)\t_ETH_(0x8070 + ((n) * 0x8))\n+#define RNP_RX_WORKAROUND_VAL\t\t_ETH_(0x7ff)\n+#define RNP_RX_DEFAULT_VAL\t\t_ETH_(0x270)\n+\n+#define RNP_MIN_FRAME_CTRL\t\t_ETH_(0x80f0)\n+#define RNP_MAX_FRAME_CTRL\t\t_ETH_(0x80f4)\n+\n+#define RNP_RX_FC_ENABLE\t\t_ETH_(0x8520)\n+#define RNP_RING_FC_EN(n)\t\t_ETH_(0x8524 + 0x4 * ((n) / 32))\n+#define RNP_RING_FC_THRESH(n)\t\t_ETH_(0x8a00 + 0x4 * (n))\n+\n+/* Mac Host Filter */\n+#define RNP_MAC_FCTRL\t\t\t_ETH_(0x9110)\n+#define RNP_MAC_FCTRL_MPE\t\tBIT(8)\t/* Multicast Promiscuous En */\n+#define RNP_MAC_FCTRL_UPE\t\tBIT(9)\t/* Unicast Promiscuous En */\n+#define RNP_MAC_FCTRL_BAM\t\tBIT(10) /* Broadcast Accept Mode */\n+#define RNP_MAC_FCTRL_BYPASS\t\t(RNP_MAC_FCTRL_MPE | \\\n+\t\t\t\t\tRNP_MAC_FCTRL_UPE | \\\n+\t\t\t\t\tRNP_MAC_FCTRL_BAM)\n+/* MC UC Mac Hash Filter Ctrl */\n+#define RNP_MAC_MCSTCTRL\t\t_ETH_(0x9114)\n+#define RNP_MAC_HASH_MASK\t\tGENMASK(11, 0)\n+#define RNP_MAC_MULTICASE_TBL_EN\tBIT(2)\n+#define RNP_MAC_UNICASE_TBL_EN\t\tBIT(3)\n+#define RNP_UC_HASH_TB(n)\t\t_ETH_(0xA800 + ((n) * 0x4))\n+#define RNP_MC_HASH_TB(n)\t\t_ETH_(0xAC00 + ((n) * 0x4))\n+\n+#define RNP_VLAN_FILTER_CTRL\t\t_ETH_(0x9118)\n+#define RNP_L2TYPE_FILTER_CTRL\t\t(RNP_VLAN_FILTER_CTRL)\n+#define RNP_L2TYPE_FILTER_EN\t\tBIT(31)\n+#define RNP_VLAN_FILTER_EN\t\tBIT(30)\n+\n+#define RNP_FC_PAUSE_FWD_ACT\t\t_ETH_(0x9280)\n+#define RNP_FC_PAUSE_DROP\t\tBIT(31)\n+#define RNP_FC_PAUSE_PASS\t\t(0)\n+#define RNP_FC_PAUSE_TYPE\t\t_ETH_(0x9284)\n+#define RNP_FC_PAUSE_POLICY_EN\t\tBIT(31)\n+#define RNP_PAUSE_TYPE\t\t\t_ETH_(0x8808)\n+\n+#define RNP_INPUT_USE_CTRL\t\t_ETH_(0x91d0)\n+#define RNP_INPUT_VALID_MASK\t\t(0xf)\n+#define RNP_INPUT_POLICY(n)\t\t_ETH_(0x91e0 + ((n) * 0x4))\n+/* RSS */\n+#define RNP_RSS_MRQC_ADDR\t\t_ETH_(0x92a0)\n+#define RNP_SRIOV_CTRL\t\t\tRNP_RSS_MRQC_ADDR\n+#define RNP_SRIOV_ENABLE\t\tBIT(3)\n+\n+#define RNP_RSS_REDIR_TB(mac, idx)\t_ETH_(0xe000 + \\\n+\t\t((mac) * 0x200) + ((idx) * 0x4))\n+#define RNP_RSS_KEY_TABLE(idx)\t\t_ETH_(0x92d0 + ((idx) * 0x4))\n+/*=======================================================================\n+ *HOST_MAC_ADDRESS_FILTER\n+ *=======================================================================\n+ */\n+#define RNP_RAL_BASE_ADDR(vf_id)\t_ETH_(0xA000 + 0x04 * (vf_id))\n+#define RNP_RAH_BASE_ADDR(vf_id)\t_ETH_(0xA400 + 0x04 * (vf_id))\n+#define RNP_MAC_FILTER_EN\t\tBIT(31)\n+\n+/* ETH Statistic */\n+#define RNP_ETH_RXTRANS_DROP(p_id)\t_ETH_((0x8904) + ((p_id) * (0x40)))\n+#define RNP_ETH_RXTRANS_CAT_ERR(p_id)\t_ETH_((0x8928) + ((p_id) * (0x40)))\n+#define RNP_ETH_TXTM_DROP\t\t_ETH_(0X0470)\n+\n+#define RNP_VFTA_BASE_ADDR\t\t_ETH_(0xB000)\n+#define RNP_VFTA_HASH_TABLE(id)\t\t(RNP_VFTA_BASE_ADDR + 0x4 * (id))\n+#define RNP_ETYPE_BASE_ADDR\t\t_ETH_(0xB300)\n+#define RNP_MPSAR_BASE_ADDR(vf_id)\t_ETH_(0xB400 + 0x04 * (vf_id))\n+#define RNP_PFVLVF_BASE_ADDR\t\t_ETH_(0xB600)\n+#define RNP_PFVLVFB_BASE_ADDR\t\t_ETH_(0xB700)\n+#define RNP_TUNNEL_PFVLVF_BASE_ADDR\t_ETH_(0xB800)\n+#define RNP_TUNNEL_PFVLVFB_BASE_ADDR\t_ETH_(0xB900)\n+\n+#define RNP_TC_PORT_MAP_TB(port)\t_ETH_(0xe840 + 0x04 * (port))\n+#endif /* RNP_ETH_REGS_H_ */\ndiff --git a/drivers/net/rnp/base/rnp_hw.h b/drivers/net/rnp/base/rnp_hw.h\nindex da3659bd67..03381ab6d0 100644\n--- a/drivers/net/rnp/base/rnp_hw.h\n+++ b/drivers/net/rnp/base/rnp_hw.h\n@@ -8,6 +8,9 @@\n #include <ethdev_driver.h>\n \n #include \"rnp_osdep.h\"\n+#include \"rnp_dma_regs.h\"\n+#include \"rnp_eth_regs.h\"\n+#include \"rnp_cfg.h\"\n \n static inline unsigned int rnp_rd_reg(volatile void *addr)\n {\n@@ -24,6 +27,9 @@ static inline void rnp_wr_reg(volatile void *reg, int val)\n #define mbx_rd32(hw, reg)\trnp_rd_reg((hw)->iobar4 + (reg))\n #define mbx_wr32(hw, reg, val)\trnp_wr_reg((hw)->iobar4 + (reg), (val))\n \n+#define rnp_eth_rd(hw, off)\trnp_rd_reg((char *)(hw)->eth_base + (off))\n+#define rnp_eth_wr(hw, off, val) \\\n+\trnp_wr_reg((char *)(hw)->eth_base + (off), val)\n struct rnp_hw;\n /* Mbx Operate info */\n enum MBX_ID {\n@@ -93,6 +99,17 @@ struct rnp_mbx_info {\n \trte_atomic16_t state;\n } __rte_cache_aligned;\n \n+struct rnp_mac_api {\n+\tint32_t (*init_hw)(struct rnp_hw *hw);\n+\tint32_t (*reset_hw)(struct rnp_hw *hw);\n+};\n+\n+struct rnp_mac_info {\n+\tuint8_t assign_addr[RTE_ETHER_ADDR_LEN];\n+\tuint8_t set_addr[RTE_ETHER_ADDR_LEN];\n+\tstruct rnp_mac_api ops;\n+} __rte_cache_aligned;\n+\n #define RNP_MAX_HW_PORT_PERR_PF (4)\n struct rnp_hw {\n \tvoid *back;\n@@ -105,8 +122,10 @@ struct rnp_hw {\n \tchar *eth_base;\n \tchar *veb_base;\n \tchar *mac_base[RNP_MAX_HW_PORT_PERR_PF];\n+\tchar *comm_reg_base;\n \tchar *msix_base;\n \t/* === dma == */\n+\tchar *dev_version;\n \tchar *dma_axi_en;\n \tchar *dma_axi_st;\n \n@@ -114,10 +133,37 @@ struct rnp_hw {\n \tuint16_t vendor_id;\n \tuint16_t function;\n \tuint16_t pf_vf_num;\n+\tint pfvfnum;\n \tuint16_t max_vfs;\n+\n+\tbool ncsi_en;\n+\tuint8_t ncsi_rar_entries;\n+\n+\tint sgmii_phy_id;\n+\tint is_sgmii;\n+\tu16 phy_type;\n+\tuint8_t force_10g_1g_speed_ablity;\n+\tuint8_t force_speed_stat;\n+#define FORCE_SPEED_STAT_DISABLED (0)\n+#define FORCE_SPEED_STAT_1G (1)\n+#define FORCE_SPEED_STAT_10G (2)\n+\tuint32_t speed;\n+\tunsigned int axi_mhz;\n+\n+\tint fw_version; /* Primary FW Version */\n+\tuint32_t fw_uid; /* Subclass Fw Version */\n+\n+\tint nic_mode;\n+\tunsigned char lane_mask;\n+\tint lane_of_port[4];\n+\tchar phy_port_ids[4]; /* port id: for lane0~3: value: 0 ~ 7 */\n+\tuint8_t max_port_num; /* Max Port Num This PF Have */\n+\n \tvoid *cookie_pool;\n \tchar cookie_p_name[RTE_MEMZONE_NAMESIZE];\n \n+\tstruct rnp_mac_info mac;\n \tstruct rnp_mbx_info mbx;\n+\trte_spinlock_t fw_lock;\n } __rte_cache_aligned;\n #endif /* __RNP_H__*/\ndiff --git a/drivers/net/rnp/meson.build b/drivers/net/rnp/meson.build\nindex 38dbee5ca4..c52566c357 100644\n--- a/drivers/net/rnp/meson.build\n+++ b/drivers/net/rnp/meson.build\n@@ -10,5 +10,8 @@ endif\n sources = files(\n \t\t'rnp_ethdev.c',\n \t\t'rnp_mbx.c',\n+\t\t'rnp_mbx_fw.c',\n+\t\t'base/rnp_api.c',\n )\n+\n includes += include_directories('base')\ndiff --git a/drivers/net/rnp/rnp.h b/drivers/net/rnp/rnp.h\nindex 437a2cc209..4e521f8bdc 100644\n--- a/drivers/net/rnp/rnp.h\n+++ b/drivers/net/rnp/rnp.h\n@@ -13,6 +13,20 @@\n #define RNP_CFG_BAR\t\t(4)\n #define RNP_PF_INFO_BAR\t\t(0)\n \n+enum rnp_resource_share_m {\n+\tRNP_SHARE_CORPORATE = 0,\n+\tRNP_SHARE_INDEPEND,\n+};\n+/*\n+ * Structure to store private data for each driver instance (for each port).\n+ */\n+enum rnp_work_mode {\n+\tRNP_SINGLE_40G = 0,\n+\tRNP_SINGLE_10G = 1,\n+\tRNP_DUAL_10G = 2,\n+\tRNP_QUAD_10G = 3,\n+};\n+\n struct rnp_eth_port {\n \tvoid *adapt;\n \tstruct rnp_hw *hw;\n@@ -21,9 +35,12 @@ struct rnp_eth_port {\n \n struct rnp_share_ops {\n \tconst struct rnp_mbx_api *mbx_api;\n+\tconst struct rnp_mac_api *mac_api;\n } __rte_cache_aligned;\n \n struct rnp_eth_adapter {\n+\tenum rnp_work_mode mode;\n+\tenum rnp_resource_share_m s_mode; /* Port Resource Share Policy */\n \tstruct rnp_hw hw;\n \tuint16_t max_vfs;\n \tstruct rte_pci_device *pdev;\n@@ -31,7 +48,9 @@ struct rnp_eth_adapter {\n \tstruct rnp_eth_port *ports[RNP_MAX_PORT_OF_PF];\n \tstruct rnp_share_ops *share_priv;\n \n+\tint max_link_speed;\n \tuint8_t num_ports; /* Cur Pf Has physical Port Num */\n+\tuint8_t lane_mask;\n } __rte_cache_aligned;\n \n #define RNP_DEV_TO_PORT(eth_dev) \\\n@@ -40,9 +59,14 @@ struct rnp_eth_adapter {\n \t((struct rnp_eth_adapter *)(RNP_DEV_TO_PORT(eth_dev)->adapt))\n #define RNP_DEV_TO_HW(eth_dev) \\\n \t(&((struct rnp_eth_adapter *)(RNP_DEV_TO_PORT((eth_dev))->adapt))->hw)\n+#define RNP_HW_TO_ADAPTER(hw) \\\n+\t((struct rnp_eth_adapter *)((hw)->back))\n #define RNP_DEV_PP_PRIV_TO_MBX_OPS(dev) \\\n \t(((struct rnp_share_ops *)(dev)->process_private)->mbx_api)\n #define RNP_DEV_TO_MBX_OPS(dev)\tRNP_DEV_PP_PRIV_TO_MBX_OPS(dev)\n+#define RNP_DEV_PP_PRIV_TO_MAC_OPS(dev) \\\n+\t(((struct rnp_share_ops *)(dev)->process_private)->mac_api)\n+#define RNP_DEV_TO_MAC_OPS(dev) RNP_DEV_PP_PRIV_TO_MAC_OPS(dev)\n \n static inline void rnp_reg_offset_init(struct rnp_hw *hw)\n {\n@@ -56,10 +80,10 @@ static inline void rnp_reg_offset_init(struct rnp_hw *hw)\n \t\thw->msix_base = hw->iobar4 + 0xa0000;\n \t}\n \t/* === dma status/config====== */\n+\thw->dev_version = hw->iobar4 + 0x0000;\n \thw->link_sync = hw->iobar4 + 0x000c;\n \thw->dma_axi_en = hw->iobar4 + 0x0010;\n \thw->dma_axi_st = hw->iobar4 + 0x0014;\n-\n \tif (hw->mbx.pf_num)\n \t\thw->msix_base += 0x200;\n \t/* === queue registers === */\n@@ -69,5 +93,7 @@ static inline void rnp_reg_offset_init(struct rnp_hw *hw)\n \t/* mac */\n \tfor (i = 0; i < RNP_MAX_HW_PORT_PERR_PF; i++)\n \t\thw->mac_base[i] = hw->iobar4 + 0x60000 + 0x10000 * i;\n+\t/* === top reg === */\n+\thw->comm_reg_base = hw->iobar4 + 0x30000;\n }\n #endif /* __RNP_H__ */\ndiff --git a/drivers/net/rnp/rnp_ethdev.c b/drivers/net/rnp/rnp_ethdev.c\nindex 47c5361f95..b7a50d889f 100644\n--- a/drivers/net/rnp/rnp_ethdev.c\n+++ b/drivers/net/rnp/rnp_ethdev.c\n@@ -8,7 +8,9 @@\n #include <ethdev_driver.h>\n \n #include \"rnp.h\"\n+#include \"rnp_api.h\"\n #include \"rnp_mbx.h\"\n+#include \"rnp_mbx_fw.h\"\n #include \"rnp_logs.h\"\n \n static int\n@@ -92,7 +94,30 @@ rnp_alloc_eth_port(struct rte_pci_device *master_pci, char *name)\n \n static void rnp_get_nic_attr(struct rnp_eth_adapter *adapter)\n {\n-\tRTE_SET_USED(adapter);\n+\tstruct rnp_hw *hw = &adapter->hw;\n+\tint lane_mask = 0, err, mode = 0;\n+\n+\trnp_mbx_link_event_enable(adapter->eth_dev, false);\n+\n+\terr = rnp_mbx_get_capability(adapter->eth_dev, &lane_mask, &mode);\n+\tif (err < 0 || !lane_mask) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: mbx_get_capability error! errcode=%d\\n\",\n+\t\t\t\t__func__, hw->speed);\n+\t\treturn;\n+\t}\n+\n+\tadapter->num_ports = __builtin_popcount(lane_mask);\n+\tadapter->max_link_speed = hw->speed;\n+\tadapter->lane_mask = lane_mask;\n+\tadapter->mode = hw->nic_mode;\n+\n+\tPMD_DRV_LOG(INFO, \"max link speed:%d lane_mask:0x%x nic-mode:0x%x\\n\",\n+\t\t\t(int)adapter->max_link_speed,\n+\t\t\t(int)adapter->num_ports, adapter->mode);\n+\tif (adapter->num_ports && adapter->num_ports == 1)\n+\t\tadapter->s_mode = RNP_SHARE_CORPORATE;\n+\telse\n+\t\tadapter->s_mode = RNP_SHARE_INDEPEND;\n }\n \n static int\n@@ -125,6 +150,72 @@ rnp_process_resource_init(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+static int32_t rnp_init_hw_pf(struct rnp_hw *hw)\n+{\n+\tstruct rnp_eth_adapter *adapter = RNP_HW_TO_ADAPTER(hw);\n+\tuint32_t version;\n+\tuint32_t reg;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tversion = rnp_rd_reg(hw->dev_version);\n+\tPMD_DRV_LOG(INFO, \"NIC HW Version:0x%.2x\\n\", version);\n+\n+\t/* Disable Rx/Tx Dma */\n+\trnp_wr_reg(hw->dma_axi_en, false);\n+\t/* Check Dma Chanle Status */\n+\twhile (rnp_rd_reg(hw->dma_axi_st) == 0)\n+\t\t;\n+\n+\t/* Reset Nic All Hardware */\n+\tif (rnp_reset_hw(adapter->eth_dev, hw))\n+\t\treturn -EPERM;\n+\n+\t/* Rx Proto Offload No-BYPASS */\n+\trnp_eth_wr(hw, RNP_ETH_ENGINE_BYPASS, false);\n+\t/* Enable Flow Filter Engine */\n+\trnp_eth_wr(hw, RNP_HOST_FILTER_EN, true);\n+\t/* Enable VXLAN Parse */\n+\trnp_eth_wr(hw, RNP_EN_TUNNEL_VXLAN_PARSE, true);\n+\t/* Enabled REDIR ACTION */\n+\trnp_eth_wr(hw, RNP_REDIR_CTRL, true);\n+\n+\t/* Setup Scatter DMA Mem Size */\n+\treg = ((RTE_ETHER_MAX_LEN / 16) << RNP_DMA_SCATTER_MEM_SHIFT);\n+\trnp_wr_reg(hw->iobar4 + RNP_DMA_CTRL, reg);\n+#ifdef PHYTIUM_SUPPORT\n+#define RNP_DMA_PADDING (1 << 8)\n+\treg = rnp_rd_reg(hw->iobar4 + RNP_DMA_CTRL);\n+\treg |= RNP_DMA_PADDING;\n+\trnp_wr_reg(hw->iobar4 + RNP_DMA_CTRL, reg);\n+#endif\n+\t/* Enable Rx/Tx Dma */\n+\trnp_wr_reg(hw->dma_axi_en, 0b1111);\n+\n+\trnp_wr_reg(hw->comm_reg_base + RNP_TX_QINQ_WORKAROUND, 1);\n+\n+\treturn 0;\n+}\n+\n+static int32_t rnp_reset_hw_pf(struct rnp_hw *hw)\n+{\n+\tstruct rnp_eth_adapter *adapter = hw->back;\n+\n+\trnp_wr_reg(hw->comm_reg_base + RNP_NIC_RESET, 0);\n+\trte_wmb();\n+\trnp_wr_reg(hw->comm_reg_base + RNP_NIC_RESET, 1);\n+\n+\trnp_mbx_fw_reset_phy(adapter->eth_dev);\n+\n+\tPMD_DRV_LOG(INFO, \"PF[%d] reset nic finish\\n\",\n+\t\t\thw->function);\n+\treturn 0;\n+}\n+\n+const struct rnp_mac_api rnp_mac_ops = {\n+\t.reset_hw\t= rnp_reset_hw_pf,\n+\t.init_hw\t= rnp_init_hw_pf\n+};\n+\n static void\n rnp_common_ops_init(struct rnp_eth_adapter *adapter)\n {\ndiff --git a/drivers/net/rnp/rnp_mbx_fw.c b/drivers/net/rnp/rnp_mbx_fw.c\nnew file mode 100644\nindex 0000000000..8928805cbf\n--- /dev/null\n+++ b/drivers/net/rnp/rnp_mbx_fw.c\n@@ -0,0 +1,272 @@\n+#include <linux/wait.h>\n+#include <stdio.h>\n+\n+#include <rte_version.h>\n+#include <ethdev_pci.h>\n+#include <rte_malloc.h>\n+#include <rte_alarm.h>\n+\n+#include \"rnp.h\"\n+#include \"rnp_mbx.h\"\n+#include \"rnp_mbx_fw.h\"\n+#include \"rnp_logs.h\"\n+\n+static int\n+rnp_fw_send_cmd_wait(struct rte_eth_dev *dev, struct mbx_fw_cmd_req *req,\n+\t\t struct mbx_fw_cmd_reply *reply)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tint err;\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\n+\terr = ops->write_posted(dev, (u32 *)req,\n+\t\t\t(req->datalen + MBX_REQ_HDR_LEN) / 4, MBX_FW);\n+\tif (err) {\n+\t\tRNP_PMD_LOG(ERR, \"%s: write_posted failed! err:0x%x\\n\",\n+\t\t\t\t__func__, err);\n+\t\trte_spinlock_unlock(&hw->fw_lock);\n+\t\treturn err;\n+\t}\n+\n+\terr = ops->read_posted(dev, (u32 *)reply, sizeof(*reply) / 4, MBX_FW);\n+\trte_spinlock_unlock(&hw->fw_lock);\n+\tif (err) {\n+\t\tRNP_PMD_LOG(ERR,\n+\t\t\t\t\"%s: read_posted failed! err:0x%x. \"\n+\t\t\t\t\"req-op:0x%x\\n\",\n+\t\t\t\t__func__,\n+\t\t\t\terr,\n+\t\t\t\treq->opcode);\n+\t\tgoto err_quit;\n+\t}\n+\n+\tif (reply->error_code) {\n+\t\tRNP_PMD_LOG(ERR,\n+\t\t\t\t\"%s: reply err:0x%x. req-op:0x%x\\n\",\n+\t\t\t\t__func__,\n+\t\t\t\treply->error_code,\n+\t\t\t\treq->opcode);\n+\t\terr = -reply->error_code;\n+\t\tgoto err_quit;\n+\t}\n+\n+\treturn 0;\n+err_quit:\n+\tRNP_PMD_LOG(ERR,\n+\t\t\t\"%s:PF[%d]: req:%08x_%08x_%08x_%08x \"\n+\t\t\t\"reply:%08x_%08x_%08x_%08x\\n\",\n+\t\t\t__func__,\n+\t\t\thw->function,\n+\t\t\t((int *)req)[0],\n+\t\t\t((int *)req)[1],\n+\t\t\t((int *)req)[2],\n+\t\t\t((int *)req)[3],\n+\t\t\t((int *)reply)[0],\n+\t\t\t((int *)reply)[1],\n+\t\t\t((int *)reply)[2],\n+\t\t\t((int *)reply)[3]);\n+\n+\treturn err;\n+}\n+\n+static int rnp_mbx_fw_post_req(struct rte_eth_dev *dev,\n+\t\t\t struct mbx_fw_cmd_req *req,\n+\t\t\t struct mbx_req_cookie *cookie)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tint err = 0;\n+\tint timeout_cnt;\n+#define WAIT_MS 10\n+\n+\tcookie->done = 0;\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\n+\t/* down_interruptible(&pf_cpu_lock); */\n+\terr = ops->write(hw, (u32 *)req,\n+\t\t\t(req->datalen + MBX_REQ_HDR_LEN) / 4, MBX_FW);\n+\tif (err) {\n+\t\tRNP_PMD_LOG(ERR, \"rnp_write_mbx failed!\\n\");\n+\t\tgoto quit;\n+\t}\n+\n+\ttimeout_cnt = cookie->timeout_ms / WAIT_MS;\n+\twhile (timeout_cnt > 0) {\n+\t\trte_delay_ms(WAIT_MS);\n+\t\ttimeout_cnt--;\n+\t\tif (cookie->done)\n+\t\t\tbreak;\n+\t}\n+\n+quit:\n+\trte_spinlock_unlock(&hw->fw_lock);\n+\treturn err;\n+}\n+\n+static int rnp_fw_get_capablity(struct rte_eth_dev *dev,\n+\t\t\t\tstruct phy_abilities *abil)\n+{\n+\tstruct mbx_fw_cmd_reply reply;\n+\tstruct mbx_fw_cmd_req req;\n+\tint err;\n+\n+\tmemset(&req, 0, sizeof(req));\n+\tmemset(&reply, 0, sizeof(reply));\n+\n+\tbuild_phy_abalities_req(&req, &req);\n+\n+\terr = rnp_fw_send_cmd_wait(dev, &req, &reply);\n+\tif (err)\n+\t\treturn err;\n+\n+\tmemcpy(abil, &reply.phy_abilities, sizeof(*abil));\n+\n+\treturn 0;\n+}\n+\n+#define RNP_MBX_API_MAX_RETRY (10)\n+int rnp_mbx_get_capability(struct rte_eth_dev *dev,\n+\t\t\t int *lane_mask,\n+\t\t\t int *nic_mode)\n+{\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct phy_abilities ablity;\n+\tuint16_t temp_lmask;\n+\tuint16_t lane_bit = 0;\n+\tuint16_t retry = 0;\n+\tint lane_cnt = 0;\n+\tuint8_t lane_idx;\n+\tint err = -EIO;\n+\tuint8_t idx;\n+\n+\tmemset(&ablity, 0, sizeof(ablity));\n+\n+\t/* enable CM3CPU to PF MBX IRQ */\n+\tdo {\n+\t\terr = rnp_fw_get_capablity(dev, &ablity);\n+\t\tif (retry > RNP_MBX_API_MAX_RETRY)\n+\t\t\tbreak;\n+\t\tretry++;\n+\t} while (err);\n+\tif (!err) {\n+\t\thw->lane_mask = ablity.lane_mask;\n+\t\thw->nic_mode = ablity.nic_mode;\n+\t\thw->pfvfnum = ablity.pfnum;\n+\t\thw->fw_version = ablity.fw_version;\n+\t\thw->axi_mhz = ablity.axi_mhz;\n+\t\thw->fw_uid = ablity.fw_uid;\n+\t\tif (ablity.phy_type == PHY_TYPE_SGMII) {\n+\t\t\thw->is_sgmii = 1;\n+\t\t\thw->sgmii_phy_id = ablity.phy_id;\n+\t\t}\n+\n+\t\tif (ablity.ext_ablity != 0xffffffff && ablity.e.valid) {\n+\t\t\thw->ncsi_en = (ablity.e.ncsi_en == 1);\n+\t\t\thw->ncsi_rar_entries = 1;\n+\t\t}\n+\n+\t\tif (hw->nic_mode == RNP_SINGLE_10G &&\n+\t\t\t\thw->fw_version >= 0x00050201 &&\n+\t\t\t\tablity.speed == RTE_ETH_SPEED_NUM_10G) {\n+\t\t\thw->force_speed_stat = FORCE_SPEED_STAT_DISABLED;\n+\t\t\thw->force_10g_1g_speed_ablity = 1;\n+\t\t}\n+\n+\t\tif (lane_mask)\n+\t\t\t*lane_mask = hw->lane_mask;\n+\t\tif (nic_mode)\n+\t\t\t*nic_mode = hw->nic_mode;\n+\n+\t\tlane_cnt = __builtin_popcount(hw->lane_mask);\n+\t\ttemp_lmask = hw->lane_mask;\n+\t\tfor (idx = 0; idx < lane_cnt; idx++) {\n+\t\t\thw->phy_port_ids[idx] = ablity.port_ids[idx];\n+\t\t\tlane_bit = ffs(temp_lmask) - 1;\n+\t\t\tlane_idx = ablity.port_ids[idx] % lane_cnt;\n+\t\t\thw->lane_of_port[lane_idx] = lane_bit;\n+\t\t\ttemp_lmask &= ~BIT(lane_bit);\n+\t\t}\n+\t\thw->max_port_num = lane_cnt;\n+\t}\n+\n+\tRNP_PMD_LOG(INFO,\n+\t\t\t\"%s: nic-mode:%d lane_cnt:%d lane_mask:0x%x \"\n+\t\t\t\"pfvfnum:0x%x, fw_version:0x%08x, ports:%d-%d-%d-%d ncsi:en:%d\\n\",\n+\t\t\t__func__,\n+\t\t\thw->nic_mode,\n+\t\t\tlane_cnt,\n+\t\t\thw->lane_mask,\n+\t\t\thw->pfvfnum,\n+\t\t\tablity.fw_version,\n+\t\t\tablity.port_ids[0],\n+\t\t\tablity.port_ids[1],\n+\t\t\tablity.port_ids[2],\n+\t\t\tablity.port_ids[3],\n+\t\t\thw->ncsi_en);\n+\n+\tif (lane_cnt <= 0 || lane_cnt > 4)\n+\t\treturn -EIO;\n+\n+\treturn err;\n+}\n+\n+int rnp_mbx_link_event_enable(struct rte_eth_dev *dev, int enable)\n+{\n+\tconst struct rnp_mbx_api *ops = RNP_DEV_TO_MBX_OPS(dev);\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct mbx_fw_cmd_reply reply;\n+\tstruct mbx_fw_cmd_req req;\n+\tint err, v;\n+\n+\tmemset(&req, 0, sizeof(req));\n+\tmemset(&reply, 0, sizeof(reply));\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\tif (enable) {\n+\t\tv = rnp_rd_reg(hw->link_sync);\n+\t\tv &= ~RNP_FIRMWARE_SYNC_MASK;\n+\t\tv |= RNP_FIRMWARE_SYNC_MAGIC;\n+\t\trnp_wr_reg(hw->link_sync, v);\n+\t} else {\n+\t\trnp_wr_reg(hw->link_sync, 0);\n+\t}\n+\trte_spinlock_unlock(&hw->fw_lock);\n+\n+\tbuild_link_set_event_mask(&req, BIT(EVT_LINK_UP),\n+\t\t\t(enable & 1) << EVT_LINK_UP, &req);\n+\n+\trte_spinlock_lock(&hw->fw_lock);\n+\terr = ops->write_posted(dev, (u32 *)&req,\n+\t\t\t(req.datalen + MBX_REQ_HDR_LEN) / 4, MBX_FW);\n+\trte_spinlock_unlock(&hw->fw_lock);\n+\n+\trte_delay_ms(200);\n+\n+\treturn err;\n+}\n+\n+int rnp_mbx_fw_reset_phy(struct rte_eth_dev *dev)\n+{\n+\tstruct rnp_hw *hw = RNP_DEV_TO_HW(dev);\n+\tstruct mbx_fw_cmd_reply reply;\n+\tstruct mbx_req_cookie *cookie;\n+\tstruct mbx_fw_cmd_req req;\n+\n+\tmemset(&req, 0, sizeof(req));\n+\tmemset(&reply, 0, sizeof(reply));\n+\n+\tif (hw->mbx.irq_enabled) {\n+\t\tcookie = rnp_memzone_reserve(hw->cookie_p_name, 0);\n+\t\tif (!cookie)\n+\t\t\treturn -ENOMEM;\n+\t\tmemset(cookie->priv, 0, cookie->priv_len);\n+\t\tbuild_reset_phy_req(&req, cookie);\n+\t\treturn rnp_mbx_fw_post_req(dev, &req, cookie);\n+\t}\n+\tbuild_reset_phy_req(&req, &req);\n+\n+\treturn rnp_fw_send_cmd_wait(dev, &req, &reply);\n+}\ndiff --git a/drivers/net/rnp/rnp_mbx_fw.h b/drivers/net/rnp/rnp_mbx_fw.h\nindex 439090b5a3..44ffe56908 100644\n--- a/drivers/net/rnp/rnp_mbx_fw.h\n+++ b/drivers/net/rnp/rnp_mbx_fw.h\n@@ -16,7 +16,168 @@ struct mbx_req_cookie {\n \tint priv_len;\n \tchar priv[RNP_MAX_SHARE_MEM];\n };\n+enum GENERIC_CMD {\n+\t/* link configuration admin commands */\n+\tGET_PHY_ABALITY = 0x0601,\n+\tRESET_PHY = 0x0603,\n+\tSET_EVENT_MASK = 0x0613,\n+};\n+\n+enum link_event_mask {\n+\tEVT_LINK_UP = 1,\n+\tEVT_NO_MEDIA = 2,\n+\tEVT_LINK_FAULT = 3,\n+\tEVT_PHY_TEMP_ALARM = 4,\n+\tEVT_EXCESSIVE_ERRORS = 5,\n+\tEVT_SIGNAL_DETECT = 6,\n+\tEVT_AUTO_NEGOTIATION_DONE = 7,\n+\tEVT_MODULE_QUALIFICATION_FAILD = 8,\n+\tEVT_PORT_TX_SUSPEND = 9,\n+};\n+\n+enum pma_type {\n+\tPHY_TYPE_NONE = 0,\n+\tPHY_TYPE_1G_BASE_KX,\n+\tPHY_TYPE_SGMII,\n+\tPHY_TYPE_10G_BASE_KR,\n+\tPHY_TYPE_25G_BASE_KR,\n+\tPHY_TYPE_40G_BASE_KR4,\n+\tPHY_TYPE_10G_BASE_SR,\n+\tPHY_TYPE_40G_BASE_SR4,\n+\tPHY_TYPE_40G_BASE_CR4,\n+\tPHY_TYPE_40G_BASE_LR4,\n+\tPHY_TYPE_10G_BASE_LR,\n+\tPHY_TYPE_10G_BASE_ER,\n+};\n+\n+struct phy_abilities {\n+\tunsigned char link_stat;\n+\tunsigned char lane_mask;\n+\n+\tint speed;\n+\tshort phy_type;\n+\tshort nic_mode;\n+\tshort pfnum;\n+\tunsigned int fw_version;\n+\tunsigned int axi_mhz;\n+\tuint8_t port_ids[4];\n+\tuint32_t fw_uid;\n+\tuint32_t phy_id;\n+\n+\tint wol_status;\n+\n+\tunion {\n+\t\tunsigned int ext_ablity;\n+\t\tstruct {\n+\t\t\tunsigned int valid : 1;\n+\t\t\tunsigned int wol_en : 1;\n+\t\t\tunsigned int pci_preset_runtime_en : 1;\n+\t\t\tunsigned int smbus_en : 1;\n+\t\t\tunsigned int ncsi_en : 1;\n+\t\t\tunsigned int rpu_en : 1;\n+\t\t\tunsigned int v2 : 1;\n+\t\t\tunsigned int pxe_en : 1;\n+\t\t\tunsigned int mctp_en : 1;\n+\t\t} e;\n+\t};\n+} __rte_packed __rte_aligned(4);\n+\n+/* firmware -> driver */\n struct mbx_fw_cmd_reply {\n-} __rte_cache_aligned;\n+\t/* fw must set: DD, CMP, Error(if error), copy value */\n+\tunsigned short flags;\n+\t/* from command: LB,RD,VFC,BUF,SI,EI,FE */\n+\tunsigned short opcode; /* 2-3: copy from req */\n+\tunsigned short error_code; /* 4-5: 0 if no error */\n+\tunsigned short datalen; /* 6-7: */\n+\tunion {\n+\t\tstruct {\n+\t\t\tunsigned int cookie_lo; /* 8-11: */\n+\t\t\tunsigned int cookie_hi; /* 12-15: */\n+\t\t};\n+\t\tvoid *cookie;\n+\t};\n+\t/* ===== data ==== [16-64] */\n+\tunion {\n+\t\tstruct phy_abilities phy_abilities;\n+\t};\n+} __rte_packed __rte_aligned(4);\n+\n+#define MBX_REQ_HDR_LEN 24\n+/* driver -> firmware */\n+struct mbx_fw_cmd_req {\n+\tunsigned short flags; /* 0-1 */\n+\tunsigned short opcode; /* 2-3 enum LINK_ADM_CMD */\n+\tunsigned short datalen; /* 4-5 */\n+\tunsigned short ret_value; /* 6-7 */\n+\tunion {\n+\t\tstruct {\n+\t\t\tunsigned int cookie_lo; /* 8-11 */\n+\t\t\tunsigned int cookie_hi; /* 12-15 */\n+\t\t};\n+\t\tvoid *cookie;\n+\t};\n+\tunsigned int reply_lo; /* 16-19 5dw */\n+\tunsigned int reply_hi; /* 20-23 */\n+\t/* === data === [24-64] 7dw */\n+\tunion {\n+\t\tstruct {\n+\t\t\tint requester;\n+#define REQUEST_BY_DPDK 0xa1\n+#define REQUEST_BY_DRV 0xa2\n+#define REQUEST_BY_PXE 0xa3\n+\t\t} get_phy_ablity;\n+\n+\t\tstruct {\n+\t\t\tunsigned short enable_stat;\n+\t\t\tunsigned short event_mask; /* enum link_event_mask */\n+\t\t} stat_event_mask;\n+\t};\n+} __rte_packed __rte_aligned(4);\n+\n+static inline void\n+build_phy_abalities_req(struct mbx_fw_cmd_req *req, void *cookie)\n+{\n+\treq->flags = 0;\n+\treq->opcode = GET_PHY_ABALITY;\n+\treq->datalen = 0;\n+\treq->reply_lo = 0;\n+\treq->reply_hi = 0;\n+\treq->cookie = cookie;\n+}\n+\n+/* enum link_event_mask or */\n+static inline void\n+build_link_set_event_mask(struct mbx_fw_cmd_req *req,\n+\t\t\t unsigned short event_mask,\n+\t\t\t unsigned short enable,\n+\t\t\t void *cookie)\n+{\n+\treq->flags = 0;\n+\treq->opcode = SET_EVENT_MASK;\n+\treq->datalen = sizeof(req->stat_event_mask);\n+\treq->cookie = cookie;\n+\treq->reply_lo = 0;\n+\treq->reply_hi = 0;\n+\treq->stat_event_mask.event_mask = event_mask;\n+\treq->stat_event_mask.enable_stat = enable;\n+}\n+\n+static inline void\n+build_reset_phy_req(struct mbx_fw_cmd_req *req,\n+\t\t void *cookie)\n+{\n+\treq->flags = 0;\n+\treq->opcode = RESET_PHY;\n+\treq->datalen = 0;\n+\treq->reply_lo = 0;\n+\treq->reply_hi = 0;\n+\treq->cookie = cookie;\n+}\n \n+int rnp_mbx_get_capability(struct rte_eth_dev *dev,\n+\t\t\t int *lane_mask,\n+\t\t\t int *nic_mode);\n+int rnp_mbx_link_event_enable(struct rte_eth_dev *dev, int enable);\n+int rnp_mbx_fw_reset_phy(struct rte_eth_dev *dev);\n #endif /* __RNP_MBX_FW_H__*/\n", "prefixes": [ "v2", "5/8" ] }