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GET /api/patches/129878/?format=api
{ "id": 129878, "url": "http://patchwork.dpdk.org/api/patches/129878/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230803075038.307012-10-david.marchand@redhat.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230803075038.307012-10-david.marchand@redhat.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230803075038.307012-10-david.marchand@redhat.com", "date": "2023-08-03T07:50:32", "name": "[09/14] pci: define some PCIe constants", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5f84546f6365d0adc657407040aa5a70ad6eaaeb", "submitter": { "id": 1173, "url": "http://patchwork.dpdk.org/api/people/1173/?format=api", "name": "David Marchand", "email": "david.marchand@redhat.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230803075038.307012-10-david.marchand@redhat.com/mbox/", "series": [ { "id": 29101, "url": "http://patchwork.dpdk.org/api/series/29101/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29101", "date": "2023-08-03T07:50:23", "name": "Cleanup PCI(e) drivers", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29101/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/129878/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/129878/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D115242FC1;\n\tThu, 3 Aug 2023 09:51:58 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7858D43267;\n\tThu, 3 Aug 2023 09:51:27 +0200 (CEST)", "from us-smtp-delivery-124.mimecast.com\n (us-smtp-delivery-124.mimecast.com [170.10.133.124])\n by mails.dpdk.org (Postfix) with ESMTP id F193E4326E\n for <dev@dpdk.org>; Thu, 3 Aug 2023 09:51:25 +0200 (CEST)", "from mimecast-mx02.redhat.com (66.187.233.73 [66.187.233.73]) by\n relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n us-mta-352-LLYNyAjFNxC7fIW7AhVEQg-1; Thu, 03 Aug 2023 03:51:20 -0400", "from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com\n [10.11.54.9])\n (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n (No client certificate requested)\n by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 8AD443811F3F;\n Thu, 3 Aug 2023 07:51:19 +0000 (UTC)", "from dmarchan.redhat.com (unknown [10.45.224.120])\n by smtp.corp.redhat.com (Postfix) with ESMTP id EE37B492B03;\n Thu, 3 Aug 2023 07:51:17 +0000 (UTC)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1691049085;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=nGTU5rzKWH39uptIvx7kqUGD4bxaSgOGSxk8Olnky1k=;\n b=KKjD8IM9tSDbQYMZvm80mkxnPWIoRbr8DVimvpoqCeTsrvTAaHEWjC1gh2JPSV35rT2Lh6\n 5afswa+kc4H4p3XYUhcayLOkxjRG9Nzhetu2WSf2kEVjBWzyYXkNVu0HHfc95neqOkr5sU\n o8w8TioVAMJYauRRgXVTCpepWWeforg=", "X-MC-Unique": "LLYNyAjFNxC7fIW7AhVEQg-1", "From": "David Marchand <david.marchand@redhat.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com,\n nipun.gupta@amd.com, Timothy McDaniel <timothy.mcdaniel@intel.com>,\n Julien Aube <julien_dpdk@jaube.fr>, Gaetan Rivet <grive@u256.net>", "Subject": "[PATCH 09/14] pci: define some PCIe constants", "Date": "Thu, 3 Aug 2023 09:50:32 +0200", "Message-ID": "<20230803075038.307012-10-david.marchand@redhat.com>", "In-Reply-To": "<20230803075038.307012-1-david.marchand@redhat.com>", "References": "<20230803075038.307012-1-david.marchand@redhat.com>", "MIME-Version": "1.0", "X-Scanned-By": "MIMEDefang 3.1 on 10.11.54.9", "X-Mimecast-Spam-Score": "0", "X-Mimecast-Originator": "redhat.com", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain; charset=\"US-ASCII\"; x-default=true", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Define some PCI Express constants and use them in existing drivers.\n\nSigned-off-by: David Marchand <david.marchand@redhat.com>\n---\n drivers/event/dlb2/pf/dlb2_main.c | 40 ++++++++++++-------------------\n drivers/net/bnx2x/bnx2x.c | 16 ++++++-------\n drivers/net/bnx2x/bnx2x.h | 35 ---------------------------\n lib/pci/rte_pci.h | 17 ++++++++++++-\n 4 files changed, 39 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex 6dbaa2ff97..8d960edef6 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -27,16 +27,6 @@\n #define NO_OWNER_VF 0\t/* PF ONLY! */\n #define NOT_VF_REQ false /* PF ONLY! */\n \n-#define DLB2_PCI_LNKCTL 16\n-#define DLB2_PCI_SLTCTL 24\n-#define DLB2_PCI_RTCTL 28\n-#define DLB2_PCI_EXP_DEVCTL2 40\n-#define DLB2_PCI_LNKCTL2 48\n-#define DLB2_PCI_SLTCTL2 56\n-#define DLB2_PCI_EXP_DEVSTA 10\n-#define DLB2_PCI_EXP_DEVSTA_TRPND 0x20\n-#define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000\n-\n #define DLB2_PCI_EXT_CAP_ID_PRI 0x13\n #define DLB2_PCI_EXT_CAP_ID_ACS 0xD\n \n@@ -249,27 +239,27 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \tif (rte_pci_read_config(pdev, &dev_ctl_word, 2, off) != 2)\n \t\tdev_ctl_word = 0;\n \n-\toff = pcie_cap_offset + DLB2_PCI_LNKCTL;\n+\toff = pcie_cap_offset + RTE_PCI_EXP_LNKCTL;\n \tif (rte_pci_read_config(pdev, &lnk_word, 2, off) != 2)\n \t\tlnk_word = 0;\n \n-\toff = pcie_cap_offset + DLB2_PCI_SLTCTL;\n+\toff = pcie_cap_offset + RTE_PCI_EXP_SLTCTL;\n \tif (rte_pci_read_config(pdev, &slt_word, 2, off) != 2)\n \t\tslt_word = 0;\n \n-\toff = pcie_cap_offset + DLB2_PCI_RTCTL;\n+\toff = pcie_cap_offset + RTE_PCI_EXP_RTCTL;\n \tif (rte_pci_read_config(pdev, &rt_ctl_word, 2, off) != 2)\n \t\trt_ctl_word = 0;\n \n-\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL2;\n+\toff = pcie_cap_offset + RTE_PCI_EXP_DEVCTL2;\n \tif (rte_pci_read_config(pdev, &dev_ctl2_word, 2, off) != 2)\n \t\tdev_ctl2_word = 0;\n \n-\toff = pcie_cap_offset + DLB2_PCI_LNKCTL2;\n+\toff = pcie_cap_offset + RTE_PCI_EXP_LNKCTL2;\n \tif (rte_pci_read_config(pdev, &lnk_word2, 2, off) != 2)\n \t\tlnk_word2 = 0;\n \n-\toff = pcie_cap_offset + DLB2_PCI_SLTCTL2;\n+\toff = pcie_cap_offset + RTE_PCI_EXP_SLTCTL2;\n \tif (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2)\n \t\tslt_word2 = 0;\n \n@@ -296,7 +286,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \tfor (wait_count = 0; wait_count < 4; wait_count++) {\n \t\tint sleep_time;\n \n-\t\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVSTA;\n+\t\toff = pcie_cap_offset + RTE_PCI_EXP_DEVSTA;\n \t\tret = rte_pci_read_config(pdev, &devsta_busy_word, 2, off);\n \t\tif (ret != 2) {\n \t\t\tDLB2_LOG_ERR(\"[%s()] failed to read the pci device status\\n\",\n@@ -304,7 +294,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\treturn ret;\n \t\t}\n \n-\t\tif (!(devsta_busy_word & DLB2_PCI_EXP_DEVSTA_TRPND))\n+\t\tif (!(devsta_busy_word & RTE_PCI_EXP_DEVSTA_TRPND))\n \t\t\tbreak;\n \n \t\tsleep_time = (1 << (wait_count)) * 100;\n@@ -325,7 +315,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\treturn ret;\n \t}\n \n-\tdevctl_word |= DLB2_PCI_EXP_DEVCTL_BCR_FLR;\n+\tdevctl_word |= RTE_PCI_EXP_DEVCTL_BCR_FLR;\n \n \tret = rte_pci_write_config(pdev, &devctl_word, 2, off);\n \tif (ret != 2) {\n@@ -347,7 +337,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\treturn ret;\n \t\t}\n \n-\t\toff = pcie_cap_offset + DLB2_PCI_LNKCTL;\n+\t\toff = pcie_cap_offset + RTE_PCI_EXP_LNKCTL;\n \t\tret = rte_pci_write_config(pdev, &lnk_word, 2, off);\n \t\tif (ret != 2) {\n \t\t\tDLB2_LOG_ERR(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n@@ -355,7 +345,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\treturn ret;\n \t\t}\n \n-\t\toff = pcie_cap_offset + DLB2_PCI_SLTCTL;\n+\t\toff = pcie_cap_offset + RTE_PCI_EXP_SLTCTL;\n \t\tret = rte_pci_write_config(pdev, &slt_word, 2, off);\n \t\tif (ret != 2) {\n \t\t\tDLB2_LOG_ERR(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n@@ -363,7 +353,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\treturn ret;\n \t\t}\n \n-\t\toff = pcie_cap_offset + DLB2_PCI_RTCTL;\n+\t\toff = pcie_cap_offset + RTE_PCI_EXP_RTCTL;\n \t\tret = rte_pci_write_config(pdev, &rt_ctl_word, 2, off);\n \t\tif (ret != 2) {\n \t\t\tDLB2_LOG_ERR(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n@@ -371,7 +361,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\treturn ret;\n \t\t}\n \n-\t\toff = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL2;\n+\t\toff = pcie_cap_offset + RTE_PCI_EXP_DEVCTL2;\n \t\tret = rte_pci_write_config(pdev, &dev_ctl2_word, 2, off);\n \t\tif (ret != 2) {\n \t\t\tDLB2_LOG_ERR(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n@@ -379,7 +369,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\treturn ret;\n \t\t}\n \n-\t\toff = pcie_cap_offset + DLB2_PCI_LNKCTL2;\n+\t\toff = pcie_cap_offset + RTE_PCI_EXP_LNKCTL2;\n \t\tret = rte_pci_write_config(pdev, &lnk_word2, 2, off);\n \t\tif (ret != 2) {\n \t\t\tDLB2_LOG_ERR(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n@@ -387,7 +377,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\treturn ret;\n \t\t}\n \n-\t\toff = pcie_cap_offset + DLB2_PCI_SLTCTL2;\n+\t\toff = pcie_cap_offset + RTE_PCI_EXP_SLTCTL2;\n \t\tret = rte_pci_write_config(pdev, &slt_word2, 2, off);\n \t\tif (ret != 2) {\n \t\t\tDLB2_LOG_ERR(\"[%s()] failed to write the pcie config space at offset %d\\n\",\ndiff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c\nindex faf061beba..cfd8e35aa3 100644\n--- a/drivers/net/bnx2x/bnx2x.c\n+++ b/drivers/net/bnx2x/bnx2x.c\n@@ -7630,8 +7630,8 @@ static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)\n \n static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)\n {\n-\treturn bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &\n-\t\tPCIM_EXP_STA_TRANSACTION_PND;\n+\treturn bnx2x_pcie_capability_read(sc, RTE_PCI_EXP_TYPE_RC_EC) &\n+\t\tRTE_PCI_EXP_DEVSTA_TRPND;\n }\n \n /*\n@@ -7658,11 +7658,11 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)\n \t\tsc->devinfo.pcie_pm_cap_reg = caps->addr;\n \t}\n \n-\tlink_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);\n+\tlink_status = bnx2x_pcie_capability_read(sc, RTE_PCI_EXP_LNKSTA);\n \n-\tsc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);\n+\tsc->devinfo.pcie_link_speed = (link_status & RTE_PCI_EXP_LNKSTA_CLS);\n \tsc->devinfo.pcie_link_width =\n-\t ((link_status & PCIM_LINK_STA_WIDTH) >> 4);\n+\t ((link_status & RTE_PCI_EXP_LNKSTA_NLW) >> 4);\n \n \tPMD_DRV_LOG(DEBUG, sc, \"PCIe link speed=%d width=%d\",\n \t\t sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);\n@@ -9979,10 +9979,10 @@ static void bnx2x_init_pxp(struct bnx2x_softc *sc)\n \tuint16_t devctl;\n \tint r_order, w_order;\n \n-\tdevctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);\n+\tdevctl = bnx2x_pcie_capability_read(sc, RTE_PCI_EXP_DEVCTL);\n \n-\tw_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);\n-\tr_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);\n+\tw_order = ((devctl & RTE_PCI_EXP_DEVCTL_PAYLOAD) >> 5);\n+\tr_order = ((devctl & RTE_PCI_EXP_DEVCTL_READRQ) >> 12);\n \n \tecore_init_pxp_arb(sc, r_order, w_order);\n }\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 1efa166316..35206b4758 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -30,45 +30,10 @@\n \n #include \"elink.h\"\n \n-#ifndef RTE_EXEC_ENV_FREEBSD\n-#include <linux/pci_regs.h>\n-\n-#define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC\n-#define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND\n-#define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA\n-#define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW\n-#define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS\n-#define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL\n-#define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD\n-#define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ\n-#else\n-#include <dev/pci/pcireg.h>\n-#endif\n-\n #define IFM_10G_CX4 20 /* 10GBase CX4 copper */\n #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */\n #define IFM_10G_T 26 /* 10GBase-T - RJ45 */\n \n-#ifndef RTE_EXEC_ENV_FREEBSD\n-#define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC\n-#define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND\n-#define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA\n-#define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW\n-#define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS\n-#define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL\n-#define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD\n-#define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ\n-#else\n-#define PCIR_EXPRESS_DEVICE_STA\tPCIER_DEVICE_STA\n-#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND\n-#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA\n-#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH\n-#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED\n-#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL\n-#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD\n-#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST\n-#endif\n-\n #ifndef ARRAY_SIZE\n #define ARRAY_SIZE(arr) RTE_DIM(arr)\n #endif\ndiff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h\nindex b7e1ff5d78..a83f6abe14 100644\n--- a/lib/pci/rte_pci.h\n+++ b/lib/pci/rte_pci.h\n@@ -73,7 +73,22 @@ extern \"C\" {\n #define RTE_PCI_MSIX_TABLE_OFFSET\t0xfffffff8 /* Offset into specified BAR */\n \n /* PCI Express capability registers */\n-#define RTE_PCI_EXP_DEVCTL\t8\t/* Device Control */\n+#define RTE_PCI_EXP_TYPE_RC_EC\t\t0xa\t/* Root Complex Event Collector */\n+#define RTE_PCI_EXP_DEVCTL\t\t0x08\t/* Device Control */\n+#define RTE_PCI_EXP_DEVCTL_PAYLOAD\t0x00e0\t/* Max_Payload_Size */\n+#define RTE_PCI_EXP_DEVCTL_READRQ\t0x7000\t/* Max_Read_Request_Size */\n+#define RTE_PCI_EXP_DEVCTL_BCR_FLR\t0x8000\t/* Bridge Configuration Retry / FLR */\n+#define RTE_PCI_EXP_DEVSTA\t\t0x0a\t/* Device Status */\n+#define RTE_PCI_EXP_DEVSTA_TRPND\t0x0020\t/* Transactions Pending */\n+#define RTE_PCI_EXP_LNKCTL\t\t0x10\t/* Link Control */\n+#define RTE_PCI_EXP_LNKSTA\t\t0x12\t/* Link Status */\n+#define RTE_PCI_EXP_LNKSTA_CLS\t\t0x000f\t/* Current Link Speed */\n+#define RTE_PCI_EXP_LNKSTA_NLW\t\t0x03f0\t/* Negotiated Link Width */\n+#define RTE_PCI_EXP_SLTCTL\t\t0x18\t/* Slot Control */\n+#define RTE_PCI_EXP_RTCTL\t\t0x1c\t/* Root Control */\n+#define RTE_PCI_EXP_DEVCTL2\t\t0x28\t/* Device Control 2 */\n+#define RTE_PCI_EXP_LNKCTL2\t\t0x30\t/* Link Control 2 */\n+#define RTE_PCI_EXP_SLTCTL2\t\t0x38\t/* Slot Control 2 */\n \n /* Extended Capabilities (PCI-X 2.0 and Express) */\n #define RTE_PCI_EXT_CAP_ID(header)\t(header & 0x0000ffff)\n", "prefixes": [ "09/14" ] }