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GET /api/patches/130006/?format=api
{ "id": 130006, "url": "http://patchwork.dpdk.org/api/patches/130006/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230809013308.1449103-13-wenjing.qiao@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230809013308.1449103-13-wenjing.qiao@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230809013308.1449103-13-wenjing.qiao@intel.com", "date": "2023-08-09T01:33:06", "name": "[12/14] common/idpf/base: refine comments and alignment", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "90f033084941a39d8991ac06cd8250344ed038b7", "submitter": { "id": 2680, "url": "http://patchwork.dpdk.org/api/people/2680/?format=api", "name": "Wenjing Qiao", "email": "wenjing.qiao@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230809013308.1449103-13-wenjing.qiao@intel.com/mbox/", "series": [ { "id": 29135, "url": "http://patchwork.dpdk.org/api/series/29135/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29135", "date": "2023-08-09T01:32:54", "name": "update idpf base code", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29135/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/130006/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/130006/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5B7B443011;\n\tWed, 9 Aug 2023 03:34:46 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EB4354328B;\n\tWed, 9 Aug 2023 03:33:54 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id A51C04328B\n for <dev@dpdk.org>; Wed, 9 Aug 2023 03:33:53 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Aug 2023 18:33:53 -0700", "from dpdk-wenjing-02.sh.intel.com ([10.67.119.75])\n by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:50 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1691544833; x=1723080833;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=VqHOrZKQG985ssEmaOes61pf5x23W7Qlsr6Dyf6Sc28=;\n b=OLV9lfvk9o3tPVj3LI9Mt9lVQYuFAcaBqRyBGoBpq/stRo11a++3wfJs\n UFP4KMrhIPM3SF3ARWOsYsOzPn2Z04NcJ1Jvc8GBA7M0mmURb58zu+9W/\n quhWkxwq/HVXnd9s5I1TUpBUz58ylUG6QjmwpVVUP4++VnWF+jDEFFJpV\n blXYjMJMf6MpwWAfOSnxuHbE1QQStTB9wKQeFHsx8OhEQwXbqq6Ca4Ru9\n reYV0rm6ETHguGvF5Vxd37qqUntEtLM5zedNepaOJkmvow/+UPUKy+1Ec\n I30pSJ1voIFbHukrO2WdfAtzdxDq693kY01xaeZoQ4OJn/f3QI2oB/IBc g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10795\"; a=\"374704511\"", "E=Sophos;i=\"6.01,157,1684825200\"; d=\"scan'208\";a=\"374704511\"", "E=McAfee;i=\"6600,9927,10795\"; a=\"845735164\"", "E=Sophos;i=\"6.01,157,1684825200\"; d=\"scan'208\";a=\"845735164\"" ], "X-ExtLoop1": "1", "From": "Wenjing Qiao <wenjing.qiao@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com,\n Simei Su <simei.su@intel.com>,\n Pavan Kumar Linga <pavan.kumar.linga@intel.com>", "Subject": "[PATCH 12/14] common/idpf/base: refine comments and alignment", "Date": "Wed, 9 Aug 2023 01:33:06 +0000", "Message-Id": "<20230809013308.1449103-13-wenjing.qiao@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230809013308.1449103-1-wenjing.qiao@intel.com>", "References": "<20230809013308.1449103-1-wenjing.qiao@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Simei Su <simei.su@intel.com>\n\nRefine the macros and definitions by using 'tab' spaces and new\nlines whereever necessary. Also refine the comment in\n'idpf_ctlq_setup_regs'.\n\nSigned-off-by: Pavan Kumar Linga <pavan.kumar.linga@intel.com>\nSigned-off-by: Simei Su <simei.su@intel.com>\n---\n drivers/common/idpf/base/idpf_controlq.c | 2 +-\n drivers/common/idpf/base/idpf_controlq_api.h | 10 +----\n drivers/common/idpf/base/idpf_lan_pf_regs.h | 7 ++--\n drivers/common/idpf/base/idpf_lan_txrx.h | 43 ++++++++++----------\n drivers/common/idpf/base/idpf_lan_vf_regs.h | 25 ++++++++----\n 5 files changed, 46 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c\nindex da5c930578..c24bfd23ef 100644\n--- a/drivers/common/idpf/base/idpf_controlq.c\n+++ b/drivers/common/idpf/base/idpf_controlq.c\n@@ -13,7 +13,7 @@ static void\n idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq,\n \t\t struct idpf_ctlq_create_info *q_create_info)\n {\n-\t/* set head and tail registers in our local struct */\n+\t/* set control queue registers in our local struct */\n \tcq->reg.head = q_create_info->reg.head;\n \tcq->reg.tail = q_create_info->reg.tail;\n \tcq->reg.len = q_create_info->reg.len;\ndiff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h\nindex 78a54f6b4c..38f5d2df3c 100644\n--- a/drivers/common/idpf/base/idpf_controlq_api.h\n+++ b/drivers/common/idpf/base/idpf_controlq_api.h\n@@ -21,10 +21,7 @@ enum idpf_ctlq_type {\n \tIDPF_CTLQ_TYPE_RDMA_COMPL\t= 7\n };\n \n-/*\n- * Generic Control Queue Structures\n- */\n-\n+/* Generic Control Queue Structures */\n struct idpf_ctlq_reg {\n \t/* used for queue tracking */\n \tu32 head;\n@@ -157,10 +154,7 @@ enum idpf_mbx_opc {\n \tidpf_mbq_opc_send_msg_to_peer_drv\t= 0x0804,\n };\n \n-/*\n- * API supported for control queue management\n- */\n-\n+/* API supported for control queue management */\n /* Will init all required q including default mb. \"q_info\" is an array of\n * create_info structs equal to the number of control queues to be created.\n */\ndiff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h\nindex 8542620e01..e47afad6e9 100644\n--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h\n@@ -80,10 +80,11 @@\n /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is\n * spacing b/w itrn registers of the same vector.\n */\n-#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n-\t\t((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))\n+#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing)\t\t\\\n+\t((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))\n /* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */\n-#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))\n+#define PF_GLINT_ITR(_ITR, _INT)\t\\\n+\t(PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))\n #define PF_GLINT_ITR_MAX_INDEX\t\t2\n #define PF_GLINT_ITR_INTERVAL_S\t\t0\n #define PF_GLINT_ITR_INTERVAL_M\t\tIDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S)\ndiff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h\nindex 7b03693eb1..cc8f1cd2a5 100644\n--- a/drivers/common/idpf/base/idpf_lan_txrx.h\n+++ b/drivers/common/idpf/base/idpf_lan_txrx.h\n@@ -8,9 +8,9 @@\n #include \"idpf_osdep.h\"\n \n enum idpf_rss_hash {\n-\t/* Values 0 - 28 are reserved for future use */\n-\tIDPF_HASH_INVALID\t\t= 0,\n-\tIDPF_HASH_NONF_UNICAST_IPV4_UDP\t= 29,\n+\tIDPF_HASH_INVALID\t\t\t= 0,\n+\t/* Values 1 - 28 are reserved for future use */\n+\tIDPF_HASH_NONF_UNICAST_IPV4_UDP\t\t= 29,\n \tIDPF_HASH_NONF_MULTICAST_IPV4_UDP,\n \tIDPF_HASH_NONF_IPV4_UDP,\n \tIDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK,\n@@ -19,7 +19,7 @@ enum idpf_rss_hash {\n \tIDPF_HASH_NONF_IPV4_OTHER,\n \tIDPF_HASH_FRAG_IPV4,\n \t/* Values 37-38 are reserved */\n-\tIDPF_HASH_NONF_UNICAST_IPV6_UDP\t= 39,\n+\tIDPF_HASH_NONF_UNICAST_IPV6_UDP\t\t= 39,\n \tIDPF_HASH_NONF_MULTICAST_IPV6_UDP,\n \tIDPF_HASH_NONF_IPV6_UDP,\n \tIDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK,\n@@ -32,22 +32,23 @@ enum idpf_rss_hash {\n \tIDPF_HASH_NONF_FCOE_RX,\n \tIDPF_HASH_NONF_FCOE_OTHER,\n \t/* Values 51-62 are reserved */\n-\tIDPF_HASH_L2_PAYLOAD\t\t= 63,\n+\tIDPF_HASH_L2_PAYLOAD\t\t\t= 63,\n+\n \tIDPF_HASH_MAX\n };\n \n /* Supported RSS offloads */\n-#define IDPF_DEFAULT_RSS_HASH ( \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \\\n-\tBIT_ULL(IDPF_HASH_FRAG_IPV4) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \\\n-\tBIT_ULL(IDPF_HASH_FRAG_IPV6) | \\\n+#define IDPF_DEFAULT_RSS_HASH\t\t\t\\\n+\t(BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV4_TCP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) |\t\\\n+\tBIT_ULL(IDPF_HASH_FRAG_IPV4) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_UDP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_TCP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) |\t\\\n+\tBIT_ULL(IDPF_HASH_FRAG_IPV6) |\t\t\\\n \tBIT_ULL(IDPF_HASH_L2_PAYLOAD))\n \n \t/* TODO: Wrap below comment under internal flag\n@@ -55,11 +56,11 @@ enum idpf_rss_hash {\n \t * They are supported by FPK and future products\n \t */\n #define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) |\t\t\\\n \tBIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP))\n \n /* For idpf_splitq_base_tx_compl_desc */\ndiff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h\nindex b5ff9b2cc9..4c5249129e 100644\n--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h\n@@ -94,14 +94,23 @@\n * b/w itrn registers of the same vector\n */\n #define VF_INT_ITR0(_ITR)\t\t(0x00004C00 + ((_ITR) * 4))\n-#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n-\t\t ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))\n-/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */\n-#define VF_INT_ITRN(_INT, _ITR)\t(0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))\n-/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */\n-#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))\n-/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */\n-#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))\n+#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n+\t((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))\n+/* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing\n+ * is 0x40 and base register offset is 0x00002800\n+ */\n+#define VF_INT_ITRN(_INT, _ITR)\t\t\t\\\n+\t(0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))\n+/* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing\n+ * is 0x100 and base register offset is 0x00002C00\n+ */\n+#define VF_INT_ITRN_64(_INT, _ITR)\t\\\n+\t(0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))\n+/* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing\n+ * is 0x2000 and base register offset is 0x00072000\n+ */\n+#define VF_INT_ITRN_2K(_INT, _ITR)\t\\\n+\t(0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))\n #define VF_INT_ITRN_MAX_INDEX\t\t2\n #define VF_INT_ITRN_INTERVAL_S\t\t0\n #define VF_INT_ITRN_INTERVAL_M\t\tIDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S)\n", "prefixes": [ "12/14" ] }