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GET /api/patches/130034/?format=api
{ "id": 130034, "url": "http://patchwork.dpdk.org/api/patches/130034/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230809074046.121807-3-haifeil@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230809074046.121807-3-haifeil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230809074046.121807-3-haifeil@nvidia.com", "date": "2023-08-09T07:40:43", "name": "[2/5] common/mlx5: extend HCA attribute query for NSH", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "32c817373050b45ca73e2f63b97a0d3d4dc7f1f3", "submitter": { "id": 2131, "url": "http://patchwork.dpdk.org/api/people/2131/?format=api", "name": "Haifei Luo", "email": "haifeil@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230809074046.121807-3-haifeil@nvidia.com/mbox/", "series": [ { "id": 29140, "url": "http://patchwork.dpdk.org/api/series/29140/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29140", "date": "2023-08-09T07:40:41", "name": "support item NSH matching", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29140/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/130034/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/130034/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9692B43016;\n\tWed, 9 Aug 2023 09:41:39 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 71B6943273;\n\tWed, 9 Aug 2023 09:41:39 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2065.outbound.protection.outlook.com [40.107.92.65])\n by mails.dpdk.org (Postfix) with ESMTP id 4D48F43261\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Haifei Luo <haifeil@nvidia.com>", "To": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <matan@nvidia.com>,\n <shahafs@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, <thomas@monjalon.net>, <wisamm@nvidia.com>,\n <rasland@nvidia.com>, <roniba@nvidia.com>", "Subject": "[PATCH 2/5] common/mlx5: extend HCA attribute query for NSH", "Date": "Wed, 9 Aug 2023 10:40:43 +0300", "Message-ID": "<20230809074046.121807-3-haifeil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230809074046.121807-1-haifeil@nvidia.com>", "References": "<20230809074046.121807-1-haifeil@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000989EB:EE_|CH0PR12MB5236:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c5133bb9-4773-4917-6618-08db98ac0ec8", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n iKcHZgwm8J0dvjwNDmD0X3tirofmyDVtnV6xZ26rwF/aW0qIwFfV8qcrmxI+a4rrdnovpUPFsYgi+RpK9mXsLwoKQlQyE9CnZnON7DYW3Q0CS2yGlv37XWt7IBHs1EvmQ3iH8W8mgy4+xRBLXA+l1jBvDcsUzRT/Of6yp3RaD3SiPRw1f/ZNl+23d0mihJUrmIk2H5jaqvFJ5vgC1u6y8UZ5CPwmOkFDeBCaHiqmqXID0IOmJhk0fOJT2dfv8XPqbb5v//QsNQxXCDIY4QIqkozAoJTd4LNfbzr+ODX8hqmmThyxjgtqsvB4kuJr09mvaO+/CEw8iS+IVe8O9zP4dJ/bk7rG0Lf2cRj0h/kabtMC2e3KOwbbSnLrwK8/ak04SrsbID+dXo4qYay+rGiucdd/HpI5ghx/Uemswps8N1kqXxbH0I37lBTZj2y0l2wh59o5F+M0IzFFixAXxNbAWcbMCkHYstczbmHqMaXS+VU/4QA0xT0g6FOYR/HvkLNXOW9pmvU83T/ILir1zuyPOuwQjzINo09wuUnHx0nEGAxR6JS5vcIs9s7ZVmBqPDC6nd9TBez4mJJkpBhqGqgPXem8gAeZ0VI22x0k5c4eSIhfnrLS4v3k9/QbiRVIwSLmQmFQPoBEVG5LGNN/B94kmu/4GP1Ae7aGFoQ3UrjTfU84xoT5GuKI7PIhi0lFFq6eevHJpMMukPVDKqMgdf0Sy4LS7nNS3E2wTwbfT+dIkhB79CW3eI/aUMeZnWcgfYCW", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(346002)(396003)(39860400002)(136003)(376002)(451199021)(82310400008)(1800799006)(186006)(40470700004)(46966006)(36840700001)(1076003)(40480700001)(55016003)(26005)(107886003)(40460700003)(110136005)(54906003)(36756003)(5660300002)(86362001)(2906002)(4326008)(6636002)(70206006)(70586007)(8676002)(8936002)(316002)(41300700001)(6666004)(7696005)(478600001)(356005)(82740400003)(7636003)(426003)(36860700001)(83380400001)(47076005)(336012)(6286002)(16526019)(2616005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Aug 2023 07:41:35.2087 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c5133bb9-4773-4917-6618-08db98ac0ec8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000989EB.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH0PR12MB5236", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add NSH supporting field in two places:\n1. New HCA capability indicating NSH is supported\n2. New field in \"mlx5_ifc_per_protocol_networking_offload_caps_bits\"\n structure\n\nSigned-off-by: Haifei Luo <haifeil@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 4 +++-\n 3 files changed, 7 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 66a77159a0..830199212e 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1313,6 +1313,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->tunnel_stateless_gtp = MLX5_GET\n \t\t\t\t\t(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, tunnel_stateless_gtp);\n+\tattr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET\n+\t\t\t\t\t(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, tunnel_stateless_vxlan_gpe_nsh);\n \tattr->rss_ind_tbl_cap = MLX5_GET\n \t\t\t\t\t(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, rss_ind_tbl_cap);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex e071cd841f..11772431ae 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -196,6 +196,7 @@ struct mlx5_hca_attr {\n \tuint32_t tunnel_stateless_geneve_rx:1;\n \tuint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */\n \tuint32_t tunnel_stateless_gtp:1;\n+\tuint32_t tunnel_stateless_vxlan_gpe_nsh:1;\n \tuint32_t max_lso_cap;\n \tuint32_t scatter_fcs:1;\n \tuint32_t lro_cap:1;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 51f426c614..f005877dd7 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1964,7 +1964,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n \tu8 swp_lso[0x1];\n \tu8 reserved_at_23[0x8];\n \tu8 tunnel_stateless_gtp[0x1];\n-\tu8 reserved_at_25[0x4];\n+\tu8 reserved_at_25[0x2];\n+\tu8 tunnel_stateless_vxlan_gpe_nsh[0x1];\n+\tu8 reserved_at_28[0x1];\n \tu8 max_vxlan_udp_ports[0x8];\n \tu8 reserved_at_38[0x6];\n \tu8 max_geneve_opt_len[0x1];\n", "prefixes": [ "2/5" ] }