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GET /api/patches/130116/?format=api
{ "id": 130116, "url": "http://patchwork.dpdk.org/api/patches/130116/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230811085805.441256-2-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230811085805.441256-2-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230811085805.441256-2-ndabilpuram@marvell.com", "date": "2023-08-11T08:57:36", "name": "[02/31] common/cnxk: optimize time while configuring fc on VF", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "44a5c7174902d0c68c3bbd9602c3aa4242163195", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230811085805.441256-2-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 29177, "url": "http://patchwork.dpdk.org/api/series/29177/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29177", "date": "2023-08-11T08:57:35", "name": "[01/31] common/cnxk: add aura ref count mechanism", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29177/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/130116/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/130116/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D690F43032;\n\tFri, 11 Aug 2023 10:58:19 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6370A43254;\n\tFri, 11 Aug 2023 10:58:18 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 77A234325B\n for <dev@dpdk.org>; Fri, 11 Aug 2023 10:58:16 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 37AMjlID001539 for <dev@dpdk.org>; Fri, 11 Aug 2023 01:58:15 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r5c-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 11 Aug 2023 01:58:15 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Fri, 11 Aug 2023 01:58:13 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Fri, 11 Aug 2023 01:58:13 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 611743F706A;\n Fri, 11 Aug 2023 01:58:11 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=vJ+BPju+IfNBe5MDSFIrN0RQvc9MiW/rigEMw5zTwy4=;\n b=A6pX4aDNXeUkQtbr6FiEGK2Df7RP+MVvsdyAyrQss0rIgA8RBx8O4yVLczUWIzfmapzX\n YBVmKGHMnuvXkP1qbNRYuiv52vi2tjZKS/FPXrlRK38NVlcfgxdl/7A6P77vnSX3vVio\n tbLsQMUMLCW1OLDn4hYAkXEjgcLaw2UAE/LFtooHx0gayDGZsq7mLGw2hMVufDAw/yjs\n 6XOFXhvtjOMg3PA7PYPdWRGmtM14BfNWRdhgyirfUaQZCSWQEHir7sjf2Hfz9pUromdB\n QWTZn/jYVFdtFmOZGfqKsYVf6gFE44nXjELp5teNnd7crF1w9AZF11fDjvFOhq1vCH5v /A==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>, Rakesh Kudurumalla\n <rkudurumalla@marvell.com>", "Subject": "[PATCH 02/31] common/cnxk: optimize time while configuring fc on VF", "Date": "Fri, 11 Aug 2023 14:27:36 +0530", "Message-ID": "<20230811085805.441256-2-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230811085805.441256-1-ndabilpuram@marvell.com>", "References": "<20230811085805.441256-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "vQRtR5gweMJ0OOscrqC0rPXSgyfCs6Z5", "X-Proofpoint-GUID": "vQRtR5gweMJ0OOscrqC0rPXSgyfCs6Z5", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26\n definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Rakesh Kudurumalla <rkudurumalla@marvell.com>\n\nPFC configuration function is taking 8 ms due\nto mailbox communication to check whether sso is\nconnected to RQ and whether back pressure is enabled\non each aura. To optimize this time we are updating\naura attributes in nixlf and sso_ena parameter\nin RQ during write configuration and the same updated\nvalue is accessed while configuring flow control,\nreducing time to 6 ms.\n\nSigned-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>\n---\n drivers/common/cnxk/roc_nix_fc.c | 47 ++++++++----------------------\n drivers/common/cnxk/roc_npa.c | 16 +++++++++-\n drivers/common/cnxk/roc_npa_priv.h | 6 ++++\n 3 files changed, 33 insertions(+), 36 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex 1f5ef960da..d58b35268e 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -285,15 +285,11 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \tstruct roc_nix_fc_cfg tmp;\n \tuint64_t pool_drop_pct;\n \tstruct roc_nix_rq *rq;\n-\tint sso_ena = 0, rc;\n+\tint rc;\n \n \trq = nix->rqs[fc_cfg->rq_cfg.rq];\n-\t/* Check whether RQ is connected to SSO or not */\n-\tsso_ena = roc_nix_rq_is_sso_enable(roc_nix, fc_cfg->rq_cfg.rq);\n-\tif (sso_ena < 0)\n-\t\treturn -EINVAL;\n \n-\tif (sso_ena) {\n+\tif (rq->sso_ena) {\n \t\tpool_drop_pct = fc_cfg->rq_cfg.pool_drop_pct;\n \t\t/* Use default value for zero pct */\n \t\tif (fc_cfg->rq_cfg.enable && !pool_drop_pct)\n@@ -486,12 +482,10 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui\n \tuint32_t aura_id = roc_npa_aura_handle_to_aura(pool_id);\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct npa_lf *lf = idev_npa_obj_get();\n-\tstruct npa_aq_enq_req *req;\n-\tstruct npa_aq_enq_rsp *rsp;\n+\tstruct npa_aura_attr *aura_attr;\n \tuint8_t bp_thresh, bp_intf;\n-\tstruct mbox *mbox;\n \tuint16_t bpid;\n-\tint rc, i;\n+\tint i;\n \n \tif (roc_nix_is_sdp(roc_nix))\n \t\treturn;\n@@ -499,30 +493,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui\n \tif (!lf)\n \t\treturn;\n \n-\tmbox = lf->mbox;\n-\treq = mbox_alloc_msg_npa_aq_enq(mbox_get(mbox));\n-\tif (req == NULL) {\n-\t\tmbox_put(mbox);\n-\t\treturn;\n-\t}\n-\n-\treq->aura_id = aura_id;\n-\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\treq->op = NPA_AQ_INSTOP_READ;\n-\n-\trc = mbox_process_msg(mbox, (void *)&rsp);\n-\tmbox_put(mbox);\n-\tif (rc) {\n-\t\tplt_nix_dbg(\"Failed to read context of aura 0x%\" PRIx64, pool_id);\n-\t\treturn;\n-\t}\n+\taura_attr = &lf->aura_attr[aura_id];\n \n \tbp_intf = 1 << nix->is_nix1;\n-\tbp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift);\n+\tbp_thresh = NIX_RQ_AURA_THRESH(drop_percent, aura_attr->limit >> aura_attr->shift);\n \n-\tbpid = (rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid;\n+\tbpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid;\n \t/* BP is already enabled. */\n-\tif (rsp->aura.bp_ena && ena) {\n+\tif (aura_attr->bp_ena && ena) {\n \t\t/* Disable BP if BPIDs don't match and couldn't add new BPID. */\n \t\tif (bpid != nix->bpid[tc]) {\n \t\t\tuint16_t bpid_new = NIX_BPID_INVALID;\n@@ -537,7 +515,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui\n \t\t\t\t\tplt_err(\"Enabling backpressue failed on aura 0x%\" PRIx64,\n \t\t\t\t\t\tpool_id);\n \t\t\t} else {\n-\t\t\t\tlf->aura_attr[aura_id].ref_count++;\n+\t\t\t\taura_attr->ref_count++;\n \t\t\t\tplt_info(\"Ignoring port=%u tc=%u config on shared aura 0x%\" PRIx64,\n \t\t\t\t\t roc_nix->port_id, tc, pool_id);\n \t\t\t}\n@@ -547,14 +525,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui\n \t}\n \n \t/* BP was previously enabled but now disabled skip. */\n-\tif (rsp->aura.bp && ena)\n+\tif (aura_attr->bp && ena)\n \t\treturn;\n \n \tif (ena) {\n \t\tif (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true))\n \t\t\tplt_err(\"Enabling backpressue failed on aura 0x%\" PRIx64, pool_id);\n \t\telse\n-\t\t\tlf->aura_attr[aura_id].ref_count++;\n+\t\t\taura_attr->ref_count++;\n \t} else {\n \t\tbool found = !!force;\n \n@@ -564,8 +542,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui\n \t\t\t\tfound = true;\n \t\tif (!found)\n \t\t\treturn;\n-\t\telse if ((lf->aura_attr[aura_id].ref_count > 0) &&\n-\t\t\t --lf->aura_attr[aura_id].ref_count)\n+\t\telse if ((aura_attr->ref_count > 0) && --(aura_attr->ref_count))\n \t\t\treturn;\n \n \t\tif (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false))\ndiff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex 3b9a70028b..d5c3a53b9b 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -535,6 +535,8 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,\n \tif (rc)\n \t\tgoto stack_mem_free;\n \n+\tlf->aura_attr[aura_id].shift = aura->shift;\n+\tlf->aura_attr[aura_id].limit = aura->limit;\n \t*aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base);\n \t/* Update aura count */\n \troc_npa_aura_op_cnt_set(*aura_handle, 0, block_count);\n@@ -657,6 +659,8 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id,\n \tif (rc)\n \t\treturn rc;\n \n+\tlf->aura_attr[aura_id].shift = aura->shift;\n+\tlf->aura_attr[aura_id].limit = aura->limit;\n \t*aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base);\n \n \treturn 0;\n@@ -735,6 +739,9 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit)\n \taura_req->aura.limit = aura_limit;\n \taura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);\n \trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tgoto exit;\n+\tlf->aura_attr[aura_req->aura_id].limit = aura_req->aura.limit;\n exit:\n \tmbox_put(mbox);\n \treturn rc;\n@@ -931,7 +938,14 @@ roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf,\n \treq->aura.bp_ena = bp_intf;\n \treq->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);\n \n-\tmbox_process(mbox);\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tgoto fail;\n+\n+\tlf->aura_attr[aura_id].nix0_bpid = req->aura.nix0_bpid;\n+\tlf->aura_attr[aura_id].nix1_bpid = req->aura.nix1_bpid;\n+\tlf->aura_attr[aura_id].bp_ena = req->aura.bp_ena;\n+\tlf->aura_attr[aura_id].bp = req->aura.bp;\n fail:\n \tmbox_put(mbox);\n \treturn rc;\ndiff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h\nindex 704d93d5dc..060df9ab04 100644\n--- a/drivers/common/cnxk/roc_npa_priv.h\n+++ b/drivers/common/cnxk/roc_npa_priv.h\n@@ -50,6 +50,12 @@ struct npa_aura_lim {\n struct npa_aura_attr {\n \tint buf_type[ROC_NPA_BUF_TYPE_END];\n \tuint16_t ref_count;\n+\tuint64_t nix0_bpid;\n+\tuint64_t nix1_bpid;\n+\tuint64_t shift;\n+\tuint64_t limit;\n+\tuint8_t bp_ena;\n+\tuint8_t bp;\n };\n \n struct dev;\n", "prefixes": [ "02/31" ] }