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GET /api/patches/130632/?format=api
{ "id": 130632, "url": "http://patchwork.dpdk.org/api/patches/130632/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230822103600.3247680-3-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230822103600.3247680-3-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230822103600.3247680-3-michaelba@nvidia.com", "date": "2023-08-22T10:36:00", "name": "[2/2] net/mlx5: add random item support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8533ee5b1777a8db017abd104a7fe58fa78027b7", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230822103600.3247680-3-michaelba@nvidia.com/mbox/", "series": [ { "id": 29308, "url": "http://patchwork.dpdk.org/api/series/29308/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29308", "date": "2023-08-22T10:35:58", "name": "net/mlx5: add random item support", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29308/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/130632/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/130632/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 2/2] net/mlx5: add random item support", "Date": "Tue, 22 Aug 2023 13:36:00 +0300", "Message-ID": "<20230822103600.3247680-3-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230822103600.3247680-1-michaelba@nvidia.com>", "References": "<20230822103600.3247680-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE33:EE_|MN2PR12MB4454:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2dfae625-7bd8-40fd-cbb0-08dba2fba478", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230031)(4636009)(396003)(136003)(376002)(346002)(39860400002)(1800799009)(186009)(451199024)(82310400011)(36840700001)(40470700004)(46966006)(54906003)(6916009)(70206006)(70586007)(316002)(8676002)(8936002)(2616005)(107886003)(4326008)(7636003)(40460700003)(36756003)(41300700001)(1076003)(82740400003)(356005)(478600001)(6666004)(55016003)(40480700001)(83380400001)(2906002)(86362001)(7696005)(47076005)(36860700001)(336012)(426003)(5660300002)(26005)(6286002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Aug 2023 10:36:28.1990 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2dfae625-7bd8-40fd-cbb0-08dba2fba478", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE33.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4454", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for random item in HWS mode.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/features/mlx5.ini | 1 +\n doc/guides/nics/mlx5.rst | 10 +++++++++-\n doc/guides/rel_notes/release_23_11.rst | 4 ++++\n drivers/net/mlx5/mlx5_flow_dv.c | 5 +++++\n drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++\n 5 files changed, 24 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini\nindex c0e0b779cf..5606f435f2 100644\n--- a/doc/guides/nics/features/mlx5.ini\n+++ b/doc/guides/nics/features/mlx5.ini\n@@ -86,6 +86,7 @@ nvgre = Y\n port_id = Y\n port_representor = Y\n quota = Y\n+random = Y\n tag = Y\n tcp = Y\n udp = Y\ndiff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex eac67a7864..f754fab3e1 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -165,7 +165,7 @@ Features\n - Sub-Function.\n - Matching on represented port.\n - Matching on aggregated affinity.\n-\n+- Matching on random value.\n \n Limitations\n -----------\n@@ -554,6 +554,7 @@ Limitations\n - Modification of the MPLS header is supported only in HWS and only to copy from,\n the encapsulation level is always 0.\n - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.\n+ - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.\n - Encapsulation levels are not supported, can modify outermost header fields only.\n - Offsets cannot skip past the boundary of a field.\n - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``\n@@ -712,6 +713,13 @@ Limitations\n \n - The NIC egress flow rules on representor port are not supported.\n \n+- Match on random value:\n+\n+ - Supported only with HW Steering enabled (``dv_flow_en`` = 2).\n+ - Supported only in table with ``nb_flows=1``.\n+ - NIC ingress flow in group 0 is not supported.\n+ - Supports matching only 16 bits (LSB).\n+\n - During live migration to a new process set its flow engine as standby mode,\n the user should only program flow rules in group 0 (``fdb_def_rule_en=0``).\n Live migration is only supported under SWS (``dv_flow_en=1``).\ndiff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst\nindex 1e90bf83e7..8a4c04ed75 100644\n--- a/doc/guides/rel_notes/release_23_11.rst\n+++ b/doc/guides/rel_notes/release_23_11.rst\n@@ -76,6 +76,10 @@ New Features\n \n Added ``RTE_FLOW_ITEM_RANDOM`` to match random value.\n \n+* **Updated NVIDIA mlx5 net driver.**\n+\n+ * Added support for random value matching.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex a8dd9920e6..1238d00073 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -5385,6 +5385,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"modifications of the MPLS header \"\n \t\t\t\t\"is not supported\");\n+\tif (dst_data->field == RTE_FLOW_FIELD_RANDOM ||\n+\t src_data->field == RTE_FLOW_FIELD_RANDOM)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\"modifications of random value is not supported\");\n \tif (dst_data->field == RTE_FLOW_FIELD_MARK ||\n \t src_data->field == RTE_FLOW_FIELD_MARK)\n \t\tif (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 5395969eb0..6fe6103a37 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -3893,6 +3893,10 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action,\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"modifying Geneve VNI is not supported\");\n+\tif (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\"modifying random value is not supported\");\n \t/* Due to HW bug, tunnel MPLS header is read only. */\n \tif (action_conf->dst.field == RTE_FLOW_FIELD_MPLS)\n \t\treturn rte_flow_error_set(error, EINVAL,\n@@ -5375,6 +5379,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_ESP:\n \t\tcase RTE_FLOW_ITEM_TYPE_FLEX:\n \t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n+\t\tcase RTE_FLOW_ITEM_TYPE_RANDOM:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n \t\t\t/*\n", "prefixes": [ "2/2" ] }