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GET /api/patches/130675/?format=api
{ "id": 130675, "url": "http://patchwork.dpdk.org/api/patches/130675/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com", "date": "2023-08-22T10:46:10", "name": "[v1] drivers/crypto: cipher buffer alignment check", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e77afbeab9514d97334664e46f9d7a9b8ba81e0f", "submitter": { "id": 3155, "url": "http://patchwork.dpdk.org/api/people/3155/?format=api", "name": "Sivaramakrishnan Venkat", "email": "venkatx.sivaramakrishnan@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com/mbox/", "series": [ { "id": 29322, "url": "http://patchwork.dpdk.org/api/series/29322/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29322", "date": "2023-08-22T10:46:10", "name": "[v1] drivers/crypto: cipher buffer alignment check", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29322/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/130675/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/130675/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 22943430E2;\n\tWed, 23 Aug 2023 09:46:37 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EB795410F1;\n\tWed, 23 Aug 2023 09:46:36 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id AB2B24021D;\n Tue, 22 Aug 2023 12:46:18 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 22 Aug 2023 03:46:17 -0700", "from silpixa00401012.ir.intel.com ([10.243.23.140])\n by orsmga008.jf.intel.com with ESMTP; 22 Aug 2023 03:46:15 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1692701179; x=1724237179;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=p1T4KtM64lTYurXg+yXDnEkpddn8kOmnKRP7EHOGthk=;\n b=ChHf7wn/WixMvoBxSGBy9R9dlqzR2lA/b3Ue6NcyU96DPhY2vJdhlDit\n guNVDOomHHaCikE0EgPz5VI15oEnJBtK/L3JzDYlhMwXyQWFXRP3gZpLu\n nTFdDo63nYdwhdeJDA1Czk+UeybboHENLDLlH0vHHcm388wMgA1AuSUEk\n soDlW3t76rWhesc4LakPj83/uQtkqejFNujyzY3JasP3qFmXw44AuoL2Y\n NKQSg2x/0DYEsLjjQVbgqjR5CeTflvWc3v+ICIkDk/YFASWn33p96UgP0\n jG/FSxORqQ6V30MOe6Z6yzUhmyH+geCvOrvX9gn51X29nkYbc/6H6MbLJ Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10809\"; a=\"404847195\"", "E=Sophos;i=\"6.01,192,1684825200\"; d=\"scan'208\";a=\"404847195\"", "E=McAfee;i=\"6600,9927,10809\"; a=\"765699043\"", "E=Sophos;i=\"6.01,192,1684825200\"; d=\"scan'208\";a=\"765699043\"" ], "X-ExtLoop1": "1", "From": "Sivaramakrishnan VenkatX <venkatx.sivaramakrishnan@intel.com>", "To": "Kai Ji <kai.ji@intel.com>", "Cc": "dev@dpdk.org, stable@dpdk.org, gakhil@marvell.com, ciara.power@intel.com,\n Sivaramakrishnan VenkatX <venkatx.sivaramakrishnan@intel.com>", "Subject": "[PATCH v1] drivers/crypto: cipher buffer alignment check", "Date": "Tue, 22 Aug 2023 10:46:10 +0000", "Message-Id": "<20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Mailman-Approved-At": "Wed, 23 Aug 2023 09:46:36 +0200", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Cipher length alignment checked for 3DES-CBC and AES-CBC to avoid slice\nhang error in QAT CPM1.8\n\nSigned-off-by: Sivaramakrishnan VenkatX <venkatx.sivaramakrishnan@intel.com>\n---\n drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 21 ++++++++++++++++++++\n 1 file changed, 21 insertions(+)", "diff": "diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\nindex cab7e214c0..98504d925f 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n@@ -10,6 +10,13 @@\n #include \"qat_sym_session.h\"\n #include \"qat_sym.h\"\n \n+#define AES_OR_3DES_MISALIGNED (ctx->qat_mode == ICP_QAT_HW_CIPHER_CBC_MODE && \\\n+\t\t\t((((ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128) || \\\n+\t\t\t(ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES192) || \\\n+\t\t\t(ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES256)) && \\\n+\t\t\t(cipher_param->cipher_length % ICP_QAT_HW_AES_BLK_SZ)) || \\\n+\t\t\t((ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) && \\\n+\t\t\t(cipher_param->cipher_length % ICP_QAT_HW_3DES_BLK_SZ))))\n #define QAT_SYM_DP_GET_MAX_ENQ(q, c, n) \\\n \tRTE_MIN((q->max_inflights - q->enqueued + q->dequeued - c), n)\n \n@@ -699,6 +706,20 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx,\n \n \tcipher_param->cipher_offset = ofs.ofs.cipher.head;\n \tcipher_param->cipher_length = cipher_len;\n+\t/* Input cipher length alignment requirement for 3DES-CBC and AES-CBC.\n+\t * For 3DES-CBC cipher algo, ESP Payload size requires 8 Byte aligned.\n+\t * For AES-CBC cipher algo, ESP Payload size requires 16 Byte aligned.\n+\t * The alignment should be guaranteed by the ESP package padding field\n+\t * according to the RFC4303. Under this condition, QAT will pass through\n+\t * chain job as NULL cipher and NULL auth operation and report misalignment\n+\t * error detected.\n+\t */\n+\tif (AES_OR_3DES_MISALIGNED) {\n+\t\tQAT_LOG(ERR, \"Input cipher length alignment error detected.\\n\");\n+\t\tctx->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_NULL;\n+\t\tctx->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;\n+\t\tcipher_param->cipher_length = 0;\n+\t}\n \tqat_set_cipher_iv(cipher_param, cipher_iv, ctx->cipher_iv.length, req);\n \n \tauth_param->auth_off = ofs.ofs.auth.head;\n", "prefixes": [ "v1" ] }