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GET /api/patches/130886/?format=api
http://patchwork.dpdk.org/api/patches/130886/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230830155927.3566-9-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230830155927.3566-9-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230830155927.3566-9-syalavarthi@marvell.com", "date": "2023-08-30T15:58:58", "name": "[v1,08/34] ml/cnxk: update device handling functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b197745151e516a9dde94a70e0b410ec064f274e", "submitter": { "id": 2480, "url": "http://patchwork.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230830155927.3566-9-syalavarthi@marvell.com/mbox/", "series": [ { "id": 29376, "url": "http://patchwork.dpdk.org/api/series/29376/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29376", "date": "2023-08-30T15:58:50", "name": "Implemenation of revised ml/cnxk driver", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29376/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/130886/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/130886/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BA02541FD1;\n\tWed, 30 Aug 2023 18:00:19 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CD259402B3;\n\tWed, 30 Aug 2023 17:59:41 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id CC0154029C\n for <dev@dpdk.org>; Wed, 30 Aug 2023 17:59:36 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 37U86I6s012554 for <dev@dpdk.org>; Wed, 30 Aug 2023 08:59:36 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3st1y61ga5-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 30 Aug 2023 08:59:35 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Wed, 30 Aug 2023 08:59:34 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Wed, 30 Aug 2023 08:59:34 -0700", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 637F83F7080;\n Wed, 30 Aug 2023 08:59:34 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=hatF2CHhzl/qeOROzVk54Wuu3GZEikzN79jiAwd7sUk=;\n b=CTZAf1b4Bs292CjwITLjhsEMXadDazOFFInJ8p8INmi2cbXpMjINRADLlw0SsA9cPioO\n kBJNG2/MTveuxB07/88ZyKCBgyun5mSjZLvtAtwhDbPCw/1nH98IFeQ2idNZnUfcr1j2\n /dqfzyepAuRimipbgvtYu6B2naZTd2uQz7LDlcPuTfw/g7kwCckJFSZW4fYLUydx+44c\n QYGoTI/cGxYF9sOWOqH8Y7JMSU5qL7e2rKnOx2rI5yy758CGrKx1y0BsrjPz4oK77dRP\n c4tId0OWrfASD2otVLvvWx+tKvvHcA9mWeD0SFwyJzXXM1ERopkAyC9w8glBQPklSXR+ dw==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <aprabhu@marvell.com>,\n <ptakkar@marvell.com>", "Subject": "[PATCH v1 08/34] ml/cnxk: update device handling functions", "Date": "Wed, 30 Aug 2023 08:58:58 -0700", "Message-ID": "<20230830155927.3566-9-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.41.0", "In-Reply-To": "<20230830155927.3566-1-syalavarthi@marvell.com>", "References": "<20230830155927.3566-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "MMKDRMNZOSS4nnNjNBwT4gt1O9yAeIQg", "X-Proofpoint-GUID": "MMKDRMNZOSS4nnNjNBwT4gt1O9yAeIQg", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26\n definitions=2023-08-30_12,2023-08-29_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Implement CNXK wrapper functions for dev_info_get,\ndev_configure, dev_close, dev_start and dev_stop. The\nwrapper functions allocate / release common resources\nfor the ML driver and invoke device specific functions.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_ops.c | 230 ++------------------------\n drivers/ml/cnxk/cn10k_ml_ops.h | 16 +-\n drivers/ml/cnxk/cnxk_ml_dev.h | 3 +\n drivers/ml/cnxk/cnxk_ml_ops.c | 286 ++++++++++++++++++++++++++++++++-\n drivers/ml/cnxk/cnxk_ml_ops.h | 3 +\n 5 files changed, 314 insertions(+), 224 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex e6383283d31..0f32f3b2bbe 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -105,7 +105,7 @@ qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n \tsnprintf(name, size, \"cnxk_ml_qp_mem_%u:%u\", dev_id, qp_id);\n }\n \n-static int\n+int\n cnxk_ml_qp_destroy(const struct rte_ml_dev *dev, struct cnxk_ml_qp *qp)\n {\n \tconst struct rte_memzone *qp_mem;\n@@ -865,20 +865,12 @@ cn10k_ml_cache_model_data(struct rte_ml_dev *dev, uint16_t model_id)\n }\n \n int\n-cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n+cn10k_ml_dev_info_get(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_dev_info *dev_info)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n-\tstruct cnxk_ml_dev *cnxk_mldev;\n \n-\tif (dev_info == NULL)\n-\t\treturn -EINVAL;\n-\n-\tcnxk_mldev = dev->data->dev_private;\n \tcn10k_mldev = &cnxk_mldev->cn10k_mldev;\n \n-\tmemset(dev_info, 0, sizeof(struct rte_ml_dev_info));\n-\tdev_info->driver_name = dev->device->driver->name;\n-\tdev_info->max_models = ML_CNXK_MAX_MODELS;\n \tif (cn10k_mldev->hw_queue_lock)\n \t\tdev_info->max_queue_pairs = ML_CN10K_MAX_QP_PER_DEVICE_SL;\n \telse\n@@ -893,143 +885,17 @@ cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n }\n \n int\n-cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *conf)\n+cn10k_ml_dev_configure(struct cnxk_ml_dev *cnxk_mldev, const struct rte_ml_dev_config *conf)\n {\n-\tstruct rte_ml_dev_info dev_info;\n \tstruct cn10k_ml_dev *cn10k_mldev;\n-\tstruct cnxk_ml_dev *cnxk_mldev;\n-\tstruct cnxk_ml_model *model;\n \tstruct cn10k_ml_ocm *ocm;\n-\tstruct cnxk_ml_qp *qp;\n-\tuint16_t model_id;\n-\tuint32_t mz_size;\n \tuint16_t tile_id;\n-\tuint16_t qp_id;\n \tint ret;\n \n-\tif (dev == NULL || conf == NULL)\n-\t\treturn -EINVAL;\n+\tRTE_SET_USED(conf);\n \n-\t/* Get CN10K device handle */\n-\tcnxk_mldev = dev->data->dev_private;\n \tcn10k_mldev = &cnxk_mldev->cn10k_mldev;\n \n-\tcn10k_ml_dev_info_get(dev, &dev_info);\n-\tif (conf->nb_models > dev_info.max_models) {\n-\t\tplt_err(\"Invalid device config, nb_models > %u\\n\", dev_info.max_models);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (conf->nb_queue_pairs > dev_info.max_queue_pairs) {\n-\t\tplt_err(\"Invalid device config, nb_queue_pairs > %u\\n\", dev_info.max_queue_pairs);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (cnxk_mldev->state == ML_CNXK_DEV_STATE_PROBED) {\n-\t\tplt_ml_dbg(\"Configuring ML device, nb_queue_pairs = %u, nb_models = %u\",\n-\t\t\t conf->nb_queue_pairs, conf->nb_models);\n-\n-\t\t/* Load firmware */\n-\t\tret = cn10k_ml_fw_load(cnxk_mldev);\n-\t\tif (ret != 0)\n-\t\t\treturn ret;\n-\t} else if (cnxk_mldev->state == ML_CNXK_DEV_STATE_CONFIGURED) {\n-\t\tplt_ml_dbg(\"Re-configuring ML device, nb_queue_pairs = %u, nb_models = %u\",\n-\t\t\t conf->nb_queue_pairs, conf->nb_models);\n-\t} else if (cnxk_mldev->state == ML_CNXK_DEV_STATE_STARTED) {\n-\t\tplt_err(\"Device can't be reconfigured in started state\\n\");\n-\t\treturn -ENOTSUP;\n-\t} else if (cnxk_mldev->state == ML_CNXK_DEV_STATE_CLOSED) {\n-\t\tplt_err(\"Device can't be reconfigured after close\\n\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\t/* Configure queue-pairs */\n-\tif (dev->data->queue_pairs == NULL) {\n-\t\tmz_size = sizeof(dev->data->queue_pairs[0]) * conf->nb_queue_pairs;\n-\t\tdev->data->queue_pairs =\n-\t\t\trte_zmalloc(\"cn10k_mldev_queue_pairs\", mz_size, RTE_CACHE_LINE_SIZE);\n-\t\tif (dev->data->queue_pairs == NULL) {\n-\t\t\tdev->data->nb_queue_pairs = 0;\n-\t\t\tplt_err(\"Failed to get memory for queue_pairs, nb_queue_pairs %u\",\n-\t\t\t\tconf->nb_queue_pairs);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t} else { /* Re-configure */\n-\t\tvoid **queue_pairs;\n-\n-\t\t/* Release all queue pairs as ML spec doesn't support queue_pair_destroy. */\n-\t\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n-\t\t\tqp = dev->data->queue_pairs[qp_id];\n-\t\t\tif (qp != NULL) {\n-\t\t\t\tret = cn10k_ml_dev_queue_pair_release(dev, qp_id);\n-\t\t\t\tif (ret < 0)\n-\t\t\t\t\treturn ret;\n-\t\t\t}\n-\t\t}\n-\n-\t\tqueue_pairs = dev->data->queue_pairs;\n-\t\tqueue_pairs =\n-\t\t\trte_realloc(queue_pairs, sizeof(queue_pairs[0]) * conf->nb_queue_pairs,\n-\t\t\t\t RTE_CACHE_LINE_SIZE);\n-\t\tif (queue_pairs == NULL) {\n-\t\t\tdev->data->nb_queue_pairs = 0;\n-\t\t\tplt_err(\"Failed to realloc queue_pairs, nb_queue_pairs = %u\",\n-\t\t\t\tconf->nb_queue_pairs);\n-\t\t\tret = -ENOMEM;\n-\t\t\tgoto error;\n-\t\t}\n-\n-\t\tmemset(queue_pairs, 0, sizeof(queue_pairs[0]) * conf->nb_queue_pairs);\n-\t\tdev->data->queue_pairs = queue_pairs;\n-\t}\n-\tdev->data->nb_queue_pairs = conf->nb_queue_pairs;\n-\n-\t/* Allocate ML models */\n-\tif (dev->data->models == NULL) {\n-\t\tmz_size = sizeof(dev->data->models[0]) * conf->nb_models;\n-\t\tdev->data->models = rte_zmalloc(\"cn10k_mldev_models\", mz_size, RTE_CACHE_LINE_SIZE);\n-\t\tif (dev->data->models == NULL) {\n-\t\t\tdev->data->nb_models = 0;\n-\t\t\tplt_err(\"Failed to get memory for ml_models, nb_models %u\",\n-\t\t\t\tconf->nb_models);\n-\t\t\tret = -ENOMEM;\n-\t\t\tgoto error;\n-\t\t}\n-\t} else {\n-\t\t/* Re-configure */\n-\t\tvoid **models;\n-\n-\t\t/* Stop and unload all models */\n-\t\tfor (model_id = 0; model_id < dev->data->nb_models; model_id++) {\n-\t\t\tmodel = dev->data->models[model_id];\n-\t\t\tif (model != NULL) {\n-\t\t\t\tif (model->state == ML_CNXK_MODEL_STATE_STARTED) {\n-\t\t\t\t\tif (cn10k_ml_model_stop(dev, model_id) != 0)\n-\t\t\t\t\t\tplt_err(\"Could not stop model %u\", model_id);\n-\t\t\t\t}\n-\t\t\t\tif (model->state == ML_CNXK_MODEL_STATE_LOADED) {\n-\t\t\t\t\tif (cn10k_ml_model_unload(dev, model_id) != 0)\n-\t\t\t\t\t\tplt_err(\"Could not unload model %u\", model_id);\n-\t\t\t\t}\n-\t\t\t\tdev->data->models[model_id] = NULL;\n-\t\t\t}\n-\t\t}\n-\n-\t\tmodels = dev->data->models;\n-\t\tmodels = rte_realloc(models, sizeof(models[0]) * conf->nb_models,\n-\t\t\t\t RTE_CACHE_LINE_SIZE);\n-\t\tif (models == NULL) {\n-\t\t\tdev->data->nb_models = 0;\n-\t\t\tplt_err(\"Failed to realloc ml_models, nb_models = %u\", conf->nb_models);\n-\t\t\tret = -ENOMEM;\n-\t\t\tgoto error;\n-\t\t}\n-\t\tmemset(models, 0, sizeof(models[0]) * conf->nb_models);\n-\t\tdev->data->models = models;\n-\t}\n-\tdev->data->nb_models = conf->nb_models;\n-\n \tocm = &cn10k_mldev->ocm;\n \tocm->num_tiles = ML_CN10K_OCM_NUMTILES;\n \tocm->size_per_tile = ML_CN10K_OCM_TILESIZE;\n@@ -1042,8 +908,7 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \t\trte_zmalloc(\"ocm_mask\", ocm->mask_words * ocm->num_tiles, RTE_CACHE_LINE_SIZE);\n \tif (ocm->ocm_mask == NULL) {\n \t\tplt_err(\"Unable to allocate memory for OCM mask\");\n-\t\tret = -ENOMEM;\n-\t\tgoto error;\n+\t\treturn -ENOMEM;\n \t}\n \n \tfor (tile_id = 0; tile_id < ocm->num_tiles; tile_id++) {\n@@ -1054,10 +919,10 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \trte_spinlock_init(&ocm->lock);\n \n \t/* Initialize xstats */\n-\tret = cn10k_ml_xstats_init(dev);\n+\tret = cn10k_ml_xstats_init(cnxk_mldev->mldev);\n \tif (ret != 0) {\n \t\tplt_err(\"Failed to initialize xstats\");\n-\t\tgoto error;\n+\t\treturn ret;\n \t}\n \n \t/* Set JCMDQ enqueue function */\n@@ -1071,77 +936,25 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \tcn10k_mldev->set_poll_ptr = cn10k_ml_set_poll_ptr;\n \tcn10k_mldev->get_poll_ptr = cn10k_ml_get_poll_ptr;\n \n-\tdev->enqueue_burst = cn10k_ml_enqueue_burst;\n-\tdev->dequeue_burst = cn10k_ml_dequeue_burst;\n-\tdev->op_error_get = cn10k_ml_op_error_get;\n-\n-\tcnxk_mldev->nb_models_loaded = 0;\n-\tcnxk_mldev->nb_models_started = 0;\n-\tcnxk_mldev->nb_models_stopped = 0;\n-\tcnxk_mldev->nb_models_unloaded = 0;\n-\tcnxk_mldev->state = ML_CNXK_DEV_STATE_CONFIGURED;\n+\tcnxk_mldev->mldev->enqueue_burst = cn10k_ml_enqueue_burst;\n+\tcnxk_mldev->mldev->dequeue_burst = cn10k_ml_dequeue_burst;\n+\tcnxk_mldev->mldev->op_error_get = cn10k_ml_op_error_get;\n \n \treturn 0;\n-\n-error:\n-\trte_free(dev->data->queue_pairs);\n-\n-\trte_free(dev->data->models);\n-\n-\treturn ret;\n }\n \n int\n-cn10k_ml_dev_close(struct rte_ml_dev *dev)\n+cn10k_ml_dev_close(struct cnxk_ml_dev *cnxk_mldev)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n-\tstruct cnxk_ml_dev *cnxk_mldev;\n-\tstruct cnxk_ml_model *model;\n-\tstruct cnxk_ml_qp *qp;\n-\tuint16_t model_id;\n-\tuint16_t qp_id;\n \n-\tif (dev == NULL)\n-\t\treturn -EINVAL;\n-\n-\tcnxk_mldev = dev->data->dev_private;\n \tcn10k_mldev = &cnxk_mldev->cn10k_mldev;\n \n \t/* Release ocm_mask memory */\n \trte_free(cn10k_mldev->ocm.ocm_mask);\n \n-\t/* Stop and unload all models */\n-\tfor (model_id = 0; model_id < dev->data->nb_models; model_id++) {\n-\t\tmodel = dev->data->models[model_id];\n-\t\tif (model != NULL) {\n-\t\t\tif (model->state == ML_CNXK_MODEL_STATE_STARTED) {\n-\t\t\t\tif (cn10k_ml_model_stop(dev, model_id) != 0)\n-\t\t\t\t\tplt_err(\"Could not stop model %u\", model_id);\n-\t\t\t}\n-\t\t\tif (model->state == ML_CNXK_MODEL_STATE_LOADED) {\n-\t\t\t\tif (cn10k_ml_model_unload(dev, model_id) != 0)\n-\t\t\t\t\tplt_err(\"Could not unload model %u\", model_id);\n-\t\t\t}\n-\t\t\tdev->data->models[model_id] = NULL;\n-\t\t}\n-\t}\n-\n-\trte_free(dev->data->models);\n-\n-\t/* Destroy all queue pairs */\n-\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n-\t\tqp = dev->data->queue_pairs[qp_id];\n-\t\tif (qp != NULL) {\n-\t\t\tif (cnxk_ml_qp_destroy(dev, qp) != 0)\n-\t\t\t\tplt_err(\"Could not destroy queue pair %u\", qp_id);\n-\t\t\tdev->data->queue_pairs[qp_id] = NULL;\n-\t\t}\n-\t}\n-\n-\trte_free(dev->data->queue_pairs);\n-\n \t/* Un-initialize xstats */\n-\tcn10k_ml_xstats_uninit(dev);\n+\tcn10k_ml_xstats_uninit(cnxk_mldev->mldev);\n \n \t/* Unload firmware */\n \tcn10k_ml_fw_unload(cnxk_mldev);\n@@ -1158,20 +971,15 @@ cn10k_ml_dev_close(struct rte_ml_dev *dev)\n \troc_ml_reg_write64(&cn10k_mldev->roc, 0, ML_MLR_BASE);\n \tplt_ml_dbg(\"ML_MLR_BASE = 0x%016lx\", roc_ml_reg_read64(&cn10k_mldev->roc, ML_MLR_BASE));\n \n-\tcnxk_mldev->state = ML_CNXK_DEV_STATE_CLOSED;\n-\n-\t/* Remove PCI device */\n-\treturn rte_dev_remove(dev->device);\n+\treturn 0;\n }\n \n int\n-cn10k_ml_dev_start(struct rte_ml_dev *dev)\n+cn10k_ml_dev_start(struct cnxk_ml_dev *cnxk_mldev)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n-\tstruct cnxk_ml_dev *cnxk_mldev;\n \tuint64_t reg_val64;\n \n-\tcnxk_mldev = dev->data->dev_private;\n \tcn10k_mldev = &cnxk_mldev->cn10k_mldev;\n \n \treg_val64 = roc_ml_reg_read64(&cn10k_mldev->roc, ML_CFG);\n@@ -1179,19 +987,15 @@ cn10k_ml_dev_start(struct rte_ml_dev *dev)\n \troc_ml_reg_write64(&cn10k_mldev->roc, reg_val64, ML_CFG);\n \tplt_ml_dbg(\"ML_CFG => 0x%016lx\", roc_ml_reg_read64(&cn10k_mldev->roc, ML_CFG));\n \n-\tcnxk_mldev->state = ML_CNXK_DEV_STATE_STARTED;\n-\n \treturn 0;\n }\n \n int\n-cn10k_ml_dev_stop(struct rte_ml_dev *dev)\n+cn10k_ml_dev_stop(struct cnxk_ml_dev *cnxk_mldev)\n {\n \tstruct cn10k_ml_dev *cn10k_mldev;\n-\tstruct cnxk_ml_dev *cnxk_mldev;\n \tuint64_t reg_val64;\n \n-\tcnxk_mldev = dev->data->dev_private;\n \tcn10k_mldev = &cnxk_mldev->cn10k_mldev;\n \n \treg_val64 = roc_ml_reg_read64(&cn10k_mldev->roc, ML_CFG);\n@@ -1199,8 +1003,6 @@ cn10k_ml_dev_stop(struct rte_ml_dev *dev)\n \troc_ml_reg_write64(&cn10k_mldev->roc, reg_val64, ML_CFG);\n \tplt_ml_dbg(\"ML_CFG => 0x%016lx\", roc_ml_reg_read64(&cn10k_mldev->roc, ML_CFG));\n \n-\tcnxk_mldev->state = ML_CNXK_DEV_STATE_CONFIGURED;\n-\n \treturn 0;\n }\n \n@@ -1221,7 +1023,7 @@ cn10k_ml_dev_queue_pair_setup(struct rte_ml_dev *dev, uint16_t queue_pair_id,\n \tif (dev->data->queue_pairs[queue_pair_id] != NULL)\n \t\tcn10k_ml_dev_queue_pair_release(dev, queue_pair_id);\n \n-\tcn10k_ml_dev_info_get(dev, &dev_info);\n+\tcnxk_ml_dev_info_get(dev, &dev_info);\n \tif ((qp_conf->nb_desc > dev_info.max_desc) || (qp_conf->nb_desc == 0)) {\n \t\tplt_err(\"Could not setup queue pair for %u descriptors\", qp_conf->nb_desc);\n \t\treturn -EINVAL;\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex 16480b9ad89..d50b5bede71 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -10,6 +10,9 @@\n \n #include <roc_api.h>\n \n+struct cnxk_ml_dev;\n+struct cnxk_ml_qp;\n+\n /* Firmware version string length */\n #define MLDEV_FIRMWARE_VERSION_LENGTH 32\n \n@@ -286,11 +289,11 @@ struct cn10k_ml_req {\n };\n \n /* Device ops */\n-int cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info);\n-int cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *conf);\n-int cn10k_ml_dev_close(struct rte_ml_dev *dev);\n-int cn10k_ml_dev_start(struct rte_ml_dev *dev);\n-int cn10k_ml_dev_stop(struct rte_ml_dev *dev);\n+int cn10k_ml_dev_info_get(struct cnxk_ml_dev *cnxk_mldev, struct rte_ml_dev_info *dev_info);\n+int cn10k_ml_dev_configure(struct cnxk_ml_dev *cnxk_mldev, const struct rte_ml_dev_config *conf);\n+int cn10k_ml_dev_close(struct cnxk_ml_dev *cnxk_mldev);\n+int cn10k_ml_dev_start(struct cnxk_ml_dev *cnxk_mldev);\n+int cn10k_ml_dev_stop(struct cnxk_ml_dev *cnxk_mldev);\n int cn10k_ml_dev_dump(struct rte_ml_dev *dev, FILE *fp);\n int cn10k_ml_dev_selftest(struct rte_ml_dev *dev);\n int cn10k_ml_dev_queue_pair_setup(struct rte_ml_dev *dev, uint16_t queue_pair_id,\n@@ -336,4 +339,7 @@ __rte_hot int cn10k_ml_op_error_get(struct rte_ml_dev *dev, struct rte_ml_op *op\n \t\t\t\t struct rte_ml_op_error *error);\n __rte_hot int cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op);\n \n+/* Temporarily set below functions as non-static */\n+int cnxk_ml_qp_destroy(const struct rte_ml_dev *dev, struct cnxk_ml_qp *qp);\n+\n #endif /* _CN10K_ML_OPS_H_ */\ndiff --git a/drivers/ml/cnxk/cnxk_ml_dev.h b/drivers/ml/cnxk/cnxk_ml_dev.h\nindex 51315de6227..02605fa28fc 100644\n--- a/drivers/ml/cnxk/cnxk_ml_dev.h\n+++ b/drivers/ml/cnxk/cnxk_ml_dev.h\n@@ -53,6 +53,9 @@ struct cnxk_ml_dev {\n \n \t/* CN10K device structure */\n \tstruct cn10k_ml_dev cn10k_mldev;\n+\n+\t/* Maximum number of layers */\n+\tuint64_t max_nb_layers;\n };\n \n #endif /* _CNXK_ML_DEV_H_ */\ndiff --git a/drivers/ml/cnxk/cnxk_ml_ops.c b/drivers/ml/cnxk/cnxk_ml_ops.c\nindex 89e0d9d32c3..83d5cbae58b 100644\n--- a/drivers/ml/cnxk/cnxk_ml_ops.c\n+++ b/drivers/ml/cnxk/cnxk_ml_ops.c\n@@ -7,15 +7,291 @@\n \n #include \"cn10k_ml_ops.h\"\n \n+#include \"cnxk_ml_dev.h\"\n+#include \"cnxk_ml_io.h\"\n+#include \"cnxk_ml_model.h\"\n #include \"cnxk_ml_ops.h\"\n \n+int\n+cnxk_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n+{\n+\tstruct cnxk_ml_dev *cnxk_mldev;\n+\n+\tif (dev == NULL || dev_info == NULL)\n+\t\treturn -EINVAL;\n+\n+\tcnxk_mldev = dev->data->dev_private;\n+\n+\tmemset(dev_info, 0, sizeof(struct rte_ml_dev_info));\n+\tdev_info->driver_name = dev->device->driver->name;\n+\tdev_info->max_models = ML_CNXK_MAX_MODELS;\n+\n+\treturn cn10k_ml_dev_info_get(cnxk_mldev, dev_info);\n+}\n+\n+static int\n+cnxk_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *conf)\n+{\n+\tstruct rte_ml_dev_info dev_info;\n+\tstruct cnxk_ml_dev *cnxk_mldev;\n+\tstruct cnxk_ml_model *model;\n+\tstruct cnxk_ml_qp *qp;\n+\tuint16_t model_id;\n+\tuint32_t mz_size;\n+\tuint16_t qp_id;\n+\tint ret;\n+\n+\tif (dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\t/* Get CNXK device handle */\n+\tcnxk_mldev = dev->data->dev_private;\n+\n+\tcnxk_ml_dev_info_get(dev, &dev_info);\n+\tif (conf->nb_models > dev_info.max_models) {\n+\t\tplt_err(\"Invalid device config, nb_models > %u\\n\", dev_info.max_models);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->nb_queue_pairs > dev_info.max_queue_pairs) {\n+\t\tplt_err(\"Invalid device config, nb_queue_pairs > %u\\n\", dev_info.max_queue_pairs);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (cnxk_mldev->state == ML_CNXK_DEV_STATE_PROBED) {\n+\t\tplt_ml_dbg(\"Configuring ML device, nb_queue_pairs = %u, nb_models = %u\",\n+\t\t\t conf->nb_queue_pairs, conf->nb_models);\n+\n+\t\t/* Load firmware */\n+\t\tret = cn10k_ml_fw_load(cnxk_mldev);\n+\t\tif (ret != 0)\n+\t\t\treturn ret;\n+\t} else if (cnxk_mldev->state == ML_CNXK_DEV_STATE_CONFIGURED) {\n+\t\tplt_ml_dbg(\"Re-configuring ML device, nb_queue_pairs = %u, nb_models = %u\",\n+\t\t\t conf->nb_queue_pairs, conf->nb_models);\n+\t} else if (cnxk_mldev->state == ML_CNXK_DEV_STATE_STARTED) {\n+\t\tplt_err(\"Device can't be reconfigured in started state\\n\");\n+\t\treturn -ENOTSUP;\n+\t} else if (cnxk_mldev->state == ML_CNXK_DEV_STATE_CLOSED) {\n+\t\tplt_err(\"Device can't be reconfigured after close\\n\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\t/* Configure queue-pairs */\n+\tif (dev->data->queue_pairs == NULL) {\n+\t\tmz_size = sizeof(dev->data->queue_pairs[0]) * conf->nb_queue_pairs;\n+\t\tdev->data->queue_pairs =\n+\t\t\trte_zmalloc(\"cnxk_mldev_queue_pairs\", mz_size, RTE_CACHE_LINE_SIZE);\n+\t\tif (dev->data->queue_pairs == NULL) {\n+\t\t\tdev->data->nb_queue_pairs = 0;\n+\t\t\tplt_err(\"Failed to get memory for queue_pairs, nb_queue_pairs %u\",\n+\t\t\t\tconf->nb_queue_pairs);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t} else { /* Re-configure */\n+\t\tvoid **queue_pairs;\n+\n+\t\t/* Release all queue pairs as ML spec doesn't support queue_pair_destroy. */\n+\t\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n+\t\t\tqp = dev->data->queue_pairs[qp_id];\n+\t\t\tif (qp != NULL) {\n+\t\t\t\tret = cn10k_ml_dev_queue_pair_release(dev, qp_id);\n+\t\t\t\tif (ret < 0)\n+\t\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\tqueue_pairs = dev->data->queue_pairs;\n+\t\tqueue_pairs =\n+\t\t\trte_realloc(queue_pairs, sizeof(queue_pairs[0]) * conf->nb_queue_pairs,\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\t\tif (queue_pairs == NULL) {\n+\t\t\tdev->data->nb_queue_pairs = 0;\n+\t\t\tplt_err(\"Failed to realloc queue_pairs, nb_queue_pairs = %u\",\n+\t\t\t\tconf->nb_queue_pairs);\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\n+\t\tmemset(queue_pairs, 0, sizeof(queue_pairs[0]) * conf->nb_queue_pairs);\n+\t\tdev->data->queue_pairs = queue_pairs;\n+\t}\n+\tdev->data->nb_queue_pairs = conf->nb_queue_pairs;\n+\n+\t/* Allocate ML models */\n+\tif (dev->data->models == NULL) {\n+\t\tmz_size = sizeof(dev->data->models[0]) * conf->nb_models;\n+\t\tdev->data->models = rte_zmalloc(\"cnxk_mldev_models\", mz_size, RTE_CACHE_LINE_SIZE);\n+\t\tif (dev->data->models == NULL) {\n+\t\t\tdev->data->nb_models = 0;\n+\t\t\tplt_err(\"Failed to get memory for ml_models, nb_models %u\",\n+\t\t\t\tconf->nb_models);\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\t} else {\n+\t\t/* Re-configure */\n+\t\tvoid **models;\n+\n+\t\t/* Stop and unload all models */\n+\t\tfor (model_id = 0; model_id < dev->data->nb_models; model_id++) {\n+\t\t\tmodel = dev->data->models[model_id];\n+\t\t\tif (model != NULL) {\n+\t\t\t\tif (model->state == ML_CNXK_MODEL_STATE_STARTED) {\n+\t\t\t\t\tif (cn10k_ml_model_stop(dev, model_id) != 0)\n+\t\t\t\t\t\tplt_err(\"Could not stop model %u\", model_id);\n+\t\t\t\t}\n+\t\t\t\tif (model->state == ML_CNXK_MODEL_STATE_LOADED) {\n+\t\t\t\t\tif (cn10k_ml_model_unload(dev, model_id) != 0)\n+\t\t\t\t\t\tplt_err(\"Could not unload model %u\", model_id);\n+\t\t\t\t}\n+\t\t\t\tdev->data->models[model_id] = NULL;\n+\t\t\t}\n+\t\t}\n+\n+\t\tmodels = dev->data->models;\n+\t\tmodels = rte_realloc(models, sizeof(models[0]) * conf->nb_models,\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\t\tif (models == NULL) {\n+\t\t\tdev->data->nb_models = 0;\n+\t\t\tplt_err(\"Failed to realloc ml_models, nb_models = %u\", conf->nb_models);\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tmemset(models, 0, sizeof(models[0]) * conf->nb_models);\n+\t\tdev->data->models = models;\n+\t}\n+\tdev->data->nb_models = conf->nb_models;\n+\n+\tret = cn10k_ml_dev_configure(cnxk_mldev, conf);\n+\tif (ret != 0) {\n+\t\tplt_err(\"Failed to configure CN10K ML Device\");\n+\t\tgoto error;\n+\t}\n+\n+\t/* Set device capabilities */\n+\tcnxk_mldev->max_nb_layers =\n+\t\tcnxk_mldev->cn10k_mldev.fw.req->cn10k_req.jd.fw_load.cap.s.max_models;\n+\n+\tcnxk_mldev->nb_models_loaded = 0;\n+\tcnxk_mldev->nb_models_started = 0;\n+\tcnxk_mldev->nb_models_stopped = 0;\n+\tcnxk_mldev->nb_models_unloaded = 0;\n+\tcnxk_mldev->state = ML_CNXK_DEV_STATE_CONFIGURED;\n+\n+\treturn 0;\n+\n+error:\n+\trte_free(dev->data->queue_pairs);\n+\trte_free(dev->data->models);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cnxk_ml_dev_close(struct rte_ml_dev *dev)\n+{\n+\tstruct cnxk_ml_dev *cnxk_mldev;\n+\tstruct cnxk_ml_model *model;\n+\tstruct cnxk_ml_qp *qp;\n+\tuint16_t model_id;\n+\tuint16_t qp_id;\n+\n+\tif (dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\tcnxk_mldev = dev->data->dev_private;\n+\n+\tif (cn10k_ml_dev_close(cnxk_mldev) != 0)\n+\t\tplt_err(\"Failed to close CN10K ML Device\");\n+\n+\t/* Stop and unload all models */\n+\tfor (model_id = 0; model_id < dev->data->nb_models; model_id++) {\n+\t\tmodel = dev->data->models[model_id];\n+\t\tif (model != NULL) {\n+\t\t\tif (model->state == ML_CNXK_MODEL_STATE_STARTED) {\n+\t\t\t\tif (cn10k_ml_model_stop(dev, model_id) != 0)\n+\t\t\t\t\tplt_err(\"Could not stop model %u\", model_id);\n+\t\t\t}\n+\t\t\tif (model->state == ML_CNXK_MODEL_STATE_LOADED) {\n+\t\t\t\tif (cn10k_ml_model_unload(dev, model_id) != 0)\n+\t\t\t\t\tplt_err(\"Could not unload model %u\", model_id);\n+\t\t\t}\n+\t\t\tdev->data->models[model_id] = NULL;\n+\t\t}\n+\t}\n+\n+\trte_free(dev->data->models);\n+\n+\t/* Destroy all queue pairs */\n+\tfor (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {\n+\t\tqp = dev->data->queue_pairs[qp_id];\n+\t\tif (qp != NULL) {\n+\t\t\tif (cnxk_ml_qp_destroy(dev, qp) != 0)\n+\t\t\t\tplt_err(\"Could not destroy queue pair %u\", qp_id);\n+\t\t\tdev->data->queue_pairs[qp_id] = NULL;\n+\t\t}\n+\t}\n+\n+\trte_free(dev->data->queue_pairs);\n+\n+\tcnxk_mldev->state = ML_CNXK_DEV_STATE_CLOSED;\n+\n+\t/* Remove PCI device */\n+\treturn rte_dev_remove(dev->device);\n+}\n+\n+static int\n+cnxk_ml_dev_start(struct rte_ml_dev *dev)\n+{\n+\tstruct cnxk_ml_dev *cnxk_mldev;\n+\tint ret;\n+\n+\tif (dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\tcnxk_mldev = dev->data->dev_private;\n+\n+\tret = cn10k_ml_dev_start(cnxk_mldev);\n+\tif (ret != 0) {\n+\t\tplt_err(\"Failed to start CN10K ML Device\");\n+\t\treturn ret;\n+\t}\n+\n+\tcnxk_mldev->state = ML_CNXK_DEV_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+static int\n+cnxk_ml_dev_stop(struct rte_ml_dev *dev)\n+{\n+\tstruct cnxk_ml_dev *cnxk_mldev;\n+\tint ret;\n+\n+\tif (dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\tcnxk_mldev = dev->data->dev_private;\n+\n+\tret = cn10k_ml_dev_stop(cnxk_mldev);\n+\tif (ret != 0) {\n+\t\tplt_err(\"Failed to stop CN10K ML Device\");\n+\t\treturn ret;\n+\t}\n+\n+\tcnxk_mldev->state = ML_CNXK_DEV_STATE_CONFIGURED;\n+\n+\treturn 0;\n+}\n+\n struct rte_ml_dev_ops cnxk_ml_ops = {\n \t/* Device control ops */\n-\t.dev_info_get = cn10k_ml_dev_info_get,\n-\t.dev_configure = cn10k_ml_dev_configure,\n-\t.dev_close = cn10k_ml_dev_close,\n-\t.dev_start = cn10k_ml_dev_start,\n-\t.dev_stop = cn10k_ml_dev_stop,\n+\t.dev_info_get = cnxk_ml_dev_info_get,\n+\t.dev_configure = cnxk_ml_dev_configure,\n+\t.dev_close = cnxk_ml_dev_close,\n+\t.dev_start = cnxk_ml_dev_start,\n+\t.dev_stop = cnxk_ml_dev_stop,\n \t.dev_dump = cn10k_ml_dev_dump,\n \t.dev_selftest = cn10k_ml_dev_selftest,\n \ndiff --git a/drivers/ml/cnxk/cnxk_ml_ops.h b/drivers/ml/cnxk/cnxk_ml_ops.h\nindex a925c075809..2996928d7d0 100644\n--- a/drivers/ml/cnxk/cnxk_ml_ops.h\n+++ b/drivers/ml/cnxk/cnxk_ml_ops.h\n@@ -62,4 +62,7 @@ struct cnxk_ml_qp {\n \n extern struct rte_ml_dev_ops cnxk_ml_ops;\n \n+/* Temporarily set cnxk driver functions as non-static */\n+int cnxk_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info);\n+\n #endif /* _CNXK_ML_OPS_H_ */\n", "prefixes": [ "v1", "08/34" ] }{ "id": 130886, "url": "