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GET /api/patches/131094/?format=api
{ "id": 131094, "url": "http://patchwork.dpdk.org/api/patches/131094/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230901121824.3250409-1-mko-plv@napatech.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230901121824.3250409-1-mko-plv@napatech.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230901121824.3250409-1-mko-plv@napatech.com", "date": "2023-09-01T12:18:17", "name": "[v13,1/8] net/ntnic: initial commit which adds register defines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5e3c4e9952262198ec3d5f607f1f3e4d467633d1", "submitter": { "id": 3153, "url": "http://patchwork.dpdk.org/api/people/3153/?format=api", "name": "Mykola Kostenok", "email": "mko-plv@napatech.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230901121824.3250409-1-mko-plv@napatech.com/mbox/", "series": [ { "id": 29404, "url": "http://patchwork.dpdk.org/api/series/29404/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29404", "date": "2023-09-01T12:18:20", "name": "[v13,1/8] net/ntnic: initial commit which adds register defines", "version": 13, "mbox": "http://patchwork.dpdk.org/series/29404/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131094/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/131094/checks/", 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b=ei1pfug1XfE0m7YikCuL6aXg655pOWmtdEPCJ77vb90TosfXRJCl+OWXL0ZfkaFKwrHFVurlToxGjebS7JY2D/njWUU2y+pTLtrjCb0B7M+FcLWDQsWdUPKi0EBCVStuZHZiZPk5vf/XfoQdXmat2FMRYEs+vKA8UzzNHTEYt9w=", "X-MS-Exchange-Authentication-Results": "spf=fail (sender IP is 178.72.21.4)\n smtp.mailfrom=napatech.com; dkim=none (message not signed)\n header.d=none;dmarc=fail action=none header.from=napatech.com;", "Received-SPF": "Fail (protection.outlook.com: domain of napatech.com does not\n designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com;\n client-ip=178.72.21.4; helo=k8s-node.default.svc.cluster.local;", "From": "Mykola Kostenok <mko-plv@napatech.com>", "To": "dev@dpdk.org", "Cc": "mko-plv@napatech.com, thomas@monjalon.net, ckm@napatech.com,\n andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com", "Subject": "[PATCH v13 1/8] net/ntnic: initial commit which adds register defines", "Date": "Fri, 1 Sep 2023 14:18:17 +0200", "Message-Id": "<20230901121824.3250409-1-mko-plv@napatech.com>", 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cloudscan14-41.eu-central-1a.ess.aws.cudaops.com]\n Rule breakdown below\n pts rule name description\n ---- ---------------------- --------------------------------\n 0.00 LARGE_BODY_SHORTCUT META: ", "X-BESS-Outbound-Spam-Status": "SCORE=0.00 using account:ESS113687 scores of\n KILL_LEVEL=7.0 tests=LARGE_BODY_SHORTCUT", "X-BESS-BRTS-Status": "1", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Christian Koue Muf <ckm@napatech.com>\n\nThe NTNIC PMD does not rely on a kernel space Napatech driver,\nthus all defines related to the register layout is part of the PMD\ncode, which will be added in later commits.\n\nSigned-off-by: Christian Koue Muf <ckm@napatech.com>\nReviewed-by: Mykola Kostenok <mko-plv@napatech.com>\n---\nv3:\n* Fixed not needed cflags as suggested in comments.\nv5:\n* Disable build for unsupported platforms.\nv7:\n* Update unsupported platforms.\nv10:\n* Update FPGA register defines.\nv13:\n* Fix typo spelling warnings\n---\n drivers/net/meson.build | 1 +\n drivers/net/ntnic/include/fpga_model.h | 99 +\n drivers/net/ntnic/meson.build | 30 +\n drivers/net/ntnic/nthw/nthw_register.h | 19 +\n .../supported/nthw_fpga_9563_055_024_0000.c | 4181 ++++++++++\n .../nthw/supported/nthw_fpga_instances.h | 14 +\n .../nthw/supported/nthw_fpga_modules_defs.h | 166 +\n .../supported/nthw_fpga_parameters_defs.h | 209 +\n .../nthw/supported/nthw_fpga_registers_defs.h | 7211 +++++++++++++++++\n 9 files changed, 11930 insertions(+)\n create mode 100644 drivers/net/ntnic/include/fpga_model.h\n create mode 100644 drivers/net/ntnic/meson.build\n create mode 100644 drivers/net/ntnic/nthw/nthw_register.h\n create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_024_0000.c\n create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h\n create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_modules_defs.h\n create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_parameters_defs.h\n create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_registers_defs.h", "diff": "diff --git a/drivers/net/meson.build b/drivers/net/meson.build\nindex bd38b533c5..fb6d34b782 100644\n--- a/drivers/net/meson.build\n+++ b/drivers/net/meson.build\n@@ -45,6 +45,7 @@ drivers = [\n 'nfb',\n 'nfp',\n 'ngbe',\n+ 'ntnic',\n 'null',\n 'octeontx',\n 'octeon_ep',\ndiff --git a/drivers/net/ntnic/include/fpga_model.h b/drivers/net/ntnic/include/fpga_model.h\nnew file mode 100644\nindex 0000000000..89f1ae9736\n--- /dev/null\n+++ b/drivers/net/ntnic/include/fpga_model.h\n@@ -0,0 +1,99 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Napatech A/S\n+ */\n+\n+#ifndef FPGA_MODEL_H_\n+#define FPGA_MODEL_H_\n+\n+#include <unistd.h>\n+#include <stdint.h>\n+#include <inttypes.h>\n+\n+enum nt_fpga_bus_type {\n+\tBUS_TYPE_UNKNOWN =\n+\t\t0, /* Unknown/uninitialized - keep this as the first enum element */\n+\tBUS_TYPE_BAR,\n+\tBUS_TYPE_PCI,\n+\tBUS_TYPE_CCIP,\n+\tBUS_TYPE_RAB0,\n+\tBUS_TYPE_RAB1,\n+\tBUS_TYPE_RAB2,\n+\tBUS_TYPE_NMB,\n+\tBUS_TYPE_NDM,\n+\tBUS_TYPE_SPI0,\n+\tBUS_TYPE_SPI = BUS_TYPE_SPI0,\n+};\n+\n+typedef enum nt_fpga_bus_type nt_fpga_bus_type_t;\n+\n+enum nt_fpga_register_type {\n+\tREGISTER_TYPE_UNKNOWN =\n+\t\t0, /* Unknown/uninitialized - keep this as the first enum element */\n+\tREGISTER_TYPE_RW,\n+\tREGISTER_TYPE_RO,\n+\tREGISTER_TYPE_WO,\n+\tREGISTER_TYPE_RC1,\n+\tREGISTER_TYPE_MIXED,\n+};\n+\n+typedef enum nt_fpga_register_type nt_fpga_register_type_t;\n+\n+struct nt_fpga_field_init {\n+\tint id;\n+\tuint16_t bw;\n+\tuint16_t low;\n+\tuint64_t reset_val;\n+};\n+\n+typedef struct nt_fpga_field_init nt_fpga_field_init_t;\n+\n+struct nt_fpga_register_init {\n+\tint id;\n+\tuint32_t addr_rel;\n+\tuint16_t bw;\n+\tnt_fpga_register_type_t type;\n+\tuint64_t reset_val;\n+\tint nb_fields;\n+\tstruct nt_fpga_field_init *fields;\n+};\n+\n+typedef struct nt_fpga_register_init nt_fpga_register_init_t;\n+\n+struct nt_fpga_module_init {\n+\tint id;\n+\tint instance;\n+\tint def_id;\n+\tint major_version;\n+\tint minor_version;\n+\tnt_fpga_bus_type_t bus_id;\n+\tuint32_t addr_base;\n+\tint nb_registers;\n+\tstruct nt_fpga_register_init *registers;\n+};\n+\n+typedef struct nt_fpga_module_init nt_fpga_module_init_t;\n+\n+struct nt_fpga_prod_param {\n+\tconst int param_id;\n+\tconst int param_value;\n+};\n+\n+typedef struct nt_fpga_prod_param nt_fpga_prod_param_t;\n+\n+struct nt_fpga_prod_init {\n+\tint fpga_item_id;\n+\tint fpga_product_id;\n+\tint fpga_version;\n+\tint fpga_revision;\n+\tint fpga_patch_no;\n+\tint fpga_build_no;\n+\tuint32_t fpga_build_time;\n+\tint nb_prod_params;\n+\tstruct nt_fpga_prod_param *product_params;\n+\tint nb_modules;\n+\tstruct nt_fpga_module_init *modules;\n+};\n+\n+typedef struct nt_fpga_prod_init nt_fpga_prod_init_t;\n+\n+#endif /* FPGA_MODEL_H_ */\ndiff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build\nnew file mode 100644\nindex 0000000000..1194ce6aea\n--- /dev/null\n+++ b/drivers/net/ntnic/meson.build\n@@ -0,0 +1,30 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2020-2023 Napatech A/S\n+\n+if not is_linux or not dpdk_conf.has('RTE_ARCH_X86_64')\n+ build = false\n+ reason = 'only supported on x86_64 Linux'\n+ subdir_done()\n+endif\n+\n+# includes\n+includes = [\n+ include_directories('.'),\n+ include_directories('include'),\n+ include_directories('nthw'),\n+ include_directories('nthw/supported'),\n+]\n+\n+# all sources\n+sources = files(\n+ 'nthw/supported/nthw_fpga_9563_055_024_0000.c',\n+)\n+\n+if is_variable('default_cflags')\n+ cflags += default_cflags\n+else\n+ cflags += machine_args\n+ cflags += ['-DALLOW_INTERNAL_API']\n+endif\n+\n+# END\ndiff --git a/drivers/net/ntnic/nthw/nthw_register.h b/drivers/net/ntnic/nthw/nthw_register.h\nnew file mode 100644\nindex 0000000000..5cdbd9fc5d\n--- /dev/null\n+++ b/drivers/net/ntnic/nthw/nthw_register.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Napatech A/S\n+ */\n+\n+#ifndef NTHW_REGISTER_H_\n+#define NTHW_REGISTER_H_\n+\n+#include <unistd.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <inttypes.h>\n+\n+#include \"fpga_model.h\"\n+\n+#include \"nthw_fpga_modules_defs.h\"\n+#include \"nthw_fpga_parameters_defs.h\"\n+#include \"nthw_fpga_registers_defs.h\"\n+\n+#endif /* NTHW_REGISTER_H_ */\ndiff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_024_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_024_0000.c\nnew file mode 100644\nindex 0000000000..87b921da73\n--- /dev/null\n+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_024_0000.c\n@@ -0,0 +1,4181 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Napatech A/S\n+ */\n+\n+#include \"nthw_register.h\"\n+\n+static nt_fpga_field_init_t cat_cct_ctrl_fields[] = {\n+\t{ CAT_CCT_CTRL_ADR, 8, 0, 0x0000 },\n+\t{ CAT_CCT_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cct_data_fields[] = {\n+\t{ CAT_CCT_DATA_COLOR, 32, 0, 0x0000 },\n+\t{ CAT_CCT_DATA_KM, 4, 32, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cfn_ctrl_fields[] = {\n+\t{ CAT_CFN_CTRL_ADR, 6, 0, 0x0000 },\n+\t{ CAT_CFN_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cfn_data_fields[] = {\n+\t{ CAT_CFN_DATA_ENABLE, 1, 0, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_CV, 2, 99, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_FCS, 2, 101, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_INV, 1, 98, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_L3_CS, 2, 105, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_L4_CS, 2, 107, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_TNL_L3_CS, 2, 109, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_TNL_L4_CS, 2, 111, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_TNL_TTL_EXP, 2, 115, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_TRUNC, 2, 103, 0x0000 },\n+\t{ CAT_CFN_DATA_ERR_TTL_EXP, 2, 113, 0x0000 },\n+\t{ CAT_CFN_DATA_INV, 1, 1, 0x0000 },\n+\t{ CAT_CFN_DATA_KM0_OR, 3, 173, 0x0000 },\n+\t{ CAT_CFN_DATA_KM1_OR, 3, 176, 0x0000 },\n+\t{ CAT_CFN_DATA_LC, 8, 164, 0x0000 },\n+\t{ CAT_CFN_DATA_LC_INV, 1, 172, 0x0000 },\n+\t{ CAT_CFN_DATA_MAC_PORT, 2, 117, 0x0000 },\n+\t{ CAT_CFN_DATA_PM_AND_INV, 1, 161, 0x0000 },\n+\t{ CAT_CFN_DATA_PM_CMB, 4, 157, 0x0000 },\n+\t{ CAT_CFN_DATA_PM_CMP, 32, 119, 0x0000 },\n+\t{ CAT_CFN_DATA_PM_DCT, 2, 151, 0x0000 },\n+\t{ CAT_CFN_DATA_PM_EXT_INV, 4, 153, 0x0000 },\n+\t{ CAT_CFN_DATA_PM_INV, 1, 163, 0x0000 },\n+\t{ CAT_CFN_DATA_PM_OR_INV, 1, 162, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_CFP, 2, 5, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_FRAG, 4, 36, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_INV, 1, 2, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_IP_PROT, 8, 40, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_ISL, 2, 3, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_L2, 7, 12, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_L3, 3, 33, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_L4, 5, 48, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_MAC, 5, 7, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_MPLS, 8, 25, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_TNL_FRAG, 4, 81, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_TNL_IP_PROT, 8, 85, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_TNL_L2, 2, 64, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_TNL_L3, 3, 78, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_TNL_L4, 5, 93, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_TNL_MPLS, 8, 70, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_TNL_VLAN, 4, 66, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_TUNNEL, 11, 53, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_VLAN, 4, 21, 0x0000 },\n+\t{ CAT_CFN_DATA_PTC_VNTAG, 2, 19, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cot_ctrl_fields[] = {\n+\t{ CAT_COT_CTRL_ADR, 6, 0, 0x0000 },\n+\t{ CAT_COT_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cot_data_fields[] = {\n+\t{ CAT_COT_DATA_COLOR, 32, 0, 0x0000 },\n+\t{ CAT_COT_DATA_KM, 4, 32, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cte_ctrl_fields[] = {\n+\t{ CAT_CTE_CTRL_ADR, 6, 0, 0x0000 },\n+\t{ CAT_CTE_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cte_data_fields[] = {\n+\t{ CAT_CTE_DATA_COL_ENABLE, 1, 0, 0x0000 },\n+\t{ CAT_CTE_DATA_COR_ENABLE, 1, 1, 0x0000 },\n+\t{ CAT_CTE_DATA_EPP_ENABLE, 1, 9, 0x0000 },\n+\t{ CAT_CTE_DATA_HSH_ENABLE, 1, 2, 0x0000 },\n+\t{ CAT_CTE_DATA_HST_ENABLE, 1, 8, 0x0000 },\n+\t{ CAT_CTE_DATA_IPF_ENABLE, 1, 4, 0x0000 },\n+\t{ CAT_CTE_DATA_MSK_ENABLE, 1, 7, 0x0000 },\n+\t{ CAT_CTE_DATA_PDB_ENABLE, 1, 6, 0x0000 },\n+\t{ CAT_CTE_DATA_QSL_ENABLE, 1, 3, 0x0000 },\n+\t{ CAT_CTE_DATA_SLC_ENABLE, 1, 5, 0x0000 },\n+\t{ CAT_CTE_DATA_TPE_ENABLE, 1, 10, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cts_ctrl_fields[] = {\n+\t{ CAT_CTS_CTRL_ADR, 9, 0, 0x0000 },\n+\t{ CAT_CTS_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_cts_data_fields[] = {\n+\t{ CAT_CTS_DATA_CAT_A, 6, 0, 0x0000 },\n+\t{ CAT_CTS_DATA_CAT_B, 6, 6, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_dct_ctrl_fields[] = {\n+\t{ CAT_DCT_CTRL_ADR, 13, 0, 0x0000 },\n+\t{ CAT_DCT_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_dct_data_fields[] = {\n+\t{ CAT_DCT_DATA_RES, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_dct_sel_fields[] = {\n+\t{ CAT_DCT_SEL_LU, 2, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_exo_ctrl_fields[] = {\n+\t{ CAT_EXO_CTRL_ADR, 2, 0, 0x0000 },\n+\t{ CAT_EXO_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_exo_data_fields[] = {\n+\t{ CAT_EXO_DATA_DYN, 5, 0, 0x0000 },\n+\t{ CAT_EXO_DATA_OFS, 11, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_fte0_ctrl_fields[] = {\n+\t{ CAT_FTE0_CTRL_ADR, 9, 0, 0x0000 },\n+\t{ CAT_FTE0_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_fte0_data_fields[] = {\n+\t{ CAT_FTE0_DATA_ENABLE, 8, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_fte1_ctrl_fields[] = {\n+\t{ CAT_FTE1_CTRL_ADR, 9, 0, 0x0000 },\n+\t{ CAT_FTE1_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_fte1_data_fields[] = {\n+\t{ CAT_FTE1_DATA_ENABLE, 8, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_join_fields[] = {\n+\t{ CAT_JOIN_J1, 2, 0, 0x0000 },\n+\t{ CAT_JOIN_J2, 1, 8, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kcc_ctrl_fields[] = {\n+\t{ CAT_KCC_CTRL_ADR, 11, 0, 0x0000 },\n+\t{ CAT_KCC_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kcc_data_fields[] = {\n+\t{ CAT_KCC_DATA_CATEGORY, 8, 64, 0x0000 },\n+\t{ CAT_KCC_DATA_ID, 12, 72, 0x0000 },\n+\t{ CAT_KCC_DATA_KEY, 64, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kce0_ctrl_fields[] = {\n+\t{ CAT_KCE0_CTRL_ADR, 3, 0, 0x0000 },\n+\t{ CAT_KCE0_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kce0_data_fields[] = {\n+\t{ CAT_KCE0_DATA_ENABLE, 8, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kce1_ctrl_fields[] = {\n+\t{ CAT_KCE1_CTRL_ADR, 3, 0, 0x0000 },\n+\t{ CAT_KCE1_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kce1_data_fields[] = {\n+\t{ CAT_KCE1_DATA_ENABLE, 8, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kcs0_ctrl_fields[] = {\n+\t{ CAT_KCS0_CTRL_ADR, 6, 0, 0x0000 },\n+\t{ CAT_KCS0_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kcs0_data_fields[] = {\n+\t{ CAT_KCS0_DATA_CATEGORY, 6, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kcs1_ctrl_fields[] = {\n+\t{ CAT_KCS1_CTRL_ADR, 6, 0, 0x0000 },\n+\t{ CAT_KCS1_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_kcs1_data_fields[] = {\n+\t{ CAT_KCS1_DATA_CATEGORY, 6, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_len_ctrl_fields[] = {\n+\t{ CAT_LEN_CTRL_ADR, 3, 0, 0x0000 },\n+\t{ CAT_LEN_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_len_data_fields[] = {\n+\t{ CAT_LEN_DATA_DYN1, 5, 28, 0x0000 },\n+\t{ CAT_LEN_DATA_DYN2, 5, 33, 0x0000 },\n+\t{ CAT_LEN_DATA_INV, 1, 38, 0x0000 },\n+\t{ CAT_LEN_DATA_LOWER, 14, 0, 0x0000 },\n+\t{ CAT_LEN_DATA_UPPER, 14, 14, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_rck_ctrl_fields[] = {\n+\t{ CAT_RCK_CTRL_ADR, 8, 0, 0x0000 },\n+\t{ CAT_RCK_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cat_rck_data_fields[] = {\n+\t{ CAT_RCK_DATA_CM0U, 1, 1, 0x0000 },\n+\t{ CAT_RCK_DATA_CM1U, 1, 5, 0x0000 },\n+\t{ CAT_RCK_DATA_CM2U, 1, 9, 0x0000 },\n+\t{ CAT_RCK_DATA_CM3U, 1, 13, 0x0000 },\n+\t{ CAT_RCK_DATA_CM4U, 1, 17, 0x0000 },\n+\t{ CAT_RCK_DATA_CM5U, 1, 21, 0x0000 },\n+\t{ CAT_RCK_DATA_CM6U, 1, 25, 0x0000 },\n+\t{ CAT_RCK_DATA_CM7U, 1, 29, 0x0000 },\n+\t{ CAT_RCK_DATA_CML0, 1, 0, 0x0000 },\n+\t{ CAT_RCK_DATA_CML1, 1, 4, 0x0000 },\n+\t{ CAT_RCK_DATA_CML2, 1, 8, 0x0000 },\n+\t{ CAT_RCK_DATA_CML3, 1, 12, 0x0000 },\n+\t{ CAT_RCK_DATA_CML4, 1, 16, 0x0000 },\n+\t{ CAT_RCK_DATA_CML5, 1, 20, 0x0000 },\n+\t{ CAT_RCK_DATA_CML6, 1, 24, 0x0000 },\n+\t{ CAT_RCK_DATA_CML7, 1, 28, 0x0000 },\n+\t{ CAT_RCK_DATA_SEL0, 1, 2, 0x0000 },\n+\t{ CAT_RCK_DATA_SEL1, 1, 6, 0x0000 },\n+\t{ CAT_RCK_DATA_SEL2, 1, 10, 0x0000 },\n+\t{ CAT_RCK_DATA_SEL3, 1, 14, 0x0000 },\n+\t{ CAT_RCK_DATA_SEL4, 1, 18, 0x0000 },\n+\t{ CAT_RCK_DATA_SEL5, 1, 22, 0x0000 },\n+\t{ CAT_RCK_DATA_SEL6, 1, 26, 0x0000 },\n+\t{ CAT_RCK_DATA_SEL7, 1, 30, 0x0000 },\n+\t{ CAT_RCK_DATA_SEU0, 1, 3, 0x0000 },\n+\t{ CAT_RCK_DATA_SEU1, 1, 7, 0x0000 },\n+\t{ CAT_RCK_DATA_SEU2, 1, 11, 0x0000 },\n+\t{ CAT_RCK_DATA_SEU3, 1, 15, 0x0000 },\n+\t{ CAT_RCK_DATA_SEU4, 1, 19, 0x0000 },\n+\t{ CAT_RCK_DATA_SEU5, 1, 23, 0x0000 },\n+\t{ CAT_RCK_DATA_SEU6, 1, 27, 0x0000 },\n+\t{ CAT_RCK_DATA_SEU7, 1, 31, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t cat_registers[] = {\n+\t{ CAT_CCT_CTRL, 30, 32, REGISTER_TYPE_WO, 0, 2, cat_cct_ctrl_fields },\n+\t{ CAT_CCT_DATA, 31, 36, REGISTER_TYPE_WO, 0, 2, cat_cct_data_fields },\n+\t{ CAT_CFN_CTRL, 10, 32, REGISTER_TYPE_WO, 0, 2, cat_cfn_ctrl_fields },\n+\t{ CAT_CFN_DATA, 11, 179, REGISTER_TYPE_WO, 0, 44, cat_cfn_data_fields },\n+\t{ CAT_COT_CTRL, 28, 32, REGISTER_TYPE_WO, 0, 2, cat_cot_ctrl_fields },\n+\t{ CAT_COT_DATA, 29, 36, REGISTER_TYPE_WO, 0, 2, cat_cot_data_fields },\n+\t{ CAT_CTE_CTRL, 24, 32, REGISTER_TYPE_WO, 0, 2, cat_cte_ctrl_fields },\n+\t{ CAT_CTE_DATA, 25, 11, REGISTER_TYPE_WO, 0, 11, cat_cte_data_fields },\n+\t{ CAT_CTS_CTRL, 26, 32, REGISTER_TYPE_WO, 0, 2, cat_cts_ctrl_fields },\n+\t{ CAT_CTS_DATA, 27, 12, REGISTER_TYPE_WO, 0, 2, cat_cts_data_fields },\n+\t{ CAT_DCT_CTRL, 6, 32, REGISTER_TYPE_WO, 0, 2, cat_dct_ctrl_fields },\n+\t{ CAT_DCT_DATA, 7, 16, REGISTER_TYPE_WO, 0, 1, cat_dct_data_fields },\n+\t{ CAT_DCT_SEL, 4, 2, REGISTER_TYPE_WO, 0, 1, cat_dct_sel_fields },\n+\t{ CAT_EXO_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, cat_exo_ctrl_fields },\n+\t{ CAT_EXO_DATA, 1, 27, REGISTER_TYPE_WO, 0, 2, cat_exo_data_fields },\n+\t{ CAT_FTE0_CTRL, 16, 32, REGISTER_TYPE_WO, 0, 2, cat_fte0_ctrl_fields },\n+\t{ CAT_FTE0_DATA, 17, 8, REGISTER_TYPE_WO, 0, 1, cat_fte0_data_fields },\n+\t{ CAT_FTE1_CTRL, 22, 32, REGISTER_TYPE_WO, 0, 2, cat_fte1_ctrl_fields },\n+\t{ CAT_FTE1_DATA, 23, 8, REGISTER_TYPE_WO, 0, 1, cat_fte1_data_fields },\n+\t{ CAT_JOIN, 5, 9, REGISTER_TYPE_WO, 0, 2, cat_join_fields },\n+\t{ CAT_KCC_CTRL, 32, 32, REGISTER_TYPE_WO, 0, 2, cat_kcc_ctrl_fields },\n+\t{ CAT_KCC_DATA, 33, 84, REGISTER_TYPE_WO, 0, 3, cat_kcc_data_fields },\n+\t{ CAT_KCE0_CTRL, 12, 32, REGISTER_TYPE_WO, 0, 2, cat_kce0_ctrl_fields },\n+\t{ CAT_KCE0_DATA, 13, 8, REGISTER_TYPE_WO, 0, 1, cat_kce0_data_fields },\n+\t{ CAT_KCE1_CTRL, 18, 32, REGISTER_TYPE_WO, 0, 2, cat_kce1_ctrl_fields },\n+\t{ CAT_KCE1_DATA, 19, 8, REGISTER_TYPE_WO, 0, 1, cat_kce1_data_fields },\n+\t{ CAT_KCS0_CTRL, 14, 32, REGISTER_TYPE_WO, 0, 2, cat_kcs0_ctrl_fields },\n+\t{ CAT_KCS0_DATA, 15, 6, REGISTER_TYPE_WO, 0, 1, cat_kcs0_data_fields },\n+\t{ CAT_KCS1_CTRL, 20, 32, REGISTER_TYPE_WO, 0, 2, cat_kcs1_ctrl_fields },\n+\t{ CAT_KCS1_DATA, 21, 6, REGISTER_TYPE_WO, 0, 1, cat_kcs1_data_fields },\n+\t{ CAT_LEN_CTRL, 8, 32, REGISTER_TYPE_WO, 0, 2, cat_len_ctrl_fields },\n+\t{ CAT_LEN_DATA, 9, 39, REGISTER_TYPE_WO, 0, 5, cat_len_data_fields },\n+\t{ CAT_RCK_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2, cat_rck_ctrl_fields },\n+\t{ CAT_RCK_DATA, 3, 32, REGISTER_TYPE_WO, 0, 32, cat_rck_data_fields },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer0_ctrl_fields[] = {\n+\t{ CPY_WRITER0_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER0_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer0_data_fields[] = {\n+\t{ CPY_WRITER0_DATA_DYN, 5, 17, 0x0000 },\n+\t{ CPY_WRITER0_DATA_LEN, 4, 22, 0x0000 },\n+\t{ CPY_WRITER0_DATA_MASK_POINTER, 4, 26, 0x0000 },\n+\t{ CPY_WRITER0_DATA_OFS, 14, 3, 0x0000 },\n+\t{ CPY_WRITER0_DATA_READER_SELECT, 3, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer0_mask_ctrl_fields[] = {\n+\t{ CPY_WRITER0_MASK_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER0_MASK_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer0_mask_data_fields[] = {\n+\t{ CPY_WRITER0_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer1_ctrl_fields[] = {\n+\t{ CPY_WRITER1_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER1_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer1_data_fields[] = {\n+\t{ CPY_WRITER1_DATA_DYN, 5, 17, 0x0000 },\n+\t{ CPY_WRITER1_DATA_LEN, 4, 22, 0x0000 },\n+\t{ CPY_WRITER1_DATA_MASK_POINTER, 4, 26, 0x0000 },\n+\t{ CPY_WRITER1_DATA_OFS, 14, 3, 0x0000 },\n+\t{ CPY_WRITER1_DATA_READER_SELECT, 3, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer1_mask_ctrl_fields[] = {\n+\t{ CPY_WRITER1_MASK_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER1_MASK_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer1_mask_data_fields[] = {\n+\t{ CPY_WRITER1_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer2_ctrl_fields[] = {\n+\t{ CPY_WRITER2_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER2_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer2_data_fields[] = {\n+\t{ CPY_WRITER2_DATA_DYN, 5, 17, 0x0000 },\n+\t{ CPY_WRITER2_DATA_LEN, 4, 22, 0x0000 },\n+\t{ CPY_WRITER2_DATA_MASK_POINTER, 4, 26, 0x0000 },\n+\t{ CPY_WRITER2_DATA_OFS, 14, 3, 0x0000 },\n+\t{ CPY_WRITER2_DATA_READER_SELECT, 3, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer2_mask_ctrl_fields[] = {\n+\t{ CPY_WRITER2_MASK_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER2_MASK_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer2_mask_data_fields[] = {\n+\t{ CPY_WRITER2_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer3_ctrl_fields[] = {\n+\t{ CPY_WRITER3_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER3_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer3_data_fields[] = {\n+\t{ CPY_WRITER3_DATA_DYN, 5, 17, 0x0000 },\n+\t{ CPY_WRITER3_DATA_LEN, 4, 22, 0x0000 },\n+\t{ CPY_WRITER3_DATA_MASK_POINTER, 4, 26, 0x0000 },\n+\t{ CPY_WRITER3_DATA_OFS, 14, 3, 0x0000 },\n+\t{ CPY_WRITER3_DATA_READER_SELECT, 3, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer3_mask_ctrl_fields[] = {\n+\t{ CPY_WRITER3_MASK_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER3_MASK_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer3_mask_data_fields[] = {\n+\t{ CPY_WRITER3_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer4_ctrl_fields[] = {\n+\t{ CPY_WRITER4_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER4_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer4_data_fields[] = {\n+\t{ CPY_WRITER4_DATA_DYN, 5, 17, 0x0000 },\n+\t{ CPY_WRITER4_DATA_LEN, 4, 22, 0x0000 },\n+\t{ CPY_WRITER4_DATA_MASK_POINTER, 4, 26, 0x0000 },\n+\t{ CPY_WRITER4_DATA_OFS, 14, 3, 0x0000 },\n+\t{ CPY_WRITER4_DATA_READER_SELECT, 3, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer4_mask_ctrl_fields[] = {\n+\t{ CPY_WRITER4_MASK_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CPY_WRITER4_MASK_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t cpy_writer4_mask_data_fields[] = {\n+\t{ CPY_WRITER4_MASK_DATA_BYTE_MASK, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t cpy_registers[] = {\n+\t{\tCPY_WRITER0_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer0_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER0_DATA, 1, 30, REGISTER_TYPE_WO, 0, 5,\n+\t\tcpy_writer0_data_fields\n+\t},\n+\t{\tCPY_WRITER0_MASK_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer0_mask_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER0_MASK_DATA, 3, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\tcpy_writer0_mask_data_fields\n+\t},\n+\t{\tCPY_WRITER1_CTRL, 4, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer1_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER1_DATA, 5, 30, REGISTER_TYPE_WO, 0, 5,\n+\t\tcpy_writer1_data_fields\n+\t},\n+\t{\tCPY_WRITER1_MASK_CTRL, 6, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer1_mask_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER1_MASK_DATA, 7, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\tcpy_writer1_mask_data_fields\n+\t},\n+\t{\tCPY_WRITER2_CTRL, 8, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer2_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER2_DATA, 9, 30, REGISTER_TYPE_WO, 0, 5,\n+\t\tcpy_writer2_data_fields\n+\t},\n+\t{\tCPY_WRITER2_MASK_CTRL, 10, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer2_mask_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER2_MASK_DATA, 11, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\tcpy_writer2_mask_data_fields\n+\t},\n+\t{\tCPY_WRITER3_CTRL, 12, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer3_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER3_DATA, 13, 30, REGISTER_TYPE_WO, 0, 5,\n+\t\tcpy_writer3_data_fields\n+\t},\n+\t{\tCPY_WRITER3_MASK_CTRL, 14, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer3_mask_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER3_MASK_DATA, 15, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\tcpy_writer3_mask_data_fields\n+\t},\n+\t{\tCPY_WRITER4_CTRL, 16, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer4_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER4_DATA, 17, 30, REGISTER_TYPE_WO, 0, 5,\n+\t\tcpy_writer4_data_fields\n+\t},\n+\t{\tCPY_WRITER4_MASK_CTRL, 18, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tcpy_writer4_mask_ctrl_fields\n+\t},\n+\t{\tCPY_WRITER4_MASK_DATA, 19, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\tcpy_writer4_mask_data_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t csu_rcp_ctrl_fields[] = {\n+\t{ CSU_RCP_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ CSU_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t csu_rcp_data_fields[] = {\n+\t{ CSU_RCP_DATA_IL3_CMD, 2, 5, 0x0000 },\n+\t{ CSU_RCP_DATA_IL4_CMD, 3, 7, 0x0000 },\n+\t{ CSU_RCP_DATA_OL3_CMD, 2, 0, 0x0000 },\n+\t{ CSU_RCP_DATA_OL4_CMD, 3, 2, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t csu_registers[] = {\n+\t{ CSU_RCP_CTRL, 1, 32, REGISTER_TYPE_WO, 0, 2, csu_rcp_ctrl_fields },\n+\t{ CSU_RCP_DATA, 2, 10, REGISTER_TYPE_WO, 0, 4, csu_rcp_data_fields },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_am_ctrl_fields[] = {\n+\t{ DBS_RX_AM_CTRL_ADR, 7, 0, 0x0000 },\n+\t{ DBS_RX_AM_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_am_data_fields[] = {\n+\t{ DBS_RX_AM_DATA_ENABLE, 1, 72, 0x0000 },\n+\t{ DBS_RX_AM_DATA_GPA, 64, 0, 0x0000 },\n+\t{ DBS_RX_AM_DATA_HID, 8, 64, 0x0000 },\n+\t{ DBS_RX_AM_DATA_INT, 1, 74, 0x0000 },\n+\t{ DBS_RX_AM_DATA_PCKED, 1, 73, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_control_fields[] = {\n+\t{ DBS_RX_CONTROL_AME, 1, 7, 0 }, { DBS_RX_CONTROL_AMS, 4, 8, 8 },\n+\t{ DBS_RX_CONTROL_LQ, 7, 0, 0 },\t { DBS_RX_CONTROL_QE, 1, 17, 0 },\n+\t{ DBS_RX_CONTROL_UWE, 1, 12, 0 }, { DBS_RX_CONTROL_UWS, 4, 13, 5 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_dr_ctrl_fields[] = {\n+\t{ DBS_RX_DR_CTRL_ADR, 7, 0, 0x0000 },\n+\t{ DBS_RX_DR_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_dr_data_fields[] = {\n+\t{ DBS_RX_DR_DATA_GPA, 64, 0, 0x0000 },\n+\t{ DBS_RX_DR_DATA_HDR, 1, 88, 0x0000 },\n+\t{ DBS_RX_DR_DATA_HID, 8, 64, 0x0000 },\n+\t{ DBS_RX_DR_DATA_PCKED, 1, 87, 0x0000 },\n+\t{ DBS_RX_DR_DATA_QS, 15, 72, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_idle_fields[] = {\n+\t{ DBS_RX_IDLE_BUSY, 1, 8, 0 },\n+\t{ DBS_RX_IDLE_IDLE, 1, 0, 0x0000 },\n+\t{ DBS_RX_IDLE_QUEUE, 7, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_init_fields[] = {\n+\t{ DBS_RX_INIT_BUSY, 1, 8, 0 },\n+\t{ DBS_RX_INIT_INIT, 1, 0, 0x0000 },\n+\t{ DBS_RX_INIT_QUEUE, 7, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_init_val_fields[] = {\n+\t{ DBS_RX_INIT_VAL_IDX, 16, 0, 0x0000 },\n+\t{ DBS_RX_INIT_VAL_PTR, 15, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_ptr_fields[] = {\n+\t{ DBS_RX_PTR_PTR, 16, 0, 0x0000 },\n+\t{ DBS_RX_PTR_QUEUE, 7, 16, 0x0000 },\n+\t{ DBS_RX_PTR_VALID, 1, 23, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_uw_ctrl_fields[] = {\n+\t{ DBS_RX_UW_CTRL_ADR, 7, 0, 0x0000 },\n+\t{ DBS_RX_UW_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_rx_uw_data_fields[] = {\n+\t{ DBS_RX_UW_DATA_GPA, 64, 0, 0x0000 },\n+\t{ DBS_RX_UW_DATA_HID, 8, 64, 0x0000 },\n+\t{ DBS_RX_UW_DATA_INT, 1, 88, 0x0000 },\n+\t{ DBS_RX_UW_DATA_ISTK, 1, 92, 0x0000 },\n+\t{ DBS_RX_UW_DATA_PCKED, 1, 87, 0x0000 },\n+\t{ DBS_RX_UW_DATA_QS, 15, 72, 0x0000 },\n+\t{ DBS_RX_UW_DATA_VEC, 3, 89, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_am_ctrl_fields[] = {\n+\t{ DBS_TX_AM_CTRL_ADR, 7, 0, 0x0000 },\n+\t{ DBS_TX_AM_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_am_data_fields[] = {\n+\t{ DBS_TX_AM_DATA_ENABLE, 1, 72, 0x0000 },\n+\t{ DBS_TX_AM_DATA_GPA, 64, 0, 0x0000 },\n+\t{ DBS_TX_AM_DATA_HID, 8, 64, 0x0000 },\n+\t{ DBS_TX_AM_DATA_INT, 1, 74, 0x0000 },\n+\t{ DBS_TX_AM_DATA_PCKED, 1, 73, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_control_fields[] = {\n+\t{ DBS_TX_CONTROL_AME, 1, 7, 0 }, { DBS_TX_CONTROL_AMS, 4, 8, 5 },\n+\t{ DBS_TX_CONTROL_LQ, 7, 0, 0 },\t { DBS_TX_CONTROL_QE, 1, 17, 0 },\n+\t{ DBS_TX_CONTROL_UWE, 1, 12, 0 }, { DBS_TX_CONTROL_UWS, 4, 13, 8 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_dr_ctrl_fields[] = {\n+\t{ DBS_TX_DR_CTRL_ADR, 7, 0, 0x0000 },\n+\t{ DBS_TX_DR_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_dr_data_fields[] = {\n+\t{ DBS_TX_DR_DATA_GPA, 64, 0, 0x0000 },\n+\t{ DBS_TX_DR_DATA_HDR, 1, 88, 0x0000 },\n+\t{ DBS_TX_DR_DATA_HID, 8, 64, 0x0000 },\n+\t{ DBS_TX_DR_DATA_PCKED, 1, 87, 0x0000 },\n+\t{ DBS_TX_DR_DATA_PORT, 1, 89, 0x0000 },\n+\t{ DBS_TX_DR_DATA_QS, 15, 72, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_idle_fields[] = {\n+\t{ DBS_TX_IDLE_BUSY, 1, 8, 0 },\n+\t{ DBS_TX_IDLE_IDLE, 1, 0, 0x0000 },\n+\t{ DBS_TX_IDLE_QUEUE, 7, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_init_fields[] = {\n+\t{ DBS_TX_INIT_BUSY, 1, 8, 0 },\n+\t{ DBS_TX_INIT_INIT, 1, 0, 0x0000 },\n+\t{ DBS_TX_INIT_QUEUE, 7, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_init_val_fields[] = {\n+\t{ DBS_TX_INIT_VAL_IDX, 16, 0, 0x0000 },\n+\t{ DBS_TX_INIT_VAL_PTR, 15, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_ptr_fields[] = {\n+\t{ DBS_TX_PTR_PTR, 16, 0, 0x0000 },\n+\t{ DBS_TX_PTR_QUEUE, 7, 16, 0x0000 },\n+\t{ DBS_TX_PTR_VALID, 1, 23, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_qos_ctrl_fields[] = {\n+\t{ DBS_TX_QOS_CTRL_ADR, 1, 0, 0x0000 },\n+\t{ DBS_TX_QOS_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_qos_data_fields[] = {\n+\t{ DBS_TX_QOS_DATA_BS, 27, 17, 0x0000 },\n+\t{ DBS_TX_QOS_DATA_EN, 1, 0, 0x0000 },\n+\t{ DBS_TX_QOS_DATA_IR, 16, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_qos_rate_fields[] = {\n+\t{ DBS_TX_QOS_RATE_DIV, 19, 16, 2 },\n+\t{ DBS_TX_QOS_RATE_MUL, 16, 0, 1 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_qp_ctrl_fields[] = {\n+\t{ DBS_TX_QP_CTRL_ADR, 7, 0, 0x0000 },\n+\t{ DBS_TX_QP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_qp_data_fields[] = {\n+\t{ DBS_TX_QP_DATA_VPORT, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_uw_ctrl_fields[] = {\n+\t{ DBS_TX_UW_CTRL_ADR, 7, 0, 0x0000 },\n+\t{ DBS_TX_UW_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t dbs_tx_uw_data_fields[] = {\n+\t{ DBS_TX_UW_DATA_GPA, 64, 0, 0x0000 },\n+\t{ DBS_TX_UW_DATA_HID, 8, 64, 0x0000 },\n+\t{ DBS_TX_UW_DATA_INO, 1, 93, 0x0000 },\n+\t{ DBS_TX_UW_DATA_INT, 1, 88, 0x0000 },\n+\t{ DBS_TX_UW_DATA_ISTK, 1, 92, 0x0000 },\n+\t{ DBS_TX_UW_DATA_PCKED, 1, 87, 0x0000 },\n+\t{ DBS_TX_UW_DATA_QS, 15, 72, 0x0000 },\n+\t{ DBS_TX_UW_DATA_VEC, 3, 89, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t dbs_registers[] = {\n+\t{\tDBS_RX_AM_CTRL, 10, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_rx_am_ctrl_fields\n+\t},\n+\t{\tDBS_RX_AM_DATA, 11, 75, REGISTER_TYPE_WO, 0, 5,\n+\t\tdbs_rx_am_data_fields\n+\t},\n+\t{\tDBS_RX_CONTROL, 0, 18, REGISTER_TYPE_RW, 43008, 6,\n+\t\tdbs_rx_control_fields\n+\t},\n+\t{\tDBS_RX_DR_CTRL, 18, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_rx_dr_ctrl_fields\n+\t},\n+\t{\tDBS_RX_DR_DATA, 19, 89, REGISTER_TYPE_WO, 0, 5,\n+\t\tdbs_rx_dr_data_fields\n+\t},\n+\t{ DBS_RX_IDLE, 8, 9, REGISTER_TYPE_MIXED, 0, 3, dbs_rx_idle_fields },\n+\t{ DBS_RX_INIT, 2, 9, REGISTER_TYPE_MIXED, 0, 3, dbs_rx_init_fields },\n+\t{\tDBS_RX_INIT_VAL, 3, 31, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_rx_init_val_fields\n+\t},\n+\t{ DBS_RX_PTR, 4, 24, REGISTER_TYPE_MIXED, 0, 3, dbs_rx_ptr_fields },\n+\t{\tDBS_RX_UW_CTRL, 14, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_rx_uw_ctrl_fields\n+\t},\n+\t{\tDBS_RX_UW_DATA, 15, 93, REGISTER_TYPE_WO, 0, 7,\n+\t\tdbs_rx_uw_data_fields\n+\t},\n+\t{\tDBS_TX_AM_CTRL, 12, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_tx_am_ctrl_fields\n+\t},\n+\t{\tDBS_TX_AM_DATA, 13, 75, REGISTER_TYPE_WO, 0, 5,\n+\t\tdbs_tx_am_data_fields\n+\t},\n+\t{\tDBS_TX_CONTROL, 1, 18, REGISTER_TYPE_RW, 66816, 6,\n+\t\tdbs_tx_control_fields\n+\t},\n+\t{\tDBS_TX_DR_CTRL, 20, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_tx_dr_ctrl_fields\n+\t},\n+\t{\tDBS_TX_DR_DATA, 21, 90, REGISTER_TYPE_WO, 0, 6,\n+\t\tdbs_tx_dr_data_fields\n+\t},\n+\t{ DBS_TX_IDLE, 9, 9, REGISTER_TYPE_MIXED, 0, 3, dbs_tx_idle_fields },\n+\t{ DBS_TX_INIT, 5, 9, REGISTER_TYPE_MIXED, 0, 3, dbs_tx_init_fields },\n+\t{\tDBS_TX_INIT_VAL, 6, 31, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_tx_init_val_fields\n+\t},\n+\t{ DBS_TX_PTR, 7, 24, REGISTER_TYPE_MIXED, 0, 3, dbs_tx_ptr_fields },\n+\t{\tDBS_TX_QOS_CTRL, 24, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_tx_qos_ctrl_fields\n+\t},\n+\t{\tDBS_TX_QOS_DATA, 25, 44, REGISTER_TYPE_WO, 0, 3,\n+\t\tdbs_tx_qos_data_fields\n+\t},\n+\t{\tDBS_TX_QOS_RATE, 26, 35, REGISTER_TYPE_RW, 131073, 2,\n+\t\tdbs_tx_qos_rate_fields\n+\t},\n+\t{\tDBS_TX_QP_CTRL, 22, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_tx_qp_ctrl_fields\n+\t},\n+\t{\tDBS_TX_QP_DATA, 23, 1, REGISTER_TYPE_WO, 0, 1,\n+\t\tdbs_tx_qp_data_fields\n+\t},\n+\t{\tDBS_TX_UW_CTRL, 16, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\tdbs_tx_uw_ctrl_fields\n+\t},\n+\t{\tDBS_TX_UW_DATA, 17, 94, REGISTER_TYPE_WO, 0, 8,\n+\t\tdbs_tx_uw_data_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t flm_buf_ctrl_fields[] = {\n+\t{ FLM_BUF_CTRL_INF_AVAIL, 16, 16, 0x0000 },\n+\t{ FLM_BUF_CTRL_LRN_FREE, 16, 0, 0x0000 },\n+\t{ FLM_BUF_CTRL_STA_AVAIL, 16, 32, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_control_fields[] = {\n+\t{ FLM_CONTROL_CRCRD, 1, 12, 0x0000 },\n+\t{ FLM_CONTROL_CRCWR, 1, 11, 0x0000 },\n+\t{ FLM_CONTROL_EAB, 5, 18, 0 },\n+\t{ FLM_CONTROL_ENABLE, 1, 0, 0 },\n+\t{ FLM_CONTROL_INIT, 1, 1, 0x0000 },\n+\t{ FLM_CONTROL_LDS, 1, 2, 0x0000 },\n+\t{ FLM_CONTROL_LFS, 1, 3, 0x0000 },\n+\t{ FLM_CONTROL_LIS, 1, 4, 0x0000 },\n+\t{ FLM_CONTROL_PDS, 1, 9, 0x0000 },\n+\t{ FLM_CONTROL_PIS, 1, 10, 0x0000 },\n+\t{ FLM_CONTROL_RBL, 4, 13, 0 },\n+\t{ FLM_CONTROL_RDS, 1, 7, 0x0000 },\n+\t{ FLM_CONTROL_RIS, 1, 8, 0x0000 },\n+\t{ FLM_CONTROL_SPLIT_SDRAM_USAGE, 5, 23, 16 },\n+\t{ FLM_CONTROL_UDS, 1, 5, 0x0000 },\n+\t{ FLM_CONTROL_UIS, 1, 6, 0x0000 },\n+\t{ FLM_CONTROL_WPD, 1, 17, 0 },\n+};\n+\n+static nt_fpga_field_init_t flm_inf_data_fields[] = {\n+\t{ FLM_INF_DATA_BYTES, 64, 0, 0x0000 },\n+\t{ FLM_INF_DATA_CAUSE, 3, 264, 0x0000 },\n+\t{ FLM_INF_DATA_EOR, 1, 287, 0x0000 },\n+\t{ FLM_INF_DATA_ID, 72, 192, 0x0000 },\n+\t{ FLM_INF_DATA_PACKETS, 64, 64, 0x0000 },\n+\t{ FLM_INF_DATA_TS, 64, 128, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_load_aps_fields[] = {\n+\t{ FLM_LOAD_APS_APS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_load_bin_fields[] = {\n+\t{ FLM_LOAD_BIN_BIN, 30, 0, 8388607 },\n+};\n+\n+static nt_fpga_field_init_t flm_load_lps_fields[] = {\n+\t{ FLM_LOAD_LPS_LPS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_load_pps_fields[] = {\n+\t{ FLM_LOAD_PPS_PPS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_lrn_data_fields[] = {\n+\t{ FLM_LRN_DATA_ADJ, 32, 480, 0x0000 },\n+\t{ FLM_LRN_DATA_COLOR, 32, 448, 0x0000 },\n+\t{ FLM_LRN_DATA_DSCP, 6, 734, 0x0000 },\n+\t{ FLM_LRN_DATA_ENT, 1, 729, 0x0000 },\n+\t{ FLM_LRN_DATA_EOR, 1, 767, 0x0000 },\n+\t{ FLM_LRN_DATA_FILL, 12, 584, 0x0000 },\n+\t{ FLM_LRN_DATA_FT, 4, 596, 0x0000 },\n+\t{ FLM_LRN_DATA_FT_MBR, 4, 600, 0x0000 },\n+\t{ FLM_LRN_DATA_FT_MISS, 4, 604, 0x0000 },\n+\t{ FLM_LRN_DATA_ID, 72, 512, 0x0000 },\n+\t{ FLM_LRN_DATA_KID, 8, 328, 0x0000 },\n+\t{ FLM_LRN_DATA_MBR_ID1, 28, 608, 0x0000 },\n+\t{ FLM_LRN_DATA_MBR_ID2, 28, 636, 0x0000 },\n+\t{ FLM_LRN_DATA_MBR_ID3, 28, 664, 0x0000 },\n+\t{ FLM_LRN_DATA_MBR_ID4, 28, 692, 0x0000 },\n+\t{ FLM_LRN_DATA_NAT_EN, 1, 747, 0x0000 },\n+\t{ FLM_LRN_DATA_NAT_IP, 32, 336, 0x0000 },\n+\t{ FLM_LRN_DATA_NAT_PORT, 16, 400, 0x0000 },\n+\t{ FLM_LRN_DATA_OP, 4, 730, 0x0000 },\n+\t{ FLM_LRN_DATA_PRIO, 2, 727, 0x0000 },\n+\t{ FLM_LRN_DATA_PROT, 8, 320, 0x0000 },\n+\t{ FLM_LRN_DATA_QFI, 6, 740, 0x0000 },\n+\t{ FLM_LRN_DATA_QW0, 128, 192, 0x0000 },\n+\t{ FLM_LRN_DATA_QW4, 128, 64, 0x0000 },\n+\t{ FLM_LRN_DATA_RATE, 16, 416, 0x0000 },\n+\t{ FLM_LRN_DATA_RQI, 1, 746, 0x0000 },\n+\t{ FLM_LRN_DATA_SIZE, 16, 432, 0x0000 },\n+\t{ FLM_LRN_DATA_STAT_PROF, 4, 723, 0x0000 },\n+\t{ FLM_LRN_DATA_SW8, 32, 32, 0x0000 },\n+\t{ FLM_LRN_DATA_SW9, 32, 0, 0x0000 },\n+\t{ FLM_LRN_DATA_TEID, 32, 368, 0x0000 },\n+\t{ FLM_LRN_DATA_VOL_IDX, 3, 720, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_prio_fields[] = {\n+\t{ FLM_PRIO_FT0, 4, 4, 1 }, { FLM_PRIO_FT1, 4, 12, 1 },\n+\t{ FLM_PRIO_FT2, 4, 20, 1 }, { FLM_PRIO_FT3, 4, 28, 1 },\n+\t{ FLM_PRIO_LIMIT0, 4, 0, 0 }, { FLM_PRIO_LIMIT1, 4, 8, 0 },\n+\t{ FLM_PRIO_LIMIT2, 4, 16, 0 }, { FLM_PRIO_LIMIT3, 4, 24, 0 },\n+};\n+\n+static nt_fpga_field_init_t flm_pst_ctrl_fields[] = {\n+\t{ FLM_PST_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ FLM_PST_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_pst_data_fields[] = {\n+\t{ FLM_PST_DATA_BP, 5, 0, 0x0000 },\n+\t{ FLM_PST_DATA_PP, 5, 5, 0x0000 },\n+\t{ FLM_PST_DATA_TP, 5, 10, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_rcp_ctrl_fields[] = {\n+\t{ FLM_RCP_CTRL_ADR, 5, 0, 0x0000 },\n+\t{ FLM_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_rcp_data_fields[] = {\n+\t{ FLM_RCP_DATA_AUTO_IPV4_MASK, 1, 402, 0x0000 },\n+\t{ FLM_RCP_DATA_BYT_DYN, 5, 387, 0x0000 },\n+\t{ FLM_RCP_DATA_BYT_OFS, 8, 392, 0x0000 },\n+\t{ FLM_RCP_DATA_IPN, 1, 386, 0x0000 },\n+\t{ FLM_RCP_DATA_KID, 8, 377, 0x0000 },\n+\t{ FLM_RCP_DATA_LOOKUP, 1, 0, 0x0000 },\n+\t{ FLM_RCP_DATA_MASK, 320, 57, 0x0000 },\n+\t{ FLM_RCP_DATA_OPN, 1, 385, 0x0000 },\n+\t{ FLM_RCP_DATA_QW0_DYN, 5, 1, 0x0000 },\n+\t{ FLM_RCP_DATA_QW0_OFS, 8, 6, 0x0000 },\n+\t{ FLM_RCP_DATA_QW0_SEL, 2, 14, 0x0000 },\n+\t{ FLM_RCP_DATA_QW4_DYN, 5, 16, 0x0000 },\n+\t{ FLM_RCP_DATA_QW4_OFS, 8, 21, 0x0000 },\n+\t{ FLM_RCP_DATA_SW8_DYN, 5, 29, 0x0000 },\n+\t{ FLM_RCP_DATA_SW8_OFS, 8, 34, 0x0000 },\n+\t{ FLM_RCP_DATA_SW8_SEL, 2, 42, 0x0000 },\n+\t{ FLM_RCP_DATA_SW9_DYN, 5, 44, 0x0000 },\n+\t{ FLM_RCP_DATA_SW9_OFS, 8, 49, 0x0000 },\n+\t{ FLM_RCP_DATA_TXPLM, 2, 400, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_scrub_fields[] = {\n+\t{ FLM_SCRUB_I, 16, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t flm_status_fields[] = {\n+\t{ FLM_STATUS_CALIBDONE, 1, 0, 0x0000 },\n+\t{ FLM_STATUS_CRCERR, 1, 5, 0x0000 },\n+\t{ FLM_STATUS_CRITICAL, 1, 3, 0x0000 },\n+\t{ FLM_STATUS_EFT_BP, 1, 6, 0x0000 },\n+\t{ FLM_STATUS_IDLE, 1, 2, 0x0000 },\n+\t{ FLM_STATUS_INITDONE, 1, 1, 0x0000 },\n+\t{ FLM_STATUS_PANIC, 1, 4, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_aul_done_fields[] = {\n+\t{ FLM_STAT_AUL_DONE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_aul_fail_fields[] = {\n+\t{ FLM_STAT_AUL_FAIL_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_aul_ignore_fields[] = {\n+\t{ FLM_STAT_AUL_IGNORE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_csh_hit_fields[] = {\n+\t{ FLM_STAT_CSH_HIT_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_csh_miss_fields[] = {\n+\t{ FLM_STAT_CSH_MISS_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_csh_unh_fields[] = {\n+\t{ FLM_STAT_CSH_UNH_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_cuc_move_fields[] = {\n+\t{ FLM_STAT_CUC_MOVE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_cuc_start_fields[] = {\n+\t{ FLM_STAT_CUC_START_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_flows_fields[] = {\n+\t{ FLM_STAT_FLOWS_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_inf_done_fields[] = {\n+\t{ FLM_STAT_INF_DONE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_inf_skip_fields[] = {\n+\t{ FLM_STAT_INF_SKIP_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_lrn_done_fields[] = {\n+\t{ FLM_STAT_LRN_DONE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_lrn_fail_fields[] = {\n+\t{ FLM_STAT_LRN_FAIL_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_lrn_ignore_fields[] = {\n+\t{ FLM_STAT_LRN_IGNORE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_pck_dis_fields[] = {\n+\t{ FLM_STAT_PCK_DIS_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_pck_hit_fields[] = {\n+\t{ FLM_STAT_PCK_HIT_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_pck_miss_fields[] = {\n+\t{ FLM_STAT_PCK_MISS_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_pck_unh_fields[] = {\n+\t{ FLM_STAT_PCK_UNH_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_prb_done_fields[] = {\n+\t{ FLM_STAT_PRB_DONE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_prb_ignore_fields[] = {\n+\t{ FLM_STAT_PRB_IGNORE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_rel_done_fields[] = {\n+\t{ FLM_STAT_REL_DONE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_rel_ignore_fields[] = {\n+\t{ FLM_STAT_REL_IGNORE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_sta_done_fields[] = {\n+\t{ FLM_STAT_STA_DONE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_tul_done_fields[] = {\n+\t{ FLM_STAT_TUL_DONE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_unl_done_fields[] = {\n+\t{ FLM_STAT_UNL_DONE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_stat_unl_ignore_fields[] = {\n+\t{ FLM_STAT_UNL_IGNORE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_sta_data_fields[] = {\n+\t{ FLM_STA_DATA_EOR, 1, 95, 0x0000 },\n+\t{ FLM_STA_DATA_ID, 72, 0, 0x0000 },\n+\t{ FLM_STA_DATA_LDS, 1, 72, 0x0000 },\n+\t{ FLM_STA_DATA_LFS, 1, 73, 0x0000 },\n+\t{ FLM_STA_DATA_LIS, 1, 74, 0x0000 },\n+\t{ FLM_STA_DATA_PDS, 1, 79, 0x0000 },\n+\t{ FLM_STA_DATA_PIS, 1, 80, 0x0000 },\n+\t{ FLM_STA_DATA_RDS, 1, 77, 0x0000 },\n+\t{ FLM_STA_DATA_RIS, 1, 78, 0x0000 },\n+\t{ FLM_STA_DATA_UDS, 1, 75, 0x0000 },\n+\t{ FLM_STA_DATA_UIS, 1, 76, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t flm_timeout_fields[] = {\n+\t{ FLM_TIMEOUT_T, 32, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t flm_registers[] = {\n+\t{ FLM_BUF_CTRL, 14, 48, REGISTER_TYPE_RW, 0, 3, flm_buf_ctrl_fields },\n+\t{\tFLM_CONTROL, 0, 28, REGISTER_TYPE_MIXED, 134217728, 17,\n+\t\tflm_control_fields\n+\t},\n+\t{ FLM_INF_DATA, 16, 288, REGISTER_TYPE_RO, 0, 6, flm_inf_data_fields },\n+\t{ FLM_LOAD_APS, 7, 32, REGISTER_TYPE_RO, 0, 1, flm_load_aps_fields },\n+\t{\tFLM_LOAD_BIN, 4, 30, REGISTER_TYPE_WO, 8388607, 1,\n+\t\tflm_load_bin_fields\n+\t},\n+\t{ FLM_LOAD_LPS, 6, 32, REGISTER_TYPE_RO, 0, 1, flm_load_lps_fields },\n+\t{ FLM_LOAD_PPS, 5, 32, REGISTER_TYPE_RO, 0, 1, flm_load_pps_fields },\n+\t{ FLM_LRN_DATA, 15, 768, REGISTER_TYPE_WO, 0, 32, flm_lrn_data_fields },\n+\t{ FLM_PRIO, 8, 32, REGISTER_TYPE_WO, 269488144, 8, flm_prio_fields },\n+\t{ FLM_PST_CTRL, 10, 32, REGISTER_TYPE_WO, 0, 2, flm_pst_ctrl_fields },\n+\t{ FLM_PST_DATA, 11, 15, REGISTER_TYPE_WO, 0, 3, flm_pst_data_fields },\n+\t{ FLM_RCP_CTRL, 12, 32, REGISTER_TYPE_WO, 0, 2, flm_rcp_ctrl_fields },\n+\t{ FLM_RCP_DATA, 13, 403, REGISTER_TYPE_WO, 0, 19, flm_rcp_data_fields },\n+\t{ FLM_SCRUB, 3, 16, REGISTER_TYPE_WO, 0, 1, flm_scrub_fields },\n+\t{ FLM_STATUS, 1, 12, REGISTER_TYPE_MIXED, 0, 7, flm_status_fields },\n+\t{\tFLM_STAT_AUL_DONE, 41, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_aul_done_fields\n+\t},\n+\t{\tFLM_STAT_AUL_FAIL, 43, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_aul_fail_fields\n+\t},\n+\t{\tFLM_STAT_AUL_IGNORE, 42, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_aul_ignore_fields\n+\t},\n+\t{\tFLM_STAT_CSH_HIT, 52, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_csh_hit_fields\n+\t},\n+\t{\tFLM_STAT_CSH_MISS, 53, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_csh_miss_fields\n+\t},\n+\t{\tFLM_STAT_CSH_UNH, 54, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_csh_unh_fields\n+\t},\n+\t{\tFLM_STAT_CUC_MOVE, 57, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_cuc_move_fields\n+\t},\n+\t{\tFLM_STAT_CUC_START, 56, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_cuc_start_fields\n+\t},\n+\t{\tFLM_STAT_FLOWS, 18, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_flows_fields\n+\t},\n+\t{\tFLM_STAT_INF_DONE, 46, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_inf_done_fields\n+\t},\n+\t{\tFLM_STAT_INF_SKIP, 47, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_inf_skip_fields\n+\t},\n+\t{\tFLM_STAT_LRN_DONE, 32, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_lrn_done_fields\n+\t},\n+\t{\tFLM_STAT_LRN_FAIL, 34, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_lrn_fail_fields\n+\t},\n+\t{\tFLM_STAT_LRN_IGNORE, 33, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_lrn_ignore_fields\n+\t},\n+\t{\tFLM_STAT_PCK_DIS, 51, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_pck_dis_fields\n+\t},\n+\t{\tFLM_STAT_PCK_HIT, 48, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_pck_hit_fields\n+\t},\n+\t{\tFLM_STAT_PCK_MISS, 49, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_pck_miss_fields\n+\t},\n+\t{\tFLM_STAT_PCK_UNH, 50, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_pck_unh_fields\n+\t},\n+\t{\tFLM_STAT_PRB_DONE, 39, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_prb_done_fields\n+\t},\n+\t{\tFLM_STAT_PRB_IGNORE, 40, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_prb_ignore_fields\n+\t},\n+\t{\tFLM_STAT_REL_DONE, 37, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_rel_done_fields\n+\t},\n+\t{\tFLM_STAT_REL_IGNORE, 38, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_rel_ignore_fields\n+\t},\n+\t{\tFLM_STAT_STA_DONE, 45, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_sta_done_fields\n+\t},\n+\t{\tFLM_STAT_TUL_DONE, 44, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_tul_done_fields\n+\t},\n+\t{\tFLM_STAT_UNL_DONE, 35, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_unl_done_fields\n+\t},\n+\t{\tFLM_STAT_UNL_IGNORE, 36, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tflm_stat_unl_ignore_fields\n+\t},\n+\t{ FLM_STA_DATA, 17, 96, REGISTER_TYPE_RO, 0, 11, flm_sta_data_fields },\n+\t{ FLM_TIMEOUT, 2, 32, REGISTER_TYPE_WO, 0, 1, flm_timeout_fields },\n+};\n+\n+static nt_fpga_field_init_t gfg_burstsize0_fields[] = {\n+\t{ GFG_BURSTSIZE0_VAL, 24, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gfg_burstsize1_fields[] = {\n+\t{ GFG_BURSTSIZE1_VAL, 24, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gfg_ctrl0_fields[] = {\n+\t{ GFG_CTRL0_ENABLE, 1, 0, 0 },\n+\t{ GFG_CTRL0_MODE, 3, 1, 0 },\n+\t{ GFG_CTRL0_PRBS_EN, 1, 4, 0 },\n+\t{ GFG_CTRL0_SIZE, 14, 16, 64 },\n+};\n+\n+static nt_fpga_field_init_t gfg_ctrl1_fields[] = {\n+\t{ GFG_CTRL1_ENABLE, 1, 0, 0 },\n+\t{ GFG_CTRL1_MODE, 3, 1, 0 },\n+\t{ GFG_CTRL1_PRBS_EN, 1, 4, 0 },\n+\t{ GFG_CTRL1_SIZE, 14, 16, 64 },\n+};\n+\n+static nt_fpga_field_init_t gfg_run0_fields[] = {\n+\t{ GFG_RUN0_RUN, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gfg_run1_fields[] = {\n+\t{ GFG_RUN1_RUN, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gfg_sizemask0_fields[] = {\n+\t{ GFG_SIZEMASK0_VAL, 14, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gfg_sizemask1_fields[] = {\n+\t{ GFG_SIZEMASK1_VAL, 14, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gfg_streamid0_fields[] = {\n+\t{ GFG_STREAMID0_VAL, 8, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gfg_streamid1_fields[] = {\n+\t{ GFG_STREAMID1_VAL, 8, 0, 1 },\n+};\n+\n+static nt_fpga_register_init_t gfg_registers[] = {\n+\t{\tGFG_BURSTSIZE0, 3, 24, REGISTER_TYPE_WO, 0, 1,\n+\t\tgfg_burstsize0_fields\n+\t},\n+\t{\tGFG_BURSTSIZE1, 8, 24, REGISTER_TYPE_WO, 0, 1,\n+\t\tgfg_burstsize1_fields\n+\t},\n+\t{ GFG_CTRL0, 0, 30, REGISTER_TYPE_WO, 4194304, 4, gfg_ctrl0_fields },\n+\t{ GFG_CTRL1, 5, 30, REGISTER_TYPE_WO, 4194304, 4, gfg_ctrl1_fields },\n+\t{ GFG_RUN0, 1, 1, REGISTER_TYPE_WO, 0, 1, gfg_run0_fields },\n+\t{ GFG_RUN1, 6, 1, REGISTER_TYPE_WO, 0, 1, gfg_run1_fields },\n+\t{ GFG_SIZEMASK0, 4, 14, REGISTER_TYPE_WO, 0, 1, gfg_sizemask0_fields },\n+\t{ GFG_SIZEMASK1, 9, 14, REGISTER_TYPE_WO, 0, 1, gfg_sizemask1_fields },\n+\t{ GFG_STREAMID0, 2, 8, REGISTER_TYPE_WO, 0, 1, gfg_streamid0_fields },\n+\t{ GFG_STREAMID1, 7, 8, REGISTER_TYPE_WO, 1, 1, gfg_streamid1_fields },\n+};\n+\n+static nt_fpga_field_init_t gmf_ctrl_fields[] = {\n+\t{ GMF_CTRL_ENABLE, 1, 0, 0 },\n+\t{ GMF_CTRL_FCS_ALWAYS, 1, 1, 0 },\n+\t{ GMF_CTRL_IFG_AUTO_ADJUST_ENABLE, 1, 7, 0 },\n+\t{ GMF_CTRL_IFG_ENABLE, 1, 2, 0 },\n+\t{ GMF_CTRL_IFG_TX_NOW_ALWAYS, 1, 3, 0 },\n+\t{ GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE, 1, 5, 0 },\n+\t{ GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK, 1, 6, 0 },\n+\t{ GMF_CTRL_IFG_TX_ON_TS_ALWAYS, 1, 4, 0 },\n+\t{ GMF_CTRL_TS_INJECT_ALWAYS, 1, 8, 0 },\n+\t{ GMF_CTRL_TS_INJECT_DUAL_STEP, 1, 9, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_debug_lane_marker_fields[] = {\n+\t{ GMF_DEBUG_LANE_MARKER_COMPENSATION, 16, 0, 16384 },\n+};\n+\n+static nt_fpga_field_init_t gmf_ifg_max_adjust_slack_fields[] = {\n+\t{ GMF_IFG_MAX_ADJUST_SLACK_SLACK, 64, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_ifg_set_clock_delta_fields[] = {\n+\t{ GMF_IFG_SET_CLOCK_DELTA_DELTA, 64, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_ifg_set_clock_delta_adjust_fields[] = {\n+\t{ GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA, 64, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_ifg_tx_now_on_ts_fields[] = {\n+\t{ GMF_IFG_TX_NOW_ON_TS_TS, 64, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_speed_fields[] = {\n+\t{ GMF_SPEED_IFG_SPEED, 64, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_stat_data_buffer_fields[] = {\n+\t{ GMF_STAT_DATA_BUFFER_USED, 15, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t gmf_stat_max_delayed_pkt_fields[] = {\n+\t{ GMF_STAT_MAX_DELAYED_PKT_NS, 64, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_stat_next_pkt_fields[] = {\n+\t{ GMF_STAT_NEXT_PKT_NS, 64, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_stat_sticky_fields[] = {\n+\t{ GMF_STAT_STICKY_DATA_UNDERFLOWED, 1, 0, 0 },\n+\t{ GMF_STAT_STICKY_IFG_ADJUSTED, 1, 1, 0 },\n+};\n+\n+static nt_fpga_field_init_t gmf_ts_inject_fields[] = {\n+\t{ GMF_TS_INJECT_OFFSET, 14, 0, 0 },\n+\t{ GMF_TS_INJECT_POS, 2, 14, 0 },\n+};\n+\n+static nt_fpga_register_init_t gmf_registers[] = {\n+\t{ GMF_CTRL, 0, 10, REGISTER_TYPE_WO, 0, 10, gmf_ctrl_fields },\n+\t{\tGMF_DEBUG_LANE_MARKER, 7, 16, REGISTER_TYPE_WO, 16384, 1,\n+\t\tgmf_debug_lane_marker_fields\n+\t},\n+\t{\tGMF_IFG_MAX_ADJUST_SLACK, 4, 64, REGISTER_TYPE_WO, 0, 1,\n+\t\tgmf_ifg_max_adjust_slack_fields\n+\t},\n+\t{\tGMF_IFG_SET_CLOCK_DELTA, 2, 64, REGISTER_TYPE_WO, 0, 1,\n+\t\tgmf_ifg_set_clock_delta_fields\n+\t},\n+\t{\tGMF_IFG_SET_CLOCK_DELTA_ADJUST, 3, 64, REGISTER_TYPE_WO, 0, 1,\n+\t\tgmf_ifg_set_clock_delta_adjust_fields\n+\t},\n+\t{\tGMF_IFG_TX_NOW_ON_TS, 5, 64, REGISTER_TYPE_WO, 0, 1,\n+\t\tgmf_ifg_tx_now_on_ts_fields\n+\t},\n+\t{ GMF_SPEED, 1, 64, REGISTER_TYPE_WO, 0, 1, gmf_speed_fields },\n+\t{\tGMF_STAT_DATA_BUFFER, 9, 15, REGISTER_TYPE_RO, 0, 1,\n+\t\tgmf_stat_data_buffer_fields\n+\t},\n+\t{\tGMF_STAT_MAX_DELAYED_PKT, 11, 64, REGISTER_TYPE_RC1, 0, 1,\n+\t\tgmf_stat_max_delayed_pkt_fields\n+\t},\n+\t{\tGMF_STAT_NEXT_PKT, 10, 64, REGISTER_TYPE_RO, 0, 1,\n+\t\tgmf_stat_next_pkt_fields\n+\t},\n+\t{\tGMF_STAT_STICKY, 8, 2, REGISTER_TYPE_RC1, 0, 2,\n+\t\tgmf_stat_sticky_fields\n+\t},\n+\t{ GMF_TS_INJECT, 6, 16, REGISTER_TYPE_WO, 0, 2, gmf_ts_inject_fields },\n+};\n+\n+static nt_fpga_field_init_t gpio_phy_cfg_fields[] = {\n+\t{ GPIO_PHY_CFG_E_PORT0_RXLOS, 1, 8, 0 },\n+\t{ GPIO_PHY_CFG_E_PORT1_RXLOS, 1, 9, 0 },\n+\t{ GPIO_PHY_CFG_PORT0_INT_B, 1, 1, 1 },\n+\t{ GPIO_PHY_CFG_PORT0_LPMODE, 1, 0, 0 },\n+\t{ GPIO_PHY_CFG_PORT0_MODPRS_B, 1, 3, 1 },\n+\t{ GPIO_PHY_CFG_PORT0_RESET_B, 1, 2, 0 },\n+\t{ GPIO_PHY_CFG_PORT1_INT_B, 1, 5, 1 },\n+\t{ GPIO_PHY_CFG_PORT1_LPMODE, 1, 4, 0 },\n+\t{ GPIO_PHY_CFG_PORT1_MODPRS_B, 1, 7, 1 },\n+\t{ GPIO_PHY_CFG_PORT1_RESET_B, 1, 6, 0 },\n+};\n+\n+static nt_fpga_field_init_t gpio_phy_gpio_fields[] = {\n+\t{ GPIO_PHY_GPIO_E_PORT0_RXLOS, 1, 8, 0 },\n+\t{ GPIO_PHY_GPIO_E_PORT1_RXLOS, 1, 9, 0 },\n+\t{ GPIO_PHY_GPIO_PORT0_INT_B, 1, 1, 0x0000 },\n+\t{ GPIO_PHY_GPIO_PORT0_LPMODE, 1, 0, 1 },\n+\t{ GPIO_PHY_GPIO_PORT0_MODPRS_B, 1, 3, 0x0000 },\n+\t{ GPIO_PHY_GPIO_PORT0_RESET_B, 1, 2, 0 },\n+\t{ GPIO_PHY_GPIO_PORT1_INT_B, 1, 5, 0x0000 },\n+\t{ GPIO_PHY_GPIO_PORT1_LPMODE, 1, 4, 1 },\n+\t{ GPIO_PHY_GPIO_PORT1_MODPRS_B, 1, 7, 0x0000 },\n+\t{ GPIO_PHY_GPIO_PORT1_RESET_B, 1, 6, 0 },\n+};\n+\n+static nt_fpga_register_init_t gpio_phy_registers[] = {\n+\t{ GPIO_PHY_CFG, 0, 10, REGISTER_TYPE_RW, 170, 10, gpio_phy_cfg_fields },\n+\t{\tGPIO_PHY_GPIO, 1, 10, REGISTER_TYPE_RW, 17, 10,\n+\t\tgpio_phy_gpio_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t hfu_rcp_ctrl_fields[] = {\n+\t{ HFU_RCP_CTRL_ADR, 6, 0, 0x0000 },\n+\t{ HFU_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t hfu_rcp_data_fields[] = {\n+\t{ HFU_RCP_DATA_CSINF, 1, 111, 0x0000 },\n+\t{ HFU_RCP_DATA_IL3OFS, 8, 139, 0x0000 },\n+\t{ HFU_RCP_DATA_IL4OFS, 8, 147, 0x0000 },\n+\t{ HFU_RCP_DATA_L3FRAG, 2, 114, 0x0000 },\n+\t{ HFU_RCP_DATA_L3PRT, 2, 112, 0x0000 },\n+\t{ HFU_RCP_DATA_L4PRT, 3, 120, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_A_ADD_DYN, 5, 15, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_A_ADD_OFS, 8, 20, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_A_OL4LEN, 1, 1, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_A_POS_DYN, 5, 2, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_A_POS_OFS, 8, 7, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_A_SUB_DYN, 5, 28, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_A_WR, 1, 0, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_B_ADD_DYN, 5, 47, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_B_ADD_OFS, 8, 52, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_B_POS_DYN, 5, 34, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_B_POS_OFS, 8, 39, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_B_SUB_DYN, 5, 60, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_B_WR, 1, 33, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_C_ADD_DYN, 5, 79, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_C_ADD_OFS, 8, 84, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_C_POS_DYN, 5, 66, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_C_POS_OFS, 8, 71, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_C_SUB_DYN, 5, 92, 0x0000 },\n+\t{ HFU_RCP_DATA_LEN_C_WR, 1, 65, 0x0000 },\n+\t{ HFU_RCP_DATA_OL3OFS, 8, 123, 0x0000 },\n+\t{ HFU_RCP_DATA_OL4OFS, 8, 131, 0x0000 },\n+\t{ HFU_RCP_DATA_TTL_POS_DYN, 5, 98, 0x0000 },\n+\t{ HFU_RCP_DATA_TTL_POS_OFS, 8, 103, 0x0000 },\n+\t{ HFU_RCP_DATA_TTL_WR, 1, 97, 0x0000 },\n+\t{ HFU_RCP_DATA_TUNNEL, 4, 116, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t hfu_registers[] = {\n+\t{ HFU_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, hfu_rcp_ctrl_fields },\n+\t{ HFU_RCP_DATA, 1, 155, REGISTER_TYPE_WO, 0, 31, hfu_rcp_data_fields },\n+};\n+\n+static nt_fpga_field_init_t hif_build_time_fields[] = {\n+\t{ HIF_BUILD_TIME_TIME, 32, 0, 1693228548 },\n+};\n+\n+static nt_fpga_field_init_t hif_config_fields[] = {\n+\t{ HIF_CONFIG_EXT_TAG, 1, 6, 0x0000 },\n+\t{ HIF_CONFIG_MAX_READ, 3, 3, 0x0000 },\n+\t{ HIF_CONFIG_MAX_TLP, 3, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t hif_control_fields[] = {\n+\t{ HIF_CONTROL_BLESSED, 8, 4, 0 },\n+\t{ HIF_CONTROL_WRAW, 4, 0, 1 },\n+};\n+\n+static nt_fpga_field_init_t hif_prod_id_ex_fields[] = {\n+\t{ HIF_PROD_ID_EX_LAYOUT, 1, 31, 0 },\n+\t{ HIF_PROD_ID_EX_LAYOUT_VERSION, 8, 0, 1 },\n+\t{ HIF_PROD_ID_EX_RESERVED, 23, 8, 0 },\n+};\n+\n+static nt_fpga_field_init_t hif_prod_id_lsb_fields[] = {\n+\t{ HIF_PROD_ID_LSB_GROUP_ID, 16, 16, 9563 },\n+\t{ HIF_PROD_ID_LSB_REV_ID, 8, 0, 24 },\n+\t{ HIF_PROD_ID_LSB_VER_ID, 8, 8, 55 },\n+};\n+\n+static nt_fpga_field_init_t hif_prod_id_msb_fields[] = {\n+\t{ HIF_PROD_ID_MSB_BUILD_NO, 10, 12, 0 },\n+\t{ HIF_PROD_ID_MSB_TYPE_ID, 12, 0, 200 },\n+};\n+\n+static nt_fpga_field_init_t hif_sample_time_fields[] = {\n+\t{ HIF_SAMPLE_TIME_SAMPLE_TIME, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t hif_status_fields[] = {\n+\t{ HIF_STATUS_RD_ERR, 1, 9, 0 },\n+\t{ HIF_STATUS_TAGS_IN_USE, 8, 0, 0 },\n+\t{ HIF_STATUS_WR_ERR, 1, 8, 0 },\n+};\n+\n+static nt_fpga_field_init_t hif_stat_ctrl_fields[] = {\n+\t{ HIF_STAT_CTRL_STAT_ENA, 1, 1, 0 },\n+\t{ HIF_STAT_CTRL_STAT_REQ, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t hif_stat_refclk_fields[] = {\n+\t{ HIF_STAT_REFCLK_REFCLK250, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t hif_stat_rx_fields[] = {\n+\t{ HIF_STAT_RX_COUNTER, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t hif_stat_tx_fields[] = {\n+\t{ HIF_STAT_TX_COUNTER, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t hif_test0_fields[] = {\n+\t{ HIF_TEST0_DATA, 32, 0, 287454020 },\n+};\n+\n+static nt_fpga_field_init_t hif_test1_fields[] = {\n+\t{ HIF_TEST1_DATA, 32, 0, 2864434397 },\n+};\n+\n+static nt_fpga_field_init_t hif_uuid0_fields[] = {\n+\t{ HIF_UUID0_UUID0, 32, 0, 929302248 },\n+};\n+\n+static nt_fpga_field_init_t hif_uuid1_fields[] = {\n+\t{ HIF_UUID1_UUID1, 32, 0, 2904641880 },\n+};\n+\n+static nt_fpga_field_init_t hif_uuid2_fields[] = {\n+\t{ HIF_UUID2_UUID2, 32, 0, 55459253 },\n+};\n+\n+static nt_fpga_field_init_t hif_uuid3_fields[] = {\n+\t{ HIF_UUID3_UUID3, 32, 0, 4051580681 },\n+};\n+\n+static nt_fpga_register_init_t hif_registers[] = {\n+\t{\tHIF_BUILD_TIME, 16, 32, REGISTER_TYPE_RO, 1693228548, 1,\n+\t\thif_build_time_fields\n+\t},\n+\t{ HIF_CONFIG, 24, 7, REGISTER_TYPE_RW, 0, 3, hif_config_fields },\n+\t{ HIF_CONTROL, 40, 12, REGISTER_TYPE_RW, 1, 2, hif_control_fields },\n+\t{\tHIF_PROD_ID_EX, 112, 32, REGISTER_TYPE_RO, 1, 3,\n+\t\thif_prod_id_ex_fields\n+\t},\n+\t{\tHIF_PROD_ID_LSB, 0, 32, REGISTER_TYPE_RO, 626734872, 3,\n+\t\thif_prod_id_lsb_fields\n+\t},\n+\t{\tHIF_PROD_ID_MSB, 8, 22, REGISTER_TYPE_RO, 200, 2,\n+\t\thif_prod_id_msb_fields\n+\t},\n+\t{\tHIF_SAMPLE_TIME, 96, 1, REGISTER_TYPE_WO, 0, 1,\n+\t\thif_sample_time_fields\n+\t},\n+\t{ HIF_STATUS, 32, 10, REGISTER_TYPE_MIXED, 0, 3, hif_status_fields },\n+\t{ HIF_STAT_CTRL, 64, 2, REGISTER_TYPE_WO, 0, 2, hif_stat_ctrl_fields },\n+\t{\tHIF_STAT_REFCLK, 72, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\thif_stat_refclk_fields\n+\t},\n+\t{ HIF_STAT_RX, 88, 32, REGISTER_TYPE_RO, 0, 1, hif_stat_rx_fields },\n+\t{ HIF_STAT_TX, 80, 32, REGISTER_TYPE_RO, 0, 1, hif_stat_tx_fields },\n+\t{ HIF_TEST0, 48, 32, REGISTER_TYPE_RW, 287454020, 1, hif_test0_fields },\n+\t{\tHIF_TEST1, 56, 32, REGISTER_TYPE_RW, 2864434397, 1,\n+\t\thif_test1_fields\n+\t},\n+\t{\tHIF_UUID0, 128, 32, REGISTER_TYPE_RO, 929302248, 1,\n+\t\thif_uuid0_fields\n+\t},\n+\t{\tHIF_UUID1, 144, 32, REGISTER_TYPE_RO, 2904641880, 1,\n+\t\thif_uuid1_fields\n+\t},\n+\t{\tHIF_UUID2, 160, 32, REGISTER_TYPE_RO, 55459253, 1,\n+\t\thif_uuid2_fields\n+\t},\n+\t{\tHIF_UUID3, 176, 32, REGISTER_TYPE_RO, 4051580681, 1,\n+\t\thif_uuid3_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t hsh_rcp_ctrl_fields[] = {\n+\t{ HSH_RCP_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ HSH_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t hsh_rcp_data_fields[] = {\n+\t{ HSH_RCP_DATA_AUTO_IPV4_MASK, 1, 742, 0x0000 },\n+\t{ HSH_RCP_DATA_HSH_TYPE, 5, 416, 0x0000 },\n+\t{ HSH_RCP_DATA_HSH_VALID, 1, 415, 0x0000 },\n+\t{ HSH_RCP_DATA_K, 320, 422, 0x0000 },\n+\t{ HSH_RCP_DATA_LOAD_DIST_TYPE, 2, 0, 0x0000 },\n+\t{ HSH_RCP_DATA_MAC_PORT_MASK, 2, 2, 0x0000 },\n+\t{ HSH_RCP_DATA_P_MASK, 1, 61, 0x0000 },\n+\t{ HSH_RCP_DATA_QW0_OFS, 8, 11, 0x0000 },\n+\t{ HSH_RCP_DATA_QW0_PE, 5, 6, 0x0000 },\n+\t{ HSH_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },\n+\t{ HSH_RCP_DATA_QW4_PE, 5, 19, 0x0000 },\n+\t{ HSH_RCP_DATA_SEED, 32, 382, 0x0000 },\n+\t{ HSH_RCP_DATA_SORT, 2, 4, 0x0000 },\n+\t{ HSH_RCP_DATA_TNL_P, 1, 414, 0x0000 },\n+\t{ HSH_RCP_DATA_TOEPLITZ, 1, 421, 0x0000 },\n+\t{ HSH_RCP_DATA_W8_OFS, 8, 37, 0x0000 },\n+\t{ HSH_RCP_DATA_W8_PE, 5, 32, 0x0000 },\n+\t{ HSH_RCP_DATA_W8_SORT, 1, 45, 0x0000 },\n+\t{ HSH_RCP_DATA_W9_OFS, 8, 51, 0x0000 },\n+\t{ HSH_RCP_DATA_W9_P, 1, 60, 0x0000 },\n+\t{ HSH_RCP_DATA_W9_PE, 5, 46, 0x0000 },\n+\t{ HSH_RCP_DATA_W9_SORT, 1, 59, 0x0000 },\n+\t{ HSH_RCP_DATA_WORD_MASK, 320, 62, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t hsh_registers[] = {\n+\t{ HSH_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, hsh_rcp_ctrl_fields },\n+\t{ HSH_RCP_DATA, 1, 743, REGISTER_TYPE_WO, 0, 23, hsh_rcp_data_fields },\n+};\n+\n+static nt_fpga_field_init_t hst_rcp_ctrl_fields[] = {\n+\t{ HST_RCP_CTRL_ADR, 5, 0, 0x0000 },\n+\t{ HST_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t hst_rcp_data_fields[] = {\n+\t{ HST_RCP_DATA_END_DYN, 5, 16, 0x0000 },\n+\t{ HST_RCP_DATA_END_OFS, 10, 21, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF0_CMD, 3, 31, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF0_DYN, 5, 34, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF0_OFS, 10, 39, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF0_VALUE, 16, 49, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF1_CMD, 3, 65, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF1_DYN, 5, 68, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF1_OFS, 10, 73, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF1_VALUE, 16, 83, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF2_CMD, 3, 99, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF2_DYN, 5, 102, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF2_OFS, 10, 107, 0x0000 },\n+\t{ HST_RCP_DATA_MODIF2_VALUE, 16, 117, 0x0000 },\n+\t{ HST_RCP_DATA_START_DYN, 5, 1, 0x0000 },\n+\t{ HST_RCP_DATA_START_OFS, 10, 6, 0x0000 },\n+\t{ HST_RCP_DATA_STRIP_MODE, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t hst_registers[] = {\n+\t{ HST_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, hst_rcp_ctrl_fields },\n+\t{ HST_RCP_DATA, 1, 133, REGISTER_TYPE_WO, 0, 17, hst_rcp_data_fields },\n+};\n+\n+static nt_fpga_field_init_t ifr_rcp_ctrl_fields[] = {\n+\t{ IFR_RCP_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ifr_rcp_data_fields[] = {\n+\t{ IFR_RCP_DATA_EN, 1, 0, 0x0000 },\n+\t{ IFR_RCP_DATA_MTU, 14, 1, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t ifr_registers[] = {\n+\t{ IFR_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, ifr_rcp_ctrl_fields },\n+\t{ IFR_RCP_DATA, 1, 15, REGISTER_TYPE_WO, 0, 2, ifr_rcp_data_fields },\n+};\n+\n+static nt_fpga_field_init_t iic_adr_fields[] = {\n+\t{ IIC_ADR_SLV_ADR, 7, 1, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_cr_fields[] = {\n+\t{ IIC_CR_EN, 1, 0, 0 },\t { IIC_CR_GC_EN, 1, 6, 0 },\n+\t{ IIC_CR_MSMS, 1, 2, 0 }, { IIC_CR_RST, 1, 7, 0 },\n+\t{ IIC_CR_RSTA, 1, 5, 0 }, { IIC_CR_TX, 1, 3, 0 },\n+\t{ IIC_CR_TXAK, 1, 4, 0 }, { IIC_CR_TXFIFO_RESET, 1, 1, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_dgie_fields[] = {\n+\t{ IIC_DGIE_GIE, 1, 31, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_gpo_fields[] = {\n+\t{ IIC_GPO_GPO_VAL, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_ier_fields[] = {\n+\t{ IIC_IER_INT0, 1, 0, 0 }, { IIC_IER_INT1, 1, 1, 0 },\n+\t{ IIC_IER_INT2, 1, 2, 0 }, { IIC_IER_INT3, 1, 3, 0 },\n+\t{ IIC_IER_INT4, 1, 4, 0 }, { IIC_IER_INT5, 1, 5, 0 },\n+\t{ IIC_IER_INT6, 1, 6, 0 }, { IIC_IER_INT7, 1, 7, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_isr_fields[] = {\n+\t{ IIC_ISR_INT0, 1, 0, 0 }, { IIC_ISR_INT1, 1, 1, 0 },\n+\t{ IIC_ISR_INT2, 1, 2, 0 }, { IIC_ISR_INT3, 1, 3, 0 },\n+\t{ IIC_ISR_INT4, 1, 4, 0 }, { IIC_ISR_INT5, 1, 5, 0 },\n+\t{ IIC_ISR_INT6, 1, 6, 0 }, { IIC_ISR_INT7, 1, 7, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_rx_fifo_fields[] = {\n+\t{ IIC_RX_FIFO_RXDATA, 8, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_rx_fifo_ocy_fields[] = {\n+\t{ IIC_RX_FIFO_OCY_OCY_VAL, 4, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_rx_fifo_pirq_fields[] = {\n+\t{ IIC_RX_FIFO_PIRQ_CMP_VAL, 4, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_softr_fields[] = {\n+\t{ IIC_SOFTR_RKEY, 4, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t iic_sr_fields[] = {\n+\t{ IIC_SR_AAS, 1, 1, 0 },\t { IIC_SR_ABGC, 1, 0, 0 },\n+\t{ IIC_SR_BB, 1, 2, 0 },\t\t { IIC_SR_RXFIFO_EMPTY, 1, 6, 1 },\n+\t{ IIC_SR_RXFIFO_FULL, 1, 5, 0 }, { IIC_SR_SRW, 1, 3, 0 },\n+\t{ IIC_SR_TXFIFO_EMPTY, 1, 7, 1 }, { IIC_SR_TXFIFO_FULL, 1, 4, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_tbuf_fields[] = {\n+\t{ IIC_TBUF_TBUF_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_ten_adr_fields[] = {\n+\t{ IIC_TEN_ADR_MSB_SLV_ADR, 3, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_thddat_fields[] = {\n+\t{ IIC_THDDAT_THDDAT_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_thdsta_fields[] = {\n+\t{ IIC_THDSTA_THDSTA_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_thigh_fields[] = {\n+\t{ IIC_THIGH_THIGH_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_tlow_fields[] = {\n+\t{ IIC_TLOW_TLOW_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_tsudat_fields[] = {\n+\t{ IIC_TSUDAT_TSUDAT_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_tsusta_fields[] = {\n+\t{ IIC_TSUSTA_TSUSTA_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_tsusto_fields[] = {\n+\t{ IIC_TSUSTO_TSUSTO_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_tx_fifo_fields[] = {\n+\t{ IIC_TX_FIFO_START, 1, 8, 0 },\n+\t{ IIC_TX_FIFO_STOP, 1, 9, 0 },\n+\t{ IIC_TX_FIFO_TXDATA, 8, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t iic_tx_fifo_ocy_fields[] = {\n+\t{ IIC_TX_FIFO_OCY_OCY_VAL, 4, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t iic_registers[] = {\n+\t{ IIC_ADR, 68, 8, REGISTER_TYPE_RW, 0, 1, iic_adr_fields },\n+\t{ IIC_CR, 64, 8, REGISTER_TYPE_RW, 0, 8, iic_cr_fields },\n+\t{ IIC_DGIE, 7, 32, REGISTER_TYPE_RW, 0, 1, iic_dgie_fields },\n+\t{ IIC_GPO, 73, 1, REGISTER_TYPE_RW, 0, 1, iic_gpo_fields },\n+\t{ IIC_IER, 10, 8, REGISTER_TYPE_RW, 0, 8, iic_ier_fields },\n+\t{ IIC_ISR, 8, 8, REGISTER_TYPE_RW, 0, 8, iic_isr_fields },\n+\t{ IIC_RX_FIFO, 67, 8, REGISTER_TYPE_RO, 0, 1, iic_rx_fifo_fields },\n+\t{\tIIC_RX_FIFO_OCY, 70, 4, REGISTER_TYPE_RO, 0, 1,\n+\t\tiic_rx_fifo_ocy_fields\n+\t},\n+\t{\tIIC_RX_FIFO_PIRQ, 72, 4, REGISTER_TYPE_RW, 0, 1,\n+\t\tiic_rx_fifo_pirq_fields\n+\t},\n+\t{ IIC_SOFTR, 16, 4, REGISTER_TYPE_WO, 0, 1, iic_softr_fields },\n+\t{ IIC_SR, 65, 8, REGISTER_TYPE_RO, 192, 8, iic_sr_fields },\n+\t{ IIC_TBUF, 78, 32, REGISTER_TYPE_RW, 0, 1, iic_tbuf_fields },\n+\t{ IIC_TEN_ADR, 71, 3, REGISTER_TYPE_RO, 0, 1, iic_ten_adr_fields },\n+\t{ IIC_THDDAT, 81, 32, REGISTER_TYPE_RW, 0, 1, iic_thddat_fields },\n+\t{ IIC_THDSTA, 76, 32, REGISTER_TYPE_RW, 0, 1, iic_thdsta_fields },\n+\t{ IIC_THIGH, 79, 32, REGISTER_TYPE_RW, 0, 1, iic_thigh_fields },\n+\t{ IIC_TLOW, 80, 32, REGISTER_TYPE_RW, 0, 1, iic_tlow_fields },\n+\t{ IIC_TSUDAT, 77, 32, REGISTER_TYPE_RW, 0, 1, iic_tsudat_fields },\n+\t{ IIC_TSUSTA, 74, 32, REGISTER_TYPE_RW, 0, 1, iic_tsusta_fields },\n+\t{ IIC_TSUSTO, 75, 32, REGISTER_TYPE_RW, 0, 1, iic_tsusto_fields },\n+\t{ IIC_TX_FIFO, 66, 10, REGISTER_TYPE_WO, 0, 3, iic_tx_fifo_fields },\n+\t{\tIIC_TX_FIFO_OCY, 69, 4, REGISTER_TYPE_RO, 0, 1,\n+\t\tiic_tx_fifo_ocy_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t ins_rcp_ctrl_fields[] = {\n+\t{ INS_RCP_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ INS_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ins_rcp_data_fields[] = {\n+\t{ INS_RCP_DATA_DYN, 5, 0, 0x0000 },\n+\t{ INS_RCP_DATA_LEN, 8, 15, 0x0000 },\n+\t{ INS_RCP_DATA_OFS, 10, 5, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t ins_registers[] = {\n+\t{ INS_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, ins_rcp_ctrl_fields },\n+\t{ INS_RCP_DATA, 1, 23, REGISTER_TYPE_WO, 0, 3, ins_rcp_data_fields },\n+};\n+\n+static nt_fpga_field_init_t km_cam_ctrl_fields[] = {\n+\t{ KM_CAM_CTRL_ADR, 13, 0, 0x0000 },\n+\t{ KM_CAM_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_cam_data_fields[] = {\n+\t{ KM_CAM_DATA_FT0, 4, 192, 0x0000 },\n+\t{ KM_CAM_DATA_FT1, 4, 196, 0x0000 },\n+\t{ KM_CAM_DATA_FT2, 4, 200, 0x0000 },\n+\t{ KM_CAM_DATA_FT3, 4, 204, 0x0000 },\n+\t{ KM_CAM_DATA_FT4, 4, 208, 0x0000 },\n+\t{ KM_CAM_DATA_FT5, 4, 212, 0x0000 },\n+\t{ KM_CAM_DATA_W0, 32, 0, 0x0000 },\n+\t{ KM_CAM_DATA_W1, 32, 32, 0x0000 },\n+\t{ KM_CAM_DATA_W2, 32, 64, 0x0000 },\n+\t{ KM_CAM_DATA_W3, 32, 96, 0x0000 },\n+\t{ KM_CAM_DATA_W4, 32, 128, 0x0000 },\n+\t{ KM_CAM_DATA_W5, 32, 160, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_rcp_ctrl_fields[] = {\n+\t{ KM_RCP_CTRL_ADR, 5, 0, 0x0000 },\n+\t{ KM_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_rcp_data_fields[] = {\n+\t{ KM_RCP_DATA_BANK_A, 12, 694, 0x0000 },\n+\t{ KM_RCP_DATA_BANK_B, 12, 706, 0x0000 },\n+\t{ KM_RCP_DATA_DUAL, 1, 651, 0x0000 },\n+\t{ KM_RCP_DATA_DW0_B_DYN, 5, 729, 0x0000 },\n+\t{ KM_RCP_DATA_DW0_B_OFS, 8, 734, 0x0000 },\n+\t{ KM_RCP_DATA_DW10_DYN, 5, 55, 0x0000 },\n+\t{ KM_RCP_DATA_DW10_OFS, 8, 60, 0x0000 },\n+\t{ KM_RCP_DATA_DW10_SEL_A, 2, 68, 0x0000 },\n+\t{ KM_RCP_DATA_DW10_SEL_B, 2, 70, 0x0000 },\n+\t{ KM_RCP_DATA_DW2_B_DYN, 5, 742, 0x0000 },\n+\t{ KM_RCP_DATA_DW2_B_OFS, 8, 747, 0x0000 },\n+\t{ KM_RCP_DATA_DW8_DYN, 5, 36, 0x0000 },\n+\t{ KM_RCP_DATA_DW8_OFS, 8, 41, 0x0000 },\n+\t{ KM_RCP_DATA_DW8_SEL_A, 3, 49, 0x0000 },\n+\t{ KM_RCP_DATA_DW8_SEL_B, 3, 52, 0x0000 },\n+\t{ KM_RCP_DATA_EL_A, 4, 653, 0x0000 },\n+\t{ KM_RCP_DATA_EL_B, 3, 657, 0x0000 },\n+\t{ KM_RCP_DATA_FTM_A, 16, 662, 0x0000 },\n+\t{ KM_RCP_DATA_FTM_B, 16, 678, 0x0000 },\n+\t{ KM_RCP_DATA_INFO_A, 1, 660, 0x0000 },\n+\t{ KM_RCP_DATA_INFO_B, 1, 661, 0x0000 },\n+\t{ KM_RCP_DATA_KEYWAY_A, 1, 725, 0x0000 },\n+\t{ KM_RCP_DATA_KEYWAY_B, 1, 726, 0x0000 },\n+\t{ KM_RCP_DATA_KL_A, 4, 718, 0x0000 },\n+\t{ KM_RCP_DATA_KL_B, 3, 722, 0x0000 },\n+\t{ KM_RCP_DATA_MASK_A, 384, 75, 0x0000 },\n+\t{ KM_RCP_DATA_MASK_B, 192, 459, 0x0000 },\n+\t{ KM_RCP_DATA_PAIRED, 1, 652, 0x0000 },\n+\t{ KM_RCP_DATA_QW0_DYN, 5, 0, 0x0000 },\n+\t{ KM_RCP_DATA_QW0_OFS, 8, 5, 0x0000 },\n+\t{ KM_RCP_DATA_QW0_SEL_A, 3, 13, 0x0000 },\n+\t{ KM_RCP_DATA_QW0_SEL_B, 3, 16, 0x0000 },\n+\t{ KM_RCP_DATA_QW4_DYN, 5, 19, 0x0000 },\n+\t{ KM_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },\n+\t{ KM_RCP_DATA_QW4_SEL_A, 2, 32, 0x0000 },\n+\t{ KM_RCP_DATA_QW4_SEL_B, 2, 34, 0x0000 },\n+\t{ KM_RCP_DATA_SW4_B_DYN, 5, 755, 0x0000 },\n+\t{ KM_RCP_DATA_SW4_B_OFS, 8, 760, 0x0000 },\n+\t{ KM_RCP_DATA_SW5_B_DYN, 5, 768, 0x0000 },\n+\t{ KM_RCP_DATA_SW5_B_OFS, 8, 773, 0x0000 },\n+\t{ KM_RCP_DATA_SWX_CCH, 1, 72, 0x0000 },\n+\t{ KM_RCP_DATA_SWX_SEL_A, 1, 73, 0x0000 },\n+\t{ KM_RCP_DATA_SWX_SEL_B, 1, 74, 0x0000 },\n+\t{ KM_RCP_DATA_SYNERGY_MODE, 2, 727, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_status_fields[] = {\n+\t{ KM_STATUS_TCQ_RDY, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_tcam_ctrl_fields[] = {\n+\t{ KM_TCAM_CTRL_ADR, 14, 0, 0x0000 },\n+\t{ KM_TCAM_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_tcam_data_fields[] = {\n+\t{ KM_TCAM_DATA_T, 72, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_tci_ctrl_fields[] = {\n+\t{ KM_TCI_CTRL_ADR, 10, 0, 0x0000 },\n+\t{ KM_TCI_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_tci_data_fields[] = {\n+\t{ KM_TCI_DATA_COLOR, 32, 0, 0x0000 },\n+\t{ KM_TCI_DATA_FT, 4, 32, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_tcq_ctrl_fields[] = {\n+\t{ KM_TCQ_CTRL_ADR, 7, 0, 0x0000 },\n+\t{ KM_TCQ_CTRL_CNT, 5, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t km_tcq_data_fields[] = {\n+\t{ KM_TCQ_DATA_BANK_MASK, 12, 0, 0x0000 },\n+\t{ KM_TCQ_DATA_QUAL, 3, 12, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t km_registers[] = {\n+\t{ KM_CAM_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2, km_cam_ctrl_fields },\n+\t{ KM_CAM_DATA, 3, 216, REGISTER_TYPE_WO, 0, 12, km_cam_data_fields },\n+\t{ KM_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, km_rcp_ctrl_fields },\n+\t{ KM_RCP_DATA, 1, 781, REGISTER_TYPE_WO, 0, 44, km_rcp_data_fields },\n+\t{ KM_STATUS, 10, 1, REGISTER_TYPE_RO, 0, 1, km_status_fields },\n+\t{ KM_TCAM_CTRL, 4, 32, REGISTER_TYPE_WO, 0, 2, km_tcam_ctrl_fields },\n+\t{ KM_TCAM_DATA, 5, 72, REGISTER_TYPE_WO, 0, 1, km_tcam_data_fields },\n+\t{ KM_TCI_CTRL, 6, 32, REGISTER_TYPE_WO, 0, 2, km_tci_ctrl_fields },\n+\t{ KM_TCI_DATA, 7, 36, REGISTER_TYPE_WO, 0, 2, km_tci_data_fields },\n+\t{ KM_TCQ_CTRL, 8, 21, REGISTER_TYPE_WO, 0, 2, km_tcq_ctrl_fields },\n+\t{ KM_TCQ_DATA, 9, 15, REGISTER_TYPE_WO, 0, 2, km_tcq_data_fields },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_bad_code_fields[] = {\n+\t{ MAC_PCS_BAD_CODE_CODE_ERR, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_bip_err_fields[] = {\n+\t{ MAC_PCS_BIP_ERR_BIP_ERR, 640, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_block_lock_fields[] = {\n+\t{ MAC_PCS_BLOCK_LOCK_LOCK, 20, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_block_lock_chg_fields[] = {\n+\t{ MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG, 20, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_debounce_ctrl_fields[] = {\n+\t{ MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY, 8, 8, 10 },\n+\t{ MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN, 1, 16, 0 },\n+\t{ MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY, 8, 0, 10 },\n+\t{ MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL, 2, 17, 2 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_drp_ctrl_fields[] = {\n+\t{ MAC_PCS_DRP_CTRL_ADR, 10, 16, 0 },\n+\t{ MAC_PCS_DRP_CTRL_DATA, 16, 0, 0 },\n+\t{ MAC_PCS_DRP_CTRL_DBG_BUSY, 1, 30, 0x0000 },\n+\t{ MAC_PCS_DRP_CTRL_DONE, 1, 31, 0x0000 },\n+\t{ MAC_PCS_DRP_CTRL_MOD_ADR, 3, 26, 0 },\n+\t{ MAC_PCS_DRP_CTRL_WREN, 1, 29, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_ctrl_fields[] = {\n+\t{ MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN, 5, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_cw_cnt_fields[] = {\n+\t{ MAC_PCS_FEC_CW_CNT_CW_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_err_cnt_0_fields[] = {\n+\t{ MAC_PCS_FEC_ERR_CNT_0_ERR_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_err_cnt_1_fields[] = {\n+\t{ MAC_PCS_FEC_ERR_CNT_1_ERR_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_err_cnt_2_fields[] = {\n+\t{ MAC_PCS_FEC_ERR_CNT_2_ERR_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_err_cnt_3_fields[] = {\n+\t{ MAC_PCS_FEC_ERR_CNT_3_ERR_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_lane_dly_0_fields[] = {\n+\t{ MAC_PCS_FEC_LANE_DLY_0_DLY, 14, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_lane_dly_1_fields[] = {\n+\t{ MAC_PCS_FEC_LANE_DLY_1_DLY, 14, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_lane_dly_2_fields[] = {\n+\t{ MAC_PCS_FEC_LANE_DLY_2_DLY, 14, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_lane_dly_3_fields[] = {\n+\t{ MAC_PCS_FEC_LANE_DLY_3_DLY, 14, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_lane_map_fields[] = {\n+\t{ MAC_PCS_FEC_LANE_MAP_MAPPING, 8, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_stat_fields[] = {\n+\t{ MAC_PCS_FEC_STAT_AM_LOCK, 1, 10, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_AM_LOCK_0, 1, 3, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_AM_LOCK_1, 1, 4, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_AM_LOCK_2, 1, 5, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_AM_LOCK_3, 1, 6, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_BLOCK_LOCK, 1, 9, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_BYPASS, 1, 0, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_FEC_LANE_ALGN, 1, 7, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_HI_SER, 1, 2, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_PCS_LANE_ALGN, 1, 8, 0x0000 },\n+\t{ MAC_PCS_FEC_STAT_VALID, 1, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_fec_ucw_cnt_fields[] = {\n+\t{ MAC_PCS_FEC_UCW_CNT_UCW_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_ctl_rx_fields[] = {\n+\t{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_0, 1, 24, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_1, 1, 25, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_2, 1, 26, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_CDR_HOLD_3, 1, 27, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_EQUA_RST_0, 1, 20, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_EQUA_RST_1, 1, 21, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_EQUA_RST_2, 1, 22, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_EQUA_RST_3, 1, 23, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_LPM_EN_0, 1, 16, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_LPM_EN_1, 1, 17, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_LPM_EN_2, 1, 18, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_LPM_EN_3, 1, 19, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_POLARITY_0, 1, 0, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_POLARITY_1, 1, 1, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_POLARITY_2, 1, 2, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_POLARITY_3, 1, 3, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_RATE_0, 3, 4, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_RATE_1, 3, 7, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_RATE_2, 3, 10, 0 },\n+\t{ MAC_PCS_GTY_CTL_RX_RATE_3, 3, 13, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_ctl_tx_fields[] = {\n+\t{ MAC_PCS_GTY_CTL_TX_INHIBIT_0, 1, 4, 0 },\n+\t{ MAC_PCS_GTY_CTL_TX_INHIBIT_1, 1, 5, 0 },\n+\t{ MAC_PCS_GTY_CTL_TX_INHIBIT_2, 1, 6, 0 },\n+\t{ MAC_PCS_GTY_CTL_TX_INHIBIT_3, 1, 7, 0 },\n+\t{ MAC_PCS_GTY_CTL_TX_POLARITY_0, 1, 0, 0 },\n+\t{ MAC_PCS_GTY_CTL_TX_POLARITY_1, 1, 1, 0 },\n+\t{ MAC_PCS_GTY_CTL_TX_POLARITY_2, 1, 2, 0 },\n+\t{ MAC_PCS_GTY_CTL_TX_POLARITY_3, 1, 3, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_diff_ctl_fields[] = {\n+\t{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0, 5, 0, 24 },\n+\t{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1, 5, 5, 24 },\n+\t{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2, 5, 10, 24 },\n+\t{ MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3, 5, 15, 24 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_loop_fields[] = {\n+\t{ MAC_PCS_GTY_LOOP_GT_LOOP_0, 3, 0, 0 },\n+\t{ MAC_PCS_GTY_LOOP_GT_LOOP_1, 3, 3, 0 },\n+\t{ MAC_PCS_GTY_LOOP_GT_LOOP_2, 3, 6, 0 },\n+\t{ MAC_PCS_GTY_LOOP_GT_LOOP_3, 3, 9, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_post_cursor_fields[] = {\n+\t{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0, 5, 0, 20 },\n+\t{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1, 5, 5, 20 },\n+\t{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2, 5, 10, 20 },\n+\t{ MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3, 5, 15, 20 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_prbs_sel_fields[] = {\n+\t{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0, 4, 16, 0 },\n+\t{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1, 4, 20, 0 },\n+\t{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2, 4, 24, 0 },\n+\t{ MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3, 4, 28, 0 },\n+\t{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0, 4, 0, 0 },\n+\t{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1, 4, 4, 0 },\n+\t{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2, 4, 8, 0 },\n+\t{ MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3, 4, 12, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_pre_cursor_fields[] = {\n+\t{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0, 5, 0, 0 },\n+\t{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1, 5, 5, 0 },\n+\t{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2, 5, 10, 0 },\n+\t{ MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3, 5, 15, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_rx_buf_stat_fields[] = {\n+\t{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0, 3, 0, 0x0000 },\n+\t{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1, 3, 3, 0x0000 },\n+\t{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2, 3, 6, 0x0000 },\n+\t{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3, 3, 9, 0x0000 },\n+\t{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0, 3, 12, 0x0000 },\n+\t{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1, 3, 15, 0x0000 },\n+\t{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2, 3, 18, 0x0000 },\n+\t{ MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3, 3, 21, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_scan_ctl_fields[] = {\n+\t{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0, 1, 0, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1, 1, 1, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2, 1, 2, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3, 1, 3, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0, 1, 4, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1, 1, 5, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2, 1, 6, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3, 1, 7, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0, 1, 12, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1, 1, 13, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2, 1, 14, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3, 1, 15, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0, 1, 8, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1, 1, 9, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2, 1, 10, 0 },\n+\t{ MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3, 1, 11, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_scan_stat_fields[] = {\n+\t{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0, 1, 0, 0x0000 },\n+\t{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1, 1, 1, 0x0000 },\n+\t{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2, 1, 2, 0x0000 },\n+\t{ MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3, 1, 3, 0x0000 },\n+\t{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0, 1, 4, 0x0000 },\n+\t{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1, 1, 5, 0x0000 },\n+\t{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2, 1, 6, 0x0000 },\n+\t{ MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3, 1, 7, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_gty_stat_fields[] = {\n+\t{ MAC_PCS_GTY_STAT_RX_RST_DONE_0, 1, 4, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_RX_RST_DONE_1, 1, 5, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_RX_RST_DONE_2, 1, 6, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_RX_RST_DONE_3, 1, 7, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_TX_BUF_STAT_0, 2, 8, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_TX_BUF_STAT_1, 2, 10, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_TX_BUF_STAT_2, 2, 12, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_TX_BUF_STAT_3, 2, 14, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_TX_RST_DONE_0, 1, 0, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_TX_RST_DONE_1, 1, 1, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_TX_RST_DONE_2, 1, 2, 0x0000 },\n+\t{ MAC_PCS_GTY_STAT_TX_RST_DONE_3, 1, 3, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_link_summary_fields[] = {\n+\t{ MAC_PCS_LINK_SUMMARY_ABS, 1, 0, 0x0000 },\n+\t{ MAC_PCS_LINK_SUMMARY_LH_ABS, 1, 2, 0x0000 },\n+\t{ MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT, 1, 13, 0 },\n+\t{ MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT, 1, 14, 0 },\n+\t{ MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT, 8, 4, 0 },\n+\t{ MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE, 1, 3, 0x0000 },\n+\t{ MAC_PCS_LINK_SUMMARY_LOCAL_FAULT, 1, 17, 0x0000 },\n+\t{ MAC_PCS_LINK_SUMMARY_NIM_INTERR, 1, 12, 0x0000 },\n+\t{ MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE, 1, 1, 0x0000 },\n+\t{ MAC_PCS_LINK_SUMMARY_REMOTE_FAULT, 1, 18, 0x0000 },\n+\t{ MAC_PCS_LINK_SUMMARY_RESERVED, 2, 15, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_mac_pcs_config_fields[] = {\n+\t{ MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST, 1, 3, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE, 1, 5, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC, 1, 6, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST, 1, 1, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN, 1, 7, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST, 1, 2, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE, 1, 8, 1 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE, 1, 4, 1 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST, 1, 0, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE, 1, 9, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI, 1, 10, 0 },\n+\t{ MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN, 1, 11, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_max_pkt_len_fields[] = {\n+\t{ MAC_PCS_MAX_PKT_LEN_MAX_LEN, 14, 0, 10000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_phymac_misc_fields[] = {\n+\t{ MAC_PCS_PHYMAC_MISC_TS_EOP, 1, 3, 1 },\n+\t{ MAC_PCS_PHYMAC_MISC_TX_MUX_STATE, 4, 4, 0x0000 },\n+\t{ MAC_PCS_PHYMAC_MISC_TX_SEL_HOST, 1, 0, 1 },\n+\t{ MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP, 1, 2, 0 },\n+\t{ MAC_PCS_PHYMAC_MISC_TX_SEL_TFG, 1, 1, 0 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_phy_stat_fields[] = {\n+\t{ MAC_PCS_PHY_STAT_ALARM, 1, 2, 0x0000 },\n+\t{ MAC_PCS_PHY_STAT_MOD_PRS, 1, 1, 0x0000 },\n+\t{ MAC_PCS_PHY_STAT_RX_LOS, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_stat_pcs_rx_fields[] = {\n+\t{ MAC_PCS_STAT_PCS_RX_ALIGNED, 1, 1, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_ALIGNED_ERR, 1, 2, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS, 1, 9, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_HI_BER, 1, 8, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LOCAL_FAULT, 1, 6, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_MISALIGNED, 1, 3, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_REMOTE_FAULT, 1, 7, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_STATUS, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_stat_pcs_rx_latch_fields[] = {\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED, 1, 1, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR, 1, 2, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS, 1, 9, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_HI_BER, 1, 8, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT, 1, 6, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED, 1, 3, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT, 1, 7, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_RX_LATCH_STATUS, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_stat_pcs_tx_fields[] = {\n+\t{ MAC_PCS_STAT_PCS_TX_LOCAL_FAULT, 1, 0, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED, 1, 5, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR, 1, 4, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED, 1, 9, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR, 1, 3, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED, 1, 8, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_TX_OVFOUT, 1, 2, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED, 1, 7, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_TX_UNFOUT, 1, 1, 0x0000 },\n+\t{ MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED, 1, 6, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_synced_fields[] = {\n+\t{ MAC_PCS_SYNCED_SYNC, 20, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_synced_err_fields[] = {\n+\t{ MAC_PCS_SYNCED_ERR_SYNC_ERROR, 20, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_test_err_fields[] = {\n+\t{ MAC_PCS_TEST_ERR_CODE_ERR, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_timestamp_comp_fields[] = {\n+\t{ MAC_PCS_TIMESTAMP_COMP_RX_DLY, 16, 0, 1451 },\n+\t{ MAC_PCS_TIMESTAMP_COMP_TX_DLY, 16, 16, 1440 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_vl_demuxed_fields[] = {\n+\t{ MAC_PCS_VL_DEMUXED_LOCK, 20, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_pcs_vl_demuxed_chg_fields[] = {\n+\t{ MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG, 20, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t mac_pcs_registers[] = {\n+\t{\tMAC_PCS_BAD_CODE, 26, 16, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_bad_code_fields\n+\t},\n+\t{\tMAC_PCS_BIP_ERR, 31, 640, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_bip_err_fields\n+\t},\n+\t{\tMAC_PCS_BLOCK_LOCK, 27, 20, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_block_lock_fields\n+\t},\n+\t{\tMAC_PCS_BLOCK_LOCK_CHG, 28, 20, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_block_lock_chg_fields\n+\t},\n+\t{\tMAC_PCS_DEBOUNCE_CTRL, 1, 19, REGISTER_TYPE_RW, 264714, 4,\n+\t\tmac_pcs_debounce_ctrl_fields\n+\t},\n+\t{\tMAC_PCS_DRP_CTRL, 43, 32, REGISTER_TYPE_MIXED, 0, 6,\n+\t\tmac_pcs_drp_ctrl_fields\n+\t},\n+\t{\tMAC_PCS_FEC_CTRL, 2, 5, REGISTER_TYPE_RW, 0, 1,\n+\t\tmac_pcs_fec_ctrl_fields\n+\t},\n+\t{\tMAC_PCS_FEC_CW_CNT, 9, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_cw_cnt_fields\n+\t},\n+\t{\tMAC_PCS_FEC_ERR_CNT_0, 11, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_err_cnt_0_fields\n+\t},\n+\t{\tMAC_PCS_FEC_ERR_CNT_1, 12, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_err_cnt_1_fields\n+\t},\n+\t{\tMAC_PCS_FEC_ERR_CNT_2, 13, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_err_cnt_2_fields\n+\t},\n+\t{\tMAC_PCS_FEC_ERR_CNT_3, 14, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_err_cnt_3_fields\n+\t},\n+\t{\tMAC_PCS_FEC_LANE_DLY_0, 5, 14, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_lane_dly_0_fields\n+\t},\n+\t{\tMAC_PCS_FEC_LANE_DLY_1, 6, 14, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_lane_dly_1_fields\n+\t},\n+\t{\tMAC_PCS_FEC_LANE_DLY_2, 7, 14, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_lane_dly_2_fields\n+\t},\n+\t{\tMAC_PCS_FEC_LANE_DLY_3, 8, 14, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_lane_dly_3_fields\n+\t},\n+\t{\tMAC_PCS_FEC_LANE_MAP, 4, 8, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_lane_map_fields\n+\t},\n+\t{\tMAC_PCS_FEC_STAT, 3, 11, REGISTER_TYPE_RO, 0, 11,\n+\t\tmac_pcs_fec_stat_fields\n+\t},\n+\t{\tMAC_PCS_FEC_UCW_CNT, 10, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_fec_ucw_cnt_fields\n+\t},\n+\t{\tMAC_PCS_GTY_CTL_RX, 38, 28, REGISTER_TYPE_RW, 0, 20,\n+\t\tmac_pcs_gty_ctl_rx_fields\n+\t},\n+\t{\tMAC_PCS_GTY_CTL_TX, 39, 8, REGISTER_TYPE_RW, 0, 8,\n+\t\tmac_pcs_gty_ctl_tx_fields\n+\t},\n+\t{\tMAC_PCS_GTY_DIFF_CTL, 35, 20, REGISTER_TYPE_RW, 811800, 4,\n+\t\tmac_pcs_gty_diff_ctl_fields\n+\t},\n+\t{\tMAC_PCS_GTY_LOOP, 20, 12, REGISTER_TYPE_RW, 0, 4,\n+\t\tmac_pcs_gty_loop_fields\n+\t},\n+\t{\tMAC_PCS_GTY_POST_CURSOR, 36, 20, REGISTER_TYPE_RW, 676500, 4,\n+\t\tmac_pcs_gty_post_cursor_fields\n+\t},\n+\t{\tMAC_PCS_GTY_PRBS_SEL, 40, 32, REGISTER_TYPE_RW, 0, 8,\n+\t\tmac_pcs_gty_prbs_sel_fields\n+\t},\n+\t{\tMAC_PCS_GTY_PRE_CURSOR, 37, 20, REGISTER_TYPE_RW, 0, 4,\n+\t\tmac_pcs_gty_pre_cursor_fields\n+\t},\n+\t{\tMAC_PCS_GTY_RX_BUF_STAT, 34, 24, REGISTER_TYPE_RO, 0, 8,\n+\t\tmac_pcs_gty_rx_buf_stat_fields\n+\t},\n+\t{\tMAC_PCS_GTY_SCAN_CTL, 41, 16, REGISTER_TYPE_RW, 0, 16,\n+\t\tmac_pcs_gty_scan_ctl_fields\n+\t},\n+\t{\tMAC_PCS_GTY_SCAN_STAT, 42, 8, REGISTER_TYPE_RO, 0, 8,\n+\t\tmac_pcs_gty_scan_stat_fields\n+\t},\n+\t{\tMAC_PCS_GTY_STAT, 33, 16, REGISTER_TYPE_RO, 0, 12,\n+\t\tmac_pcs_gty_stat_fields\n+\t},\n+\t{\tMAC_PCS_LINK_SUMMARY, 0, 19, REGISTER_TYPE_RO, 0, 11,\n+\t\tmac_pcs_link_summary_fields\n+\t},\n+\t{\tMAC_PCS_MAC_PCS_CONFIG, 19, 12, REGISTER_TYPE_RW, 272, 12,\n+\t\tmac_pcs_mac_pcs_config_fields\n+\t},\n+\t{\tMAC_PCS_MAX_PKT_LEN, 17, 14, REGISTER_TYPE_RW, 10000, 1,\n+\t\tmac_pcs_max_pkt_len_fields\n+\t},\n+\t{\tMAC_PCS_PHYMAC_MISC, 16, 8, REGISTER_TYPE_MIXED, 9, 5,\n+\t\tmac_pcs_phymac_misc_fields\n+\t},\n+\t{\tMAC_PCS_PHY_STAT, 15, 3, REGISTER_TYPE_RO, 0, 3,\n+\t\tmac_pcs_phy_stat_fields\n+\t},\n+\t{\tMAC_PCS_STAT_PCS_RX, 21, 10, REGISTER_TYPE_RO, 0, 10,\n+\t\tmac_pcs_stat_pcs_rx_fields\n+\t},\n+\t{\tMAC_PCS_STAT_PCS_RX_LATCH, 22, 10, REGISTER_TYPE_RO, 0, 10,\n+\t\tmac_pcs_stat_pcs_rx_latch_fields\n+\t},\n+\t{\tMAC_PCS_STAT_PCS_TX, 23, 10, REGISTER_TYPE_RO, 0, 10,\n+\t\tmac_pcs_stat_pcs_tx_fields\n+\t},\n+\t{\tMAC_PCS_SYNCED, 24, 20, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_synced_fields\n+\t},\n+\t{\tMAC_PCS_SYNCED_ERR, 25, 20, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_synced_err_fields\n+\t},\n+\t{\tMAC_PCS_TEST_ERR, 32, 16, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_test_err_fields\n+\t},\n+\t{\tMAC_PCS_TIMESTAMP_COMP, 18, 32, REGISTER_TYPE_RW, 94373291, 2,\n+\t\tmac_pcs_timestamp_comp_fields\n+\t},\n+\t{\tMAC_PCS_VL_DEMUXED, 29, 20, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_vl_demuxed_fields\n+\t},\n+\t{\tMAC_PCS_VL_DEMUXED_CHG, 30, 20, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_pcs_vl_demuxed_chg_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t mac_rx_bad_fcs_fields[] = {\n+\t{ MAC_RX_BAD_FCS_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_rx_fragment_fields[] = {\n+\t{ MAC_RX_FRAGMENT_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_rx_packet_bad_fcs_fields[] = {\n+\t{ MAC_RX_PACKET_BAD_FCS_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_rx_packet_small_fields[] = {\n+\t{ MAC_RX_PACKET_SMALL_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_rx_total_bytes_fields[] = {\n+\t{ MAC_RX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_rx_total_good_bytes_fields[] = {\n+\t{ MAC_RX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_rx_total_good_packets_fields[] = {\n+\t{ MAC_RX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_rx_total_packets_fields[] = {\n+\t{ MAC_RX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_rx_undersize_fields[] = {\n+\t{ MAC_RX_UNDERSIZE_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t mac_rx_registers[] = {\n+\t{\tMAC_RX_BAD_FCS, 0, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_bad_fcs_fields\n+\t},\n+\t{\tMAC_RX_FRAGMENT, 6, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_fragment_fields\n+\t},\n+\t{\tMAC_RX_PACKET_BAD_FCS, 7, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_packet_bad_fcs_fields\n+\t},\n+\t{\tMAC_RX_PACKET_SMALL, 3, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_packet_small_fields\n+\t},\n+\t{\tMAC_RX_TOTAL_BYTES, 4, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_total_bytes_fields\n+\t},\n+\t{\tMAC_RX_TOTAL_GOOD_BYTES, 5, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_total_good_bytes_fields\n+\t},\n+\t{\tMAC_RX_TOTAL_GOOD_PACKETS, 2, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_total_good_packets_fields\n+\t},\n+\t{\tMAC_RX_TOTAL_PACKETS, 1, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_total_packets_fields\n+\t},\n+\t{\tMAC_RX_UNDERSIZE, 8, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_rx_undersize_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t mac_tx_packet_small_fields[] = {\n+\t{ MAC_TX_PACKET_SMALL_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_tx_total_bytes_fields[] = {\n+\t{ MAC_TX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_tx_total_good_bytes_fields[] = {\n+\t{ MAC_TX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_tx_total_good_packets_fields[] = {\n+\t{ MAC_TX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t mac_tx_total_packets_fields[] = {\n+\t{ MAC_TX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t mac_tx_registers[] = {\n+\t{\tMAC_TX_PACKET_SMALL, 2, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_tx_packet_small_fields\n+\t},\n+\t{\tMAC_TX_TOTAL_BYTES, 3, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_tx_total_bytes_fields\n+\t},\n+\t{\tMAC_TX_TOTAL_GOOD_BYTES, 4, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_tx_total_good_bytes_fields\n+\t},\n+\t{\tMAC_TX_TOTAL_GOOD_PACKETS, 1, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_tx_total_good_packets_fields\n+\t},\n+\t{\tMAC_TX_TOTAL_PACKETS, 0, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tmac_tx_total_packets_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t pci_rd_tg_tg_ctrl_fields[] = {\n+\t{ PCI_RD_TG_TG_CTRL_TG_RD_RDY, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_rd_tg_tg_rdaddr_fields[] = {\n+\t{ PCI_RD_TG_TG_RDADDR_RAM_ADDR, 9, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_rd_tg_tg_rddata0_fields[] = {\n+\t{ PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_rd_tg_tg_rddata1_fields[] = {\n+\t{ PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_rd_tg_tg_rddata2_fields[] = {\n+\t{ PCI_RD_TG_TG_RDDATA2_REQ_HID, 6, 22, 0 },\n+\t{ PCI_RD_TG_TG_RDDATA2_REQ_SIZE, 22, 0, 0 },\n+\t{ PCI_RD_TG_TG_RDDATA2_WAIT, 1, 30, 0 },\n+\t{ PCI_RD_TG_TG_RDDATA2_WRAP, 1, 31, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_rd_tg_tg_rd_run_fields[] = {\n+\t{ PCI_RD_TG_TG_RD_RUN_RD_ITERATION, 16, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t pci_rd_tg_registers[] = {\n+\t{\tPCI_RD_TG_TG_CTRL, 5, 1, REGISTER_TYPE_RO, 0, 1,\n+\t\tpci_rd_tg_tg_ctrl_fields\n+\t},\n+\t{\tPCI_RD_TG_TG_RDADDR, 3, 9, REGISTER_TYPE_WO, 0, 1,\n+\t\tpci_rd_tg_tg_rdaddr_fields\n+\t},\n+\t{\tPCI_RD_TG_TG_RDDATA0, 0, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tpci_rd_tg_tg_rddata0_fields\n+\t},\n+\t{\tPCI_RD_TG_TG_RDDATA1, 1, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tpci_rd_tg_tg_rddata1_fields\n+\t},\n+\t{\tPCI_RD_TG_TG_RDDATA2, 2, 32, REGISTER_TYPE_WO, 0, 4,\n+\t\tpci_rd_tg_tg_rddata2_fields\n+\t},\n+\t{\tPCI_RD_TG_TG_RD_RUN, 4, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\tpci_rd_tg_tg_rd_run_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t pci_ta_control_fields[] = {\n+\t{ PCI_TA_CONTROL_ENABLE, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_ta_length_error_fields[] = {\n+\t{ PCI_TA_LENGTH_ERROR_AMOUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t pci_ta_packet_bad_fields[] = {\n+\t{ PCI_TA_PACKET_BAD_AMOUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t pci_ta_packet_good_fields[] = {\n+\t{ PCI_TA_PACKET_GOOD_AMOUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t pci_ta_payload_error_fields[] = {\n+\t{ PCI_TA_PAYLOAD_ERROR_AMOUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t pci_ta_registers[] = {\n+\t{ PCI_TA_CONTROL, 0, 1, REGISTER_TYPE_WO, 0, 1, pci_ta_control_fields },\n+\t{\tPCI_TA_LENGTH_ERROR, 3, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tpci_ta_length_error_fields\n+\t},\n+\t{\tPCI_TA_PACKET_BAD, 2, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tpci_ta_packet_bad_fields\n+\t},\n+\t{\tPCI_TA_PACKET_GOOD, 1, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tpci_ta_packet_good_fields\n+\t},\n+\t{\tPCI_TA_PAYLOAD_ERROR, 4, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tpci_ta_payload_error_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t pci_wr_tg_tg_ctrl_fields[] = {\n+\t{ PCI_WR_TG_TG_CTRL_TG_WR_RDY, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_wr_tg_tg_seq_fields[] = {\n+\t{ PCI_WR_TG_TG_SEQ_SEQUENCE, 16, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_wr_tg_tg_wraddr_fields[] = {\n+\t{ PCI_WR_TG_TG_WRADDR_RAM_ADDR, 9, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_wr_tg_tg_wrdata0_fields[] = {\n+\t{ PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_wr_tg_tg_wrdata1_fields[] = {\n+\t{ PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_wr_tg_tg_wrdata2_fields[] = {\n+\t{ PCI_WR_TG_TG_WRDATA2_INC_MODE, 1, 29, 0 },\n+\t{ PCI_WR_TG_TG_WRDATA2_REQ_HID, 6, 22, 0 },\n+\t{ PCI_WR_TG_TG_WRDATA2_REQ_SIZE, 22, 0, 0 },\n+\t{ PCI_WR_TG_TG_WRDATA2_WAIT, 1, 30, 0 },\n+\t{ PCI_WR_TG_TG_WRDATA2_WRAP, 1, 31, 0 },\n+};\n+\n+static nt_fpga_field_init_t pci_wr_tg_tg_wr_run_fields[] = {\n+\t{ PCI_WR_TG_TG_WR_RUN_WR_ITERATION, 16, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t pci_wr_tg_registers[] = {\n+\t{\tPCI_WR_TG_TG_CTRL, 5, 1, REGISTER_TYPE_RO, 0, 1,\n+\t\tpci_wr_tg_tg_ctrl_fields\n+\t},\n+\t{\tPCI_WR_TG_TG_SEQ, 6, 16, REGISTER_TYPE_RW, 0, 1,\n+\t\tpci_wr_tg_tg_seq_fields\n+\t},\n+\t{\tPCI_WR_TG_TG_WRADDR, 3, 9, REGISTER_TYPE_WO, 0, 1,\n+\t\tpci_wr_tg_tg_wraddr_fields\n+\t},\n+\t{\tPCI_WR_TG_TG_WRDATA0, 0, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tpci_wr_tg_tg_wrdata0_fields\n+\t},\n+\t{\tPCI_WR_TG_TG_WRDATA1, 1, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tpci_wr_tg_tg_wrdata1_fields\n+\t},\n+\t{\tPCI_WR_TG_TG_WRDATA2, 2, 32, REGISTER_TYPE_WO, 0, 5,\n+\t\tpci_wr_tg_tg_wrdata2_fields\n+\t},\n+\t{\tPCI_WR_TG_TG_WR_RUN, 4, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\tpci_wr_tg_tg_wr_run_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t pdb_config_fields[] = {\n+\t{ PDB_CONFIG_PORT_OFS, 6, 3, 0 },\n+\t{ PDB_CONFIG_TS_FORMAT, 3, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pdb_rcp_ctrl_fields[] = {\n+\t{ PDB_RCP_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ PDB_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t pdb_rcp_data_fields[] = {\n+\t{ PDB_RCP_DATA_ALIGN, 1, 17, 0x0000 },\n+\t{ PDB_RCP_DATA_CRC_OVERWRITE, 1, 16, 0x0000 },\n+\t{ PDB_RCP_DATA_DESCRIPTOR, 4, 0, 0x0000 },\n+\t{ PDB_RCP_DATA_DESC_LEN, 5, 4, 0 },\n+\t{ PDB_RCP_DATA_DUPLICATE_BIT, 5, 61, 0x0000 },\n+\t{ PDB_RCP_DATA_DUPLICATE_EN, 1, 60, 0x0000 },\n+\t{ PDB_RCP_DATA_IP_PROT_TNL, 1, 57, 0x0000 },\n+\t{ PDB_RCP_DATA_OFS0_DYN, 5, 18, 0x0000 },\n+\t{ PDB_RCP_DATA_OFS0_REL, 8, 23, 0x0000 },\n+\t{ PDB_RCP_DATA_OFS1_DYN, 5, 31, 0x0000 },\n+\t{ PDB_RCP_DATA_OFS1_REL, 8, 36, 0x0000 },\n+\t{ PDB_RCP_DATA_OFS2_DYN, 5, 44, 0x0000 },\n+\t{ PDB_RCP_DATA_OFS2_REL, 8, 49, 0x0000 },\n+\t{ PDB_RCP_DATA_PCAP_KEEP_FCS, 1, 66, 0x0000 },\n+\t{ PDB_RCP_DATA_PPC_HSH, 2, 58, 0x0000 },\n+\t{ PDB_RCP_DATA_TX_IGNORE, 1, 14, 0x0000 },\n+\t{ PDB_RCP_DATA_TX_NOW, 1, 15, 0x0000 },\n+\t{ PDB_RCP_DATA_TX_PORT, 5, 9, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t pdb_registers[] = {\n+\t{ PDB_CONFIG, 2, 10, REGISTER_TYPE_WO, 0, 2, pdb_config_fields },\n+\t{ PDB_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, pdb_rcp_ctrl_fields },\n+\t{ PDB_RCP_DATA, 1, 67, REGISTER_TYPE_WO, 0, 18, pdb_rcp_data_fields },\n+};\n+\n+static nt_fpga_field_init_t pdi_cr_fields[] = {\n+\t{ PDI_CR_EN, 1, 0, 0 },\t { PDI_CR_PARITY, 1, 4, 0 },\n+\t{ PDI_CR_RST, 1, 1, 0 }, { PDI_CR_RXRST, 1, 2, 0 },\n+\t{ PDI_CR_STOP, 1, 5, 0 }, { PDI_CR_TXRST, 1, 3, 0 },\n+};\n+\n+static nt_fpga_field_init_t pdi_drr_fields[] = {\n+\t{ PDI_DRR_DRR, 8, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pdi_dtr_fields[] = {\n+\t{ PDI_DTR_DTR, 8, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t pdi_pre_fields[] = {\n+\t{ PDI_PRE_PRE, 7, 0, 3 },\n+};\n+\n+static nt_fpga_field_init_t pdi_sr_fields[] = {\n+\t{ PDI_SR_DISABLE_BUSY, 1, 2, 0 }, { PDI_SR_DONE, 1, 0, 0 },\n+\t{ PDI_SR_ENABLE_BUSY, 1, 1, 0 }, { PDI_SR_FRAME_ERR, 1, 5, 0 },\n+\t{ PDI_SR_OVERRUN_ERR, 1, 7, 0 }, { PDI_SR_PARITY_ERR, 1, 6, 0 },\n+\t{ PDI_SR_RXLVL, 7, 8, 0 },\t { PDI_SR_RX_BUSY, 1, 4, 0 },\n+\t{ PDI_SR_TXLVL, 7, 15, 0 },\t { PDI_SR_TX_BUSY, 1, 3, 0 },\n+};\n+\n+static nt_fpga_field_init_t pdi_srr_fields[] = {\n+\t{ PDI_SRR_RST, 4, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t pdi_registers[] = {\n+\t{ PDI_CR, 1, 6, REGISTER_TYPE_WO, 0, 6, pdi_cr_fields },\n+\t{ PDI_DRR, 4, 8, REGISTER_TYPE_RO, 0, 1, pdi_drr_fields },\n+\t{ PDI_DTR, 3, 8, REGISTER_TYPE_WO, 0, 1, pdi_dtr_fields },\n+\t{ PDI_PRE, 5, 7, REGISTER_TYPE_WO, 3, 1, pdi_pre_fields },\n+\t{ PDI_SR, 2, 22, REGISTER_TYPE_RO, 0, 10, pdi_sr_fields },\n+\t{ PDI_SRR, 0, 4, REGISTER_TYPE_WO, 0, 1, pdi_srr_fields },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_conf_fields[] = {\n+\t{ PTP1588_CONF_MII_RX_TX_LOOP, 1, 0, 0 },\n+\t{ PTP1588_CONF_MII_TX_RX_LOOP, 1, 1, 0 },\n+\t{ PTP1588_CONF_PHY_RST1, 1, 10, 1 },\n+\t{ PTP1588_CONF_PHY_RST2, 1, 11, 1 },\n+\t{ PTP1588_CONF_PTP_CTRL_LOCAL, 1, 24, 0 },\n+\t{ PTP1588_CONF_PTP_RX_CTRL, 2, 19, 0 },\n+\t{ PTP1588_CONF_PTP_TX_CTRL, 2, 21, 0 },\n+\t{ PTP1588_CONF_PTP_TX_CTRL_OS, 1, 23, 0 },\n+\t{ PTP1588_CONF_RX_IGNORE_DEST_ADDR, 1, 25, 0 },\n+\t{ PTP1588_CONF_TG_CMD, 2, 13, 0 },\n+\t{ PTP1588_CONF_TG_MODE, 1, 12, 0 },\n+\t{ PTP1588_CONF_TSM_MI_ACK, 1, 16, 0 },\n+\t{ PTP1588_CONF_TSM_MI_BUSY, 1, 15, 0 },\n+\t{ PTP1588_CONF_TSM_MI_ENA, 1, 18, 0 },\n+\t{ PTP1588_CONF_TSM_MI_REQ, 1, 17, 0 },\n+\t{ PTP1588_CONF_TX_IFG, 8, 2, 0 },\n+\t{ PTP1588_CONF_TX_IGNORE_DEST_ADDR, 1, 26, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_gp_data_fields[] = {\n+\t{ PTP1588_GP_DATA_GPIO, 9, 1, 0 },\n+\t{ PTP1588_GP_DATA_PWRDOWN_INTN, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_gp_data_lh_fields[] = {\n+\t{ PTP1588_GP_DATA_LH_GPIO, 9, 1, 0 },\n+\t{ PTP1588_GP_DATA_LH_PWRDOWN_INTN, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_gp_data_ll_fields[] = {\n+\t{ PTP1588_GP_DATA_LL_GPIO, 9, 1, 511 },\n+\t{ PTP1588_GP_DATA_LL_PWRDOWN_INTN, 1, 0, 1 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_gp_oe_fields[] = {\n+\t{ PTP1588_GP_OE_GPIO, 9, 1, 0 },\n+\t{ PTP1588_GP_OE_PWRDOWN_INTN, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_mac_inband_stat_fields[] = {\n+\t{ PTP1588_MAC_INBAND_STAT_DUPLEX, 1, 3, 0x0000 },\n+\t{ PTP1588_MAC_INBAND_STAT_LINK, 1, 0, 0x0000 },\n+\t{ PTP1588_MAC_INBAND_STAT_SPEED, 2, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_mac_mi_conf_fields[] = {\n+\t{ PTP1588_MAC_MI_CONF_ACCESS_TYPE, 1, 16, 0 },\n+\t{ PTP1588_MAC_MI_CONF_ADDRESS, 16, 0, 0 },\n+\t{ PTP1588_MAC_MI_CONF_RDY, 1, 17, 1 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_mac_mi_data_fields[] = {\n+\t{ PTP1588_MAC_MI_DATA_DATA, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_rx_host_adr_lsb_fields[] = {\n+\t{ PTP1588_RX_HOST_ADR_LSB_LSB, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_rx_host_adr_msb_fields[] = {\n+\t{ PTP1588_RX_HOST_ADR_MSB_MSB, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_rx_host_conf_fields[] = {\n+\t{ PTP1588_RX_HOST_CONF_ENA, 1, 11, 0 },\n+\t{ PTP1588_RX_HOST_CONF_RDPTR, 11, 0, 0 },\n+\t{ PTP1588_RX_HOST_CONF_REDUCED, 1, 12, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_stat_fields[] = {\n+\t{ PTP1588_STAT_DATA, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_stat_conf_fields[] = {\n+\t{ PTP1588_STAT_CONF_INDEX, 5, 0, 0 },\n+\t{ PTP1588_STAT_CONF_LOCK, 1, 5, 0 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_first_dat_fields[] = {\n+\t{ PTP1588_TX_FIRST_DAT_DAT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_last1_dat_fields[] = {\n+\t{ PTP1588_TX_LAST1_DAT_DAT, 8, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_last2_dat_fields[] = {\n+\t{ PTP1588_TX_LAST2_DAT_DAT, 16, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_last3_dat_fields[] = {\n+\t{ PTP1588_TX_LAST3_DAT_DAT, 24, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_last4_dat_fields[] = {\n+\t{ PTP1588_TX_LAST4_DAT_DAT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_mid_dat_fields[] = {\n+\t{ PTP1588_TX_MID_DAT_DAT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_packet_state_fields[] = {\n+\t{ PTP1588_TX_PACKET_STATE_MSG_TYPE, 4, 16, 0x0000 },\n+\t{ PTP1588_TX_PACKET_STATE_PCK_TYPE, 3, 20, 0x0000 },\n+\t{ PTP1588_TX_PACKET_STATE_SEQ_ID, 16, 0, 0x0000 },\n+\t{ PTP1588_TX_PACKET_STATE_TEST_MARGIN, 7, 23, 0x0000 },\n+\t{ PTP1588_TX_PACKET_STATE_VALID, 1, 30, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_status_fields[] = {\n+\t{ PTP1588_TX_STATUS_DB_ERR, 1, 10, 1 },\n+\t{ PTP1588_TX_STATUS_DB_FULL, 1, 9, 1 },\n+\t{ PTP1588_TX_STATUS_FIFO_STATUS, 9, 0, 0 },\n+\t{ PTP1588_TX_STATUS_RDY, 1, 11, 1 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_timestamp_ns_fields[] = {\n+\t{ PTP1588_TX_TIMESTAMP_NS_TIMESTAMP, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t ptp1588_tx_timestamp_sec_fields[] = {\n+\t{ PTP1588_TX_TIMESTAMP_SEC_TIMESTAMP, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t ptp1588_registers[] = {\n+\t{\tPTP1588_CONF, 0, 27, REGISTER_TYPE_MIXED, 3072, 17,\n+\t\tptp1588_conf_fields\n+\t},\n+\t{\tPTP1588_GP_DATA, 20, 10, REGISTER_TYPE_RW, 0, 2,\n+\t\tptp1588_gp_data_fields\n+\t},\n+\t{\tPTP1588_GP_DATA_LH, 22, 10, REGISTER_TYPE_RO, 0, 2,\n+\t\tptp1588_gp_data_lh_fields\n+\t},\n+\t{\tPTP1588_GP_DATA_LL, 21, 10, REGISTER_TYPE_RO, 1023, 2,\n+\t\tptp1588_gp_data_ll_fields\n+\t},\n+\t{ PTP1588_GP_OE, 19, 10, REGISTER_TYPE_WO, 0, 2, ptp1588_gp_oe_fields },\n+\t{\tPTP1588_MAC_INBAND_STAT, 3, 4, REGISTER_TYPE_RO, 0, 3,\n+\t\tptp1588_mac_inband_stat_fields\n+\t},\n+\t{\tPTP1588_MAC_MI_CONF, 17, 18, REGISTER_TYPE_MIXED, 131072, 3,\n+\t\tptp1588_mac_mi_conf_fields\n+\t},\n+\t{\tPTP1588_MAC_MI_DATA, 18, 32, REGISTER_TYPE_RW, 0, 1,\n+\t\tptp1588_mac_mi_data_fields\n+\t},\n+\t{\tPTP1588_RX_HOST_ADR_LSB, 8, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tptp1588_rx_host_adr_lsb_fields\n+\t},\n+\t{\tPTP1588_RX_HOST_ADR_MSB, 9, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tptp1588_rx_host_adr_msb_fields\n+\t},\n+\t{\tPTP1588_RX_HOST_CONF, 7, 13, REGISTER_TYPE_RW, 0, 3,\n+\t\tptp1588_rx_host_conf_fields\n+\t},\n+\t{ PTP1588_STAT, 6, 32, REGISTER_TYPE_RO, 0, 1, ptp1588_stat_fields },\n+\t{\tPTP1588_STAT_CONF, 5, 6, REGISTER_TYPE_WO, 0, 2,\n+\t\tptp1588_stat_conf_fields\n+\t},\n+\t{\tPTP1588_TX_FIRST_DAT, 10, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tptp1588_tx_first_dat_fields\n+\t},\n+\t{\tPTP1588_TX_LAST1_DAT, 12, 8, REGISTER_TYPE_WO, 0, 1,\n+\t\tptp1588_tx_last1_dat_fields\n+\t},\n+\t{\tPTP1588_TX_LAST2_DAT, 13, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\tptp1588_tx_last2_dat_fields\n+\t},\n+\t{\tPTP1588_TX_LAST3_DAT, 14, 24, REGISTER_TYPE_WO, 0, 1,\n+\t\tptp1588_tx_last3_dat_fields\n+\t},\n+\t{\tPTP1588_TX_LAST4_DAT, 15, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tptp1588_tx_last4_dat_fields\n+\t},\n+\t{\tPTP1588_TX_MID_DAT, 11, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tptp1588_tx_mid_dat_fields\n+\t},\n+\t{\tPTP1588_TX_PACKET_STATE, 4, 31, REGISTER_TYPE_RO, 0, 5,\n+\t\tptp1588_tx_packet_state_fields\n+\t},\n+\t{\tPTP1588_TX_STATUS, 16, 12, REGISTER_TYPE_RO, 3584, 4,\n+\t\tptp1588_tx_status_fields\n+\t},\n+\t{\tPTP1588_TX_TIMESTAMP_NS, 2, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tptp1588_tx_timestamp_ns_fields\n+\t},\n+\t{\tPTP1588_TX_TIMESTAMP_SEC, 1, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tptp1588_tx_timestamp_sec_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t qsl_qen_ctrl_fields[] = {\n+\t{ QSL_QEN_CTRL_ADR, 5, 0, 0x0000 },\n+\t{ QSL_QEN_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qsl_qen_data_fields[] = {\n+\t{ QSL_QEN_DATA_EN, 4, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qsl_qst_ctrl_fields[] = {\n+\t{ QSL_QST_CTRL_ADR, 12, 0, 0x0000 },\n+\t{ QSL_QST_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qsl_qst_data_fields[] = {\n+\t{ QSL_QST_DATA_LRE, 1, 9, 0x0000 },\n+\t{ QSL_QST_DATA_QEN, 1, 7, 0x0000 },\n+\t{ QSL_QST_DATA_QUEUE, 7, 0, 0x0000 },\n+\t{ QSL_QST_DATA_TCI, 16, 10, 0x0000 },\n+\t{ QSL_QST_DATA_TX_PORT, 1, 8, 0x0000 },\n+\t{ QSL_QST_DATA_VEN, 1, 26, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qsl_rcp_ctrl_fields[] = {\n+\t{ QSL_RCP_CTRL_ADR, 5, 0, 0x0000 },\n+\t{ QSL_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qsl_rcp_data_fields[] = {\n+\t{ QSL_RCP_DATA_DISCARD, 1, 0, 0x0000 },\n+\t{ QSL_RCP_DATA_DROP, 2, 1, 0x0000 },\n+\t{ QSL_RCP_DATA_LR, 2, 51, 0x0000 },\n+\t{ QSL_RCP_DATA_TBL_HI, 12, 15, 0x0000 },\n+\t{ QSL_RCP_DATA_TBL_IDX, 12, 27, 0x0000 },\n+\t{ QSL_RCP_DATA_TBL_LO, 12, 3, 0x0000 },\n+\t{ QSL_RCP_DATA_TBL_MSK, 12, 39, 0x0000 },\n+\t{ QSL_RCP_DATA_TSA, 1, 53, 0x0000 },\n+\t{ QSL_RCP_DATA_VLI, 2, 54, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qsl_unmq_ctrl_fields[] = {\n+\t{ QSL_UNMQ_CTRL_ADR, 1, 0, 0x0000 },\n+\t{ QSL_UNMQ_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qsl_unmq_data_fields[] = {\n+\t{ QSL_UNMQ_DATA_DEST_QUEUE, 7, 0, 0x0000 },\n+\t{ QSL_UNMQ_DATA_EN, 1, 7, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t qsl_registers[] = {\n+\t{ QSL_QEN_CTRL, 4, 32, REGISTER_TYPE_WO, 0, 2, qsl_qen_ctrl_fields },\n+\t{ QSL_QEN_DATA, 5, 4, REGISTER_TYPE_WO, 0, 1, qsl_qen_data_fields },\n+\t{ QSL_QST_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2, qsl_qst_ctrl_fields },\n+\t{ QSL_QST_DATA, 3, 27, REGISTER_TYPE_WO, 0, 6, qsl_qst_data_fields },\n+\t{ QSL_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, qsl_rcp_ctrl_fields },\n+\t{ QSL_RCP_DATA, 1, 56, REGISTER_TYPE_WO, 0, 9, qsl_rcp_data_fields },\n+\t{ QSL_UNMQ_CTRL, 6, 32, REGISTER_TYPE_WO, 0, 2, qsl_unmq_ctrl_fields },\n+\t{ QSL_UNMQ_DATA, 7, 8, REGISTER_TYPE_WO, 0, 2, qsl_unmq_data_fields },\n+};\n+\n+static nt_fpga_field_init_t qspi_cr_fields[] = {\n+\t{ QSPI_CR_CPHA, 1, 4, 0 }, { QSPI_CR_CPOL, 1, 3, 0 },\n+\t{ QSPI_CR_LOOP, 1, 0, 0 }, { QSPI_CR_LSBF, 1, 9, 0 },\n+\t{ QSPI_CR_MSSAE, 1, 7, 1 }, { QSPI_CR_MST, 1, 2, 0 },\n+\t{ QSPI_CR_MTI, 1, 8, 1 }, { QSPI_CR_RXFIFO_RST, 1, 6, 0 },\n+\t{ QSPI_CR_SPE, 1, 1, 0 }, { QSPI_CR_TXFIFO_RST, 1, 5, 0 },\n+};\n+\n+static nt_fpga_field_init_t qspi_dgie_fields[] = {\n+\t{ QSPI_DGIE_GIE, 1, 31, 0 },\n+};\n+\n+static nt_fpga_field_init_t qspi_drr_fields[] = {\n+\t{ QSPI_DRR_DATA_VAL, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qspi_dtr_fields[] = {\n+\t{ QSPI_DTR_DATA_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t qspi_ier_fields[] = {\n+\t{ QSPI_IER_CMD_ERR, 1, 13, 0 }, { QSPI_IER_CPOL_CPHA_ERR, 1, 9, 0 },\n+\t{ QSPI_IER_DRR_FULL, 1, 4, 0 }, { QSPI_IER_DRR_NEMPTY, 1, 8, 0 },\n+\t{ QSPI_IER_DRR_OR, 1, 5, 0 },\t{ QSPI_IER_DTR_EMPTY, 1, 2, 0 },\n+\t{ QSPI_IER_DTR_UR, 1, 3, 0 },\t{ QSPI_IER_LOOP_ERR, 1, 12, 0 },\n+\t{ QSPI_IER_MODF, 1, 0, 0 },\t{ QSPI_IER_MSB_ERR, 1, 11, 0 },\n+\t{ QSPI_IER_SLV_ERR, 1, 10, 0 }, { QSPI_IER_SLV_MODF, 1, 1, 0 },\n+\t{ QSPI_IER_SLV_MS, 1, 7, 0 },\t{ QSPI_IER_TXFIFO_HEMPTY, 1, 6, 0 },\n+};\n+\n+static nt_fpga_field_init_t qspi_isr_fields[] = {\n+\t{ QSPI_ISR_CMD_ERR, 1, 13, 0 }, { QSPI_ISR_CPOL_CPHA_ERR, 1, 9, 0 },\n+\t{ QSPI_ISR_DRR_FULL, 1, 4, 0 }, { QSPI_ISR_DRR_NEMPTY, 1, 8, 0 },\n+\t{ QSPI_ISR_DRR_OR, 1, 5, 0 },\t{ QSPI_ISR_DTR_EMPTY, 1, 2, 0 },\n+\t{ QSPI_ISR_DTR_UR, 1, 3, 0 },\t{ QSPI_ISR_LOOP_ERR, 1, 12, 0 },\n+\t{ QSPI_ISR_MODF, 1, 0, 0 },\t{ QSPI_ISR_MSB_ERR, 1, 11, 0 },\n+\t{ QSPI_ISR_SLV_ERR, 1, 10, 0 }, { QSPI_ISR_SLV_MODF, 1, 1, 0 },\n+\t{ QSPI_ISR_SLV_MS, 1, 7, 0 },\t{ QSPI_ISR_TXFIFO_HEMPTY, 1, 6, 0 },\n+};\n+\n+static nt_fpga_field_init_t qspi_rx_fifo_ocy_fields[] = {\n+\t{ QSPI_RX_FIFO_OCY_OCY_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t qspi_sr_fields[] = {\n+\t{ QSPI_SR_CMD_ERR, 1, 10, 0 }, { QSPI_SR_CPOL_CPHA_ERR, 1, 6, 0 },\n+\t{ QSPI_SR_LOOP_ERR, 1, 9, 0 }, { QSPI_SR_MODF, 1, 4, 0 },\n+\t{ QSPI_SR_MSB_ERR, 1, 8, 0 }, { QSPI_SR_RXEMPTY, 1, 0, 1 },\n+\t{ QSPI_SR_RXFULL, 1, 1, 0 }, { QSPI_SR_SLVMS, 1, 5, 1 },\n+\t{ QSPI_SR_SLV_ERR, 1, 7, 0 }, { QSPI_SR_TXEMPTY, 1, 2, 1 },\n+\t{ QSPI_SR_TXFULL, 1, 3, 0 },\n+};\n+\n+static nt_fpga_field_init_t qspi_srr_fields[] = {\n+\t{ QSPI_SRR_RST, 4, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t qspi_ssr_fields[] = {\n+\t{ QSPI_SSR_SEL_SLV, 32, 0, 4294967295 },\n+};\n+\n+static nt_fpga_field_init_t qspi_tx_fifo_ocy_fields[] = {\n+\t{ QSPI_TX_FIFO_OCY_OCY_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t qspi_registers[] = {\n+\t{ QSPI_CR, 24, 10, REGISTER_TYPE_RW, 384, 10, qspi_cr_fields },\n+\t{ QSPI_DGIE, 7, 32, REGISTER_TYPE_RW, 0, 1, qspi_dgie_fields },\n+\t{ QSPI_DRR, 27, 32, REGISTER_TYPE_RO, 0, 1, qspi_drr_fields },\n+\t{ QSPI_DTR, 26, 32, REGISTER_TYPE_WO, 0, 1, qspi_dtr_fields },\n+\t{ QSPI_IER, 10, 14, REGISTER_TYPE_RW, 0, 14, qspi_ier_fields },\n+\t{ QSPI_ISR, 8, 14, REGISTER_TYPE_RW, 0, 14, qspi_isr_fields },\n+\t{\tQSPI_RX_FIFO_OCY, 30, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tqspi_rx_fifo_ocy_fields\n+\t},\n+\t{ QSPI_SR, 25, 11, REGISTER_TYPE_RO, 37, 11, qspi_sr_fields },\n+\t{ QSPI_SRR, 16, 4, REGISTER_TYPE_WO, 0, 1, qspi_srr_fields },\n+\t{ QSPI_SSR, 28, 32, REGISTER_TYPE_RW, 4294967295, 1, qspi_ssr_fields },\n+\t{\tQSPI_TX_FIFO_OCY, 29, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\tqspi_tx_fifo_ocy_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t rac_dbg_ctrl_fields[] = {\n+\t{ RAC_DBG_CTRL_C, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rac_dbg_data_fields[] = {\n+\t{ RAC_DBG_DATA_D, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_buf_free_fields[] = {\n+\t{ RAC_RAB_BUF_FREE_IB_FREE, 9, 0, 511 },\n+\t{ RAC_RAB_BUF_FREE_IB_OVF, 1, 12, 0 },\n+\t{ RAC_RAB_BUF_FREE_OB_FREE, 9, 16, 511 },\n+\t{ RAC_RAB_BUF_FREE_OB_OVF, 1, 28, 0 },\n+\t{ RAC_RAB_BUF_FREE_TIMEOUT, 1, 31, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_buf_used_fields[] = {\n+\t{ RAC_RAB_BUF_USED_FLUSH, 1, 31, 0 },\n+\t{ RAC_RAB_BUF_USED_IB_USED, 9, 0, 0 },\n+\t{ RAC_RAB_BUF_USED_OB_USED, 9, 16, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_dma_ib_hi_fields[] = {\n+\t{ RAC_RAB_DMA_IB_HI_PHYADDR, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_dma_ib_lo_fields[] = {\n+\t{ RAC_RAB_DMA_IB_LO_PHYADDR, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_dma_ib_rd_fields[] = {\n+\t{ RAC_RAB_DMA_IB_RD_PTR, 16, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_dma_ib_wr_fields[] = {\n+\t{ RAC_RAB_DMA_IB_WR_PTR, 16, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_dma_ob_hi_fields[] = {\n+\t{ RAC_RAB_DMA_OB_HI_PHYADDR, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_dma_ob_lo_fields[] = {\n+\t{ RAC_RAB_DMA_OB_LO_PHYADDR, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_dma_ob_wr_fields[] = {\n+\t{ RAC_RAB_DMA_OB_WR_PTR, 16, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_ib_data_fields[] = {\n+\t{ RAC_RAB_IB_DATA_D, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_init_fields[] = {\n+\t{ RAC_RAB_INIT_RAB, 3, 0, 7 },\n+};\n+\n+static nt_fpga_field_init_t rac_rab_ob_data_fields[] = {\n+\t{ RAC_RAB_OB_DATA_D, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t rac_registers[] = {\n+\t{ RAC_DBG_CTRL, 4200, 32, REGISTER_TYPE_RW, 0, 1, rac_dbg_ctrl_fields },\n+\t{ RAC_DBG_DATA, 4208, 32, REGISTER_TYPE_RW, 0, 1, rac_dbg_data_fields },\n+\t{\tRAC_RAB_BUF_FREE, 4176, 32, REGISTER_TYPE_MIXED, 33489407, 5,\n+\t\trac_rab_buf_free_fields\n+\t},\n+\t{\tRAC_RAB_BUF_USED, 4184, 32, REGISTER_TYPE_MIXED, 0, 3,\n+\t\trac_rab_buf_used_fields\n+\t},\n+\t{\tRAC_RAB_DMA_IB_HI, 4360, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\trac_rab_dma_ib_hi_fields\n+\t},\n+\t{\tRAC_RAB_DMA_IB_LO, 4352, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\trac_rab_dma_ib_lo_fields\n+\t},\n+\t{\tRAC_RAB_DMA_IB_RD, 4424, 16, REGISTER_TYPE_RO, 0, 1,\n+\t\trac_rab_dma_ib_rd_fields\n+\t},\n+\t{\tRAC_RAB_DMA_IB_WR, 4416, 16, REGISTER_TYPE_WO, 0, 1,\n+\t\trac_rab_dma_ib_wr_fields\n+\t},\n+\t{\tRAC_RAB_DMA_OB_HI, 4376, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\trac_rab_dma_ob_hi_fields\n+\t},\n+\t{\tRAC_RAB_DMA_OB_LO, 4368, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\trac_rab_dma_ob_lo_fields\n+\t},\n+\t{\tRAC_RAB_DMA_OB_WR, 4480, 16, REGISTER_TYPE_RO, 0, 1,\n+\t\trac_rab_dma_ob_wr_fields\n+\t},\n+\t{\tRAC_RAB_IB_DATA, 4160, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\trac_rab_ib_data_fields\n+\t},\n+\t{ RAC_RAB_INIT, 4192, 3, REGISTER_TYPE_RW, 7, 1, rac_rab_init_fields },\n+\t{\tRAC_RAB_OB_DATA, 4168, 32, REGISTER_TYPE_RC1, 0, 1,\n+\t\trac_rab_ob_data_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t rfd_ctrl_fields[] = {\n+\t{ RFD_CTRL_CFP, 1, 2, 1 },\n+\t{ RFD_CTRL_ISL, 1, 0, 1 },\n+\t{ RFD_CTRL_PWMCW, 1, 1, 1 },\n+};\n+\n+static nt_fpga_field_init_t rfd_max_frame_size_fields[] = {\n+\t{ RFD_MAX_FRAME_SIZE_MAX, 14, 0, 9018 },\n+};\n+\n+static nt_fpga_field_init_t rfd_tnl_vlan_fields[] = {\n+\t{ RFD_TNL_VLAN_TPID0, 16, 0, 33024 },\n+\t{ RFD_TNL_VLAN_TPID1, 16, 16, 33024 },\n+};\n+\n+static nt_fpga_field_init_t rfd_vlan_fields[] = {\n+\t{ RFD_VLAN_TPID0, 16, 0, 33024 },\n+\t{ RFD_VLAN_TPID1, 16, 16, 33024 },\n+};\n+\n+static nt_fpga_field_init_t rfd_vxlan_fields[] = {\n+\t{ RFD_VXLAN_DP0, 16, 0, 4789 },\n+\t{ RFD_VXLAN_DP1, 16, 16, 4789 },\n+};\n+\n+static nt_fpga_register_init_t rfd_registers[] = {\n+\t{ RFD_CTRL, 0, 3, REGISTER_TYPE_WO, 7, 3, rfd_ctrl_fields },\n+\t{\tRFD_MAX_FRAME_SIZE, 1, 14, REGISTER_TYPE_WO, 9018, 1,\n+\t\trfd_max_frame_size_fields\n+\t},\n+\t{\tRFD_TNL_VLAN, 3, 32, REGISTER_TYPE_WO, 2164293888, 2,\n+\t\trfd_tnl_vlan_fields\n+\t},\n+\t{ RFD_VLAN, 2, 32, REGISTER_TYPE_WO, 2164293888, 2, rfd_vlan_fields },\n+\t{ RFD_VXLAN, 4, 32, REGISTER_TYPE_WO, 313856693, 2, rfd_vxlan_fields },\n+};\n+\n+static nt_fpga_field_init_t rmc_ctrl_fields[] = {\n+\t{ RMC_CTRL_BLOCK_KEEPA, 1, 1, 1 },\n+\t{ RMC_CTRL_BLOCK_MAC_PORT, 2, 8, 3 },\n+\t{ RMC_CTRL_BLOCK_RPP_SLICE, 8, 10, 0 },\n+\t{ RMC_CTRL_BLOCK_STATT, 1, 0, 1 },\n+\t{ RMC_CTRL_LAG_PHY_ODD_EVEN, 1, 24, 0 },\n+};\n+\n+static nt_fpga_field_init_t rmc_dbg_fields[] = {\n+\t{ RMC_DBG_MERGE, 31, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rmc_mac_if_fields[] = {\n+\t{ RMC_MAC_IF_ERR, 31, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rmc_status_fields[] = {\n+\t{ RMC_STATUS_DESCR_FIFO_OF, 1, 16, 0 },\n+\t{ RMC_STATUS_SF_RAM_OF, 1, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t rmc_registers[] = {\n+\t{ RMC_CTRL, 0, 25, REGISTER_TYPE_RW, 771, 5, rmc_ctrl_fields },\n+\t{ RMC_DBG, 2, 31, REGISTER_TYPE_RO, 0, 1, rmc_dbg_fields },\n+\t{ RMC_MAC_IF, 3, 31, REGISTER_TYPE_RO, 0, 1, rmc_mac_if_fields },\n+\t{ RMC_STATUS, 1, 17, REGISTER_TYPE_RO, 0, 2, rmc_status_fields },\n+};\n+\n+static nt_fpga_field_init_t rpl_ext_ctrl_fields[] = {\n+\t{ RPL_EXT_CTRL_ADR, 10, 0, 0x0000 },\n+\t{ RPL_EXT_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rpl_ext_data_fields[] = {\n+\t{ RPL_EXT_DATA_RPL_PTR, 12, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rpl_rcp_ctrl_fields[] = {\n+\t{ RPL_RCP_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ RPL_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rpl_rcp_data_fields[] = {\n+\t{ RPL_RCP_DATA_DYN, 5, 0, 0x0000 },\n+\t{ RPL_RCP_DATA_EXT_PRIO, 1, 35, 0x0000 },\n+\t{ RPL_RCP_DATA_LEN, 8, 15, 0x0000 },\n+\t{ RPL_RCP_DATA_OFS, 10, 5, 0x0000 },\n+\t{ RPL_RCP_DATA_RPL_PTR, 12, 23, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rpl_rpl_ctrl_fields[] = {\n+\t{ RPL_RPL_CTRL_ADR, 12, 0, 0x0000 },\n+\t{ RPL_RPL_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rpl_rpl_data_fields[] = {\n+\t{ RPL_RPL_DATA_VALUE, 128, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t rpl_registers[] = {\n+\t{ RPL_EXT_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2, rpl_ext_ctrl_fields },\n+\t{ RPL_EXT_DATA, 3, 12, REGISTER_TYPE_WO, 0, 1, rpl_ext_data_fields },\n+\t{ RPL_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, rpl_rcp_ctrl_fields },\n+\t{ RPL_RCP_DATA, 1, 36, REGISTER_TYPE_WO, 0, 5, rpl_rcp_data_fields },\n+\t{ RPL_RPL_CTRL, 4, 32, REGISTER_TYPE_WO, 0, 2, rpl_rpl_ctrl_fields },\n+\t{ RPL_RPL_DATA, 5, 128, REGISTER_TYPE_WO, 0, 1, rpl_rpl_data_fields },\n+};\n+\n+static nt_fpga_field_init_t rpp_lr_ifr_rcp_ctrl_fields[] = {\n+\t{ RPP_LR_IFR_RCP_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ RPP_LR_IFR_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rpp_lr_ifr_rcp_data_fields[] = {\n+\t{ RPP_LR_IFR_RCP_DATA_EN, 1, 0, 0x0000 },\n+\t{ RPP_LR_IFR_RCP_DATA_MTU, 14, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rpp_lr_rcp_ctrl_fields[] = {\n+\t{ RPP_LR_RCP_CTRL_ADR, 4, 0, 0x0000 },\n+\t{ RPP_LR_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rpp_lr_rcp_data_fields[] = {\n+\t{ RPP_LR_RCP_DATA_EXP, 14, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t rpp_lr_registers[] = {\n+\t{\tRPP_LR_IFR_RCP_CTRL, 2, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\trpp_lr_ifr_rcp_ctrl_fields\n+\t},\n+\t{\tRPP_LR_IFR_RCP_DATA, 3, 15, REGISTER_TYPE_WO, 0, 2,\n+\t\trpp_lr_ifr_rcp_data_fields\n+\t},\n+\t{\tRPP_LR_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\trpp_lr_rcp_ctrl_fields\n+\t},\n+\t{\tRPP_LR_RCP_DATA, 1, 14, REGISTER_TYPE_WO, 0, 1,\n+\t\trpp_lr_rcp_data_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t rst9563_ctrl_fields[] = {\n+\t{ RST9563_CTRL_PTP_MMCM_CLKSEL, 1, 2, 1 },\n+\t{ RST9563_CTRL_TS_CLKSEL, 1, 1, 1 },\n+\t{ RST9563_CTRL_TS_CLKSEL_OVERRIDE, 1, 0, 1 },\n+};\n+\n+static nt_fpga_field_init_t rst9563_power_fields[] = {\n+\t{ RST9563_POWER_PU_NSEB, 1, 1, 0 },\n+\t{ RST9563_POWER_PU_PHY, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t rst9563_rst_fields[] = {\n+\t{ RST9563_RST_CORE_MMCM, 1, 15, 0 }, { RST9563_RST_DDR4, 3, 3, 7 },\n+\t{ RST9563_RST_MAC_RX, 2, 9, 3 }, { RST9563_RST_PERIPH, 1, 13, 0 },\n+\t{ RST9563_RST_PHY, 2, 7, 3 },\t { RST9563_RST_PTP, 1, 11, 1 },\n+\t{ RST9563_RST_PTP_MMCM, 1, 16, 0 }, { RST9563_RST_RPP, 1, 2, 1 },\n+\t{ RST9563_RST_SDC, 1, 6, 1 },\t { RST9563_RST_SYS, 1, 0, 1 },\n+\t{ RST9563_RST_SYS_MMCM, 1, 14, 0 }, { RST9563_RST_TMC, 1, 1, 1 },\n+\t{ RST9563_RST_TS, 1, 12, 1 },\t { RST9563_RST_TS_MMCM, 1, 17, 0 },\n+};\n+\n+static nt_fpga_field_init_t rst9563_stat_fields[] = {\n+\t{ RST9563_STAT_CORE_MMCM_LOCKED, 1, 5, 0x0000 },\n+\t{ RST9563_STAT_DDR4_MMCM_LOCKED, 1, 2, 0x0000 },\n+\t{ RST9563_STAT_DDR4_PLL_LOCKED, 1, 3, 0x0000 },\n+\t{ RST9563_STAT_PTP_MMCM_LOCKED, 1, 0, 0x0000 },\n+\t{ RST9563_STAT_SYS_MMCM_LOCKED, 1, 4, 0x0000 },\n+\t{ RST9563_STAT_TS_MMCM_LOCKED, 1, 1, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t rst9563_sticky_fields[] = {\n+\t{ RST9563_STICKY_CORE_MMCM_UNLOCKED, 1, 5, 0x0000 },\n+\t{ RST9563_STICKY_DDR4_MMCM_UNLOCKED, 1, 2, 0x0000 },\n+\t{ RST9563_STICKY_DDR4_PLL_UNLOCKED, 1, 3, 0x0000 },\n+\t{ RST9563_STICKY_PTP_MMCM_UNLOCKED, 1, 0, 0x0000 },\n+\t{ RST9563_STICKY_SYS_MMCM_UNLOCKED, 1, 4, 0x0000 },\n+\t{ RST9563_STICKY_TS_MMCM_UNLOCKED, 1, 1, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t rst9563_registers[] = {\n+\t{ RST9563_CTRL, 1, 3, REGISTER_TYPE_RW, 7, 3, rst9563_ctrl_fields },\n+\t{ RST9563_POWER, 4, 2, REGISTER_TYPE_RW, 0, 2, rst9563_power_fields },\n+\t{ RST9563_RST, 0, 18, REGISTER_TYPE_RW, 8191, 14, rst9563_rst_fields },\n+\t{ RST9563_STAT, 2, 6, REGISTER_TYPE_RO, 0, 6, rst9563_stat_fields },\n+\t{\tRST9563_STICKY, 3, 6, REGISTER_TYPE_RC1, 0, 6,\n+\t\trst9563_sticky_fields\n+\t},\n+};\n+\n+static nt_fpga_field_init_t slc_rcp_ctrl_fields[] = {\n+\t{ SLC_RCP_CTRL_ADR, 6, 0, 0x0000 },\n+\t{ SLC_RCP_CTRL_CNT, 16, 16, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t slc_rcp_data_fields[] = {\n+\t{ SLC_RCP_DATA_PCAP, 1, 35, 0x0000 },\n+\t{ SLC_RCP_DATA_TAIL_DYN, 5, 15, 0x0000 },\n+\t{ SLC_RCP_DATA_TAIL_OFS, 15, 20, 0x0000 },\n+\t{ SLC_RCP_DATA_TAIL_SLC_EN, 1, 14, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t slc_registers[] = {\n+\t{ SLC_RCP_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 2, slc_rcp_ctrl_fields },\n+\t{ SLC_RCP_DATA, 1, 36, REGISTER_TYPE_WO, 0, 4, slc_rcp_data_fields },\n+};\n+\n+static nt_fpga_field_init_t spim_cfg_fields[] = {\n+\t{ SPIM_CFG_PRE, 3, 0, 5 },\n+};\n+\n+static nt_fpga_field_init_t spim_cr_fields[] = {\n+\t{ SPIM_CR_EN, 1, 1, 0 },\n+\t{ SPIM_CR_LOOP, 1, 0, 0 },\n+\t{ SPIM_CR_RXRST, 1, 3, 0 },\n+\t{ SPIM_CR_TXRST, 1, 2, 0 },\n+};\n+\n+static nt_fpga_field_init_t spim_drr_fields[] = {\n+\t{ SPIM_DRR_DRR, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t spim_dtr_fields[] = {\n+\t{ SPIM_DTR_DTR, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t spim_sr_fields[] = {\n+\t{ SPIM_SR_DONE, 1, 0, 0 }, { SPIM_SR_RXEMPTY, 1, 2, 1 },\n+\t{ SPIM_SR_RXFULL, 1, 4, 0 }, { SPIM_SR_RXLVL, 8, 16, 0 },\n+\t{ SPIM_SR_TXEMPTY, 1, 1, 1 }, { SPIM_SR_TXFULL, 1, 3, 0 },\n+\t{ SPIM_SR_TXLVL, 8, 8, 0 },\n+};\n+\n+static nt_fpga_field_init_t spim_srr_fields[] = {\n+\t{ SPIM_SRR_RST, 4, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t spim_registers[] = {\n+\t{ SPIM_CFG, 5, 3, REGISTER_TYPE_WO, 5, 1, spim_cfg_fields },\n+\t{ SPIM_CR, 1, 4, REGISTER_TYPE_WO, 0, 4, spim_cr_fields },\n+\t{ SPIM_DRR, 4, 32, REGISTER_TYPE_RO, 0, 1, spim_drr_fields },\n+\t{ SPIM_DTR, 3, 32, REGISTER_TYPE_WO, 0, 1, spim_dtr_fields },\n+\t{ SPIM_SR, 2, 24, REGISTER_TYPE_RO, 6, 7, spim_sr_fields },\n+\t{ SPIM_SRR, 0, 4, REGISTER_TYPE_WO, 0, 1, spim_srr_fields },\n+};\n+\n+static nt_fpga_field_init_t spis_cr_fields[] = {\n+\t{ SPIS_CR_DEBUG, 1, 4, 0 }, { SPIS_CR_EN, 1, 1, 0 },\n+\t{ SPIS_CR_LOOP, 1, 0, 0 }, { SPIS_CR_RXRST, 1, 3, 0 },\n+\t{ SPIS_CR_TXRST, 1, 2, 0 },\n+};\n+\n+static nt_fpga_field_init_t spis_drr_fields[] = {\n+\t{ SPIS_DRR_DRR, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t spis_dtr_fields[] = {\n+\t{ SPIS_DTR_DTR, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t spis_ram_ctrl_fields[] = {\n+\t{ SPIS_RAM_CTRL_ADR, 6, 0, 0 },\n+\t{ SPIS_RAM_CTRL_CNT, 6, 6, 0 },\n+};\n+\n+static nt_fpga_field_init_t spis_ram_data_fields[] = {\n+\t{ SPIS_RAM_DATA_DATA, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t spis_sr_fields[] = {\n+\t{ SPIS_SR_DONE, 1, 0, 0 },\t{ SPIS_SR_FRAME_ERR, 1, 24, 0 },\n+\t{ SPIS_SR_READ_ERR, 1, 25, 0 }, { SPIS_SR_RXEMPTY, 1, 2, 1 },\n+\t{ SPIS_SR_RXFULL, 1, 4, 0 },\t{ SPIS_SR_RXLVL, 8, 16, 0 },\n+\t{ SPIS_SR_TXEMPTY, 1, 1, 1 },\t{ SPIS_SR_TXFULL, 1, 3, 0 },\n+\t{ SPIS_SR_TXLVL, 8, 8, 0 },\t{ SPIS_SR_WRITE_ERR, 1, 26, 0 },\n+};\n+\n+static nt_fpga_field_init_t spis_srr_fields[] = {\n+\t{ SPIS_SRR_RST, 4, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t spis_registers[] = {\n+\t{ SPIS_CR, 1, 5, REGISTER_TYPE_WO, 0, 5, spis_cr_fields },\n+\t{ SPIS_DRR, 4, 32, REGISTER_TYPE_RO, 0, 1, spis_drr_fields },\n+\t{ SPIS_DTR, 3, 32, REGISTER_TYPE_WO, 0, 1, spis_dtr_fields },\n+\t{ SPIS_RAM_CTRL, 5, 12, REGISTER_TYPE_RW, 0, 2, spis_ram_ctrl_fields },\n+\t{ SPIS_RAM_DATA, 6, 32, REGISTER_TYPE_RW, 0, 1, spis_ram_data_fields },\n+\t{ SPIS_SR, 2, 27, REGISTER_TYPE_RO, 6, 10, spis_sr_fields },\n+\t{ SPIS_SRR, 0, 4, REGISTER_TYPE_WO, 0, 1, spis_srr_fields },\n+};\n+\n+static nt_fpga_field_init_t sta_byte_fields[] = {\n+\t{ STA_BYTE_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t sta_cfg_fields[] = {\n+\t{ STA_CFG_CNT_CLEAR, 1, 1, 0 },\n+\t{ STA_CFG_DMA_ENA, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t sta_cv_err_fields[] = {\n+\t{ STA_CV_ERR_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t sta_fcs_err_fields[] = {\n+\t{ STA_FCS_ERR_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t sta_host_adr_lsb_fields[] = {\n+\t{ STA_HOST_ADR_LSB_LSB, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t sta_host_adr_msb_fields[] = {\n+\t{ STA_HOST_ADR_MSB_MSB, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t sta_pckt_fields[] = {\n+\t{ STA_PCKT_CNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t sta_status_fields[] = {\n+\t{ STA_STATUS_STAT_TOGGLE_MISSED, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t sta_registers[] = {\n+\t{ STA_BYTE, 4, 32, REGISTER_TYPE_RO, 0, 1, sta_byte_fields },\n+\t{ STA_CFG, 0, 2, REGISTER_TYPE_RW, 0, 2, sta_cfg_fields },\n+\t{ STA_CV_ERR, 5, 32, REGISTER_TYPE_RO, 0, 1, sta_cv_err_fields },\n+\t{ STA_FCS_ERR, 6, 32, REGISTER_TYPE_RO, 0, 1, sta_fcs_err_fields },\n+\t{\tSTA_HOST_ADR_LSB, 1, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tsta_host_adr_lsb_fields\n+\t},\n+\t{\tSTA_HOST_ADR_MSB, 2, 32, REGISTER_TYPE_WO, 0, 1,\n+\t\tsta_host_adr_msb_fields\n+\t},\n+\t{ STA_PCKT, 3, 32, REGISTER_TYPE_RO, 0, 1, sta_pckt_fields },\n+\t{ STA_STATUS, 7, 1, REGISTER_TYPE_RC1, 0, 1, sta_status_fields },\n+};\n+\n+static nt_fpga_field_init_t tempmon_alarms_fields[] = {\n+\t{ TEMPMON_ALARMS_OT, 1, 1, 0x0000 },\n+\t{ TEMPMON_ALARMS_OT_OVERWR, 1, 2, 0 },\n+\t{ TEMPMON_ALARMS_OT_OVERWRVAL, 1, 3, 0 },\n+\t{ TEMPMON_ALARMS_TEMP, 1, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tempmon_stat_fields[] = {\n+\t{ TEMPMON_STAT_TEMP, 12, 0, 0x0000 },\n+};\n+\n+static nt_fpga_register_init_t tempmon_registers[] = {\n+\t{\tTEMPMON_ALARMS, 1, 4, REGISTER_TYPE_MIXED, 0, 4,\n+\t\ttempmon_alarms_fields\n+\t},\n+\t{ TEMPMON_STAT, 0, 12, REGISTER_TYPE_RO, 0, 1, tempmon_stat_fields },\n+};\n+\n+static nt_fpga_field_init_t tint_ctrl_fields[] = {\n+\t{ TINT_CTRL_INTERVAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tint_status_fields[] = {\n+\t{ TINT_STATUS_DELAYED, 8, 8, 0 },\n+\t{ TINT_STATUS_SKIPPED, 8, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t tint_registers[] = {\n+\t{ TINT_CTRL, 0, 32, REGISTER_TYPE_WO, 0, 1, tint_ctrl_fields },\n+\t{ TINT_STATUS, 1, 16, REGISTER_TYPE_RC1, 0, 2, tint_status_fields },\n+};\n+\n+static nt_fpga_field_init_t tmc_port_rpl_fields[] = {\n+\t{ TMC_PORT_RPL_P0, 1, 0, 0 },\n+\t{ TMC_PORT_RPL_P1, 1, 1, 1 },\n+};\n+\n+static nt_fpga_register_init_t tmc_registers[] = {\n+\t{ TMC_PORT_RPL, 0, 2, REGISTER_TYPE_WO, 2, 2, tmc_port_rpl_fields },\n+};\n+\n+static nt_fpga_field_init_t tsm_con0_config_fields[] = {\n+\t{ TSM_CON0_CONFIG_BLIND, 5, 8, 9 },\n+\t{ TSM_CON0_CONFIG_DC_SRC, 3, 5, 0 },\n+\t{ TSM_CON0_CONFIG_PORT, 3, 0, 0 },\n+\t{ TSM_CON0_CONFIG_PPSIN_2_5V, 1, 13, 0 },\n+\t{ TSM_CON0_CONFIG_SAMPLE_EDGE, 2, 3, 2 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con0_interface_fields[] = {\n+\t{ TSM_CON0_INTERFACE_EX_TERM, 2, 0, 3 },\n+\t{ TSM_CON0_INTERFACE_IN_REF_PWM, 8, 12, 128 },\n+\t{ TSM_CON0_INTERFACE_PWM_ENA, 1, 2, 0 },\n+\t{ TSM_CON0_INTERFACE_RESERVED, 1, 3, 0 },\n+\t{ TSM_CON0_INTERFACE_VTERM_PWM, 8, 4, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con0_sample_hi_fields[] = {\n+\t{ TSM_CON0_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con0_sample_lo_fields[] = {\n+\t{ TSM_CON0_SAMPLE_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con1_config_fields[] = {\n+\t{ TSM_CON1_CONFIG_BLIND, 5, 8, 9 },\n+\t{ TSM_CON1_CONFIG_DC_SRC, 3, 5, 0 },\n+\t{ TSM_CON1_CONFIG_PORT, 3, 0, 0 },\n+\t{ TSM_CON1_CONFIG_PPSIN_2_5V, 1, 13, 0 },\n+\t{ TSM_CON1_CONFIG_SAMPLE_EDGE, 2, 3, 2 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con1_sample_hi_fields[] = {\n+\t{ TSM_CON1_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con1_sample_lo_fields[] = {\n+\t{ TSM_CON1_SAMPLE_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con2_config_fields[] = {\n+\t{ TSM_CON2_CONFIG_BLIND, 5, 8, 9 },\n+\t{ TSM_CON2_CONFIG_DC_SRC, 3, 5, 0 },\n+\t{ TSM_CON2_CONFIG_PORT, 3, 0, 0 },\n+\t{ TSM_CON2_CONFIG_PPSIN_2_5V, 1, 13, 0 },\n+\t{ TSM_CON2_CONFIG_SAMPLE_EDGE, 2, 3, 2 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con2_sample_hi_fields[] = {\n+\t{ TSM_CON2_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con2_sample_lo_fields[] = {\n+\t{ TSM_CON2_SAMPLE_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con3_config_fields[] = {\n+\t{ TSM_CON3_CONFIG_BLIND, 5, 5, 26 },\n+\t{ TSM_CON3_CONFIG_PORT, 3, 0, 1 },\n+\t{ TSM_CON3_CONFIG_SAMPLE_EDGE, 2, 3, 1 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con3_sample_hi_fields[] = {\n+\t{ TSM_CON3_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con3_sample_lo_fields[] = {\n+\t{ TSM_CON3_SAMPLE_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con4_config_fields[] = {\n+\t{ TSM_CON4_CONFIG_BLIND, 5, 5, 26 },\n+\t{ TSM_CON4_CONFIG_PORT, 3, 0, 1 },\n+\t{ TSM_CON4_CONFIG_SAMPLE_EDGE, 2, 3, 1 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con4_sample_hi_fields[] = {\n+\t{ TSM_CON4_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con4_sample_lo_fields[] = {\n+\t{ TSM_CON4_SAMPLE_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con5_config_fields[] = {\n+\t{ TSM_CON5_CONFIG_BLIND, 5, 5, 26 },\n+\t{ TSM_CON5_CONFIG_PORT, 3, 0, 1 },\n+\t{ TSM_CON5_CONFIG_SAMPLE_EDGE, 2, 3, 1 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con5_sample_hi_fields[] = {\n+\t{ TSM_CON5_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con5_sample_lo_fields[] = {\n+\t{ TSM_CON5_SAMPLE_LO_TIME, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con6_config_fields[] = {\n+\t{ TSM_CON6_CONFIG_BLIND, 5, 5, 26 },\n+\t{ TSM_CON6_CONFIG_PORT, 3, 0, 1 },\n+\t{ TSM_CON6_CONFIG_SAMPLE_EDGE, 2, 3, 1 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con6_sample_hi_fields[] = {\n+\t{ TSM_CON6_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con6_sample_lo_fields[] = {\n+\t{ TSM_CON6_SAMPLE_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con7_host_sample_hi_fields[] = {\n+\t{ TSM_CON7_HOST_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_con7_host_sample_lo_fields[] = {\n+\t{ TSM_CON7_HOST_SAMPLE_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_config_fields[] = {\n+\t{ TSM_CONFIG_NTTS_SRC, 2, 5, 0 },\n+\t{ TSM_CONFIG_NTTS_SYNC, 1, 4, 0 },\n+\t{ TSM_CONFIG_TIMESET_EDGE, 2, 8, 1 },\n+\t{ TSM_CONFIG_TIMESET_SRC, 3, 10, 0 },\n+\t{ TSM_CONFIG_TIMESET_UP, 1, 7, 0 },\n+\t{ TSM_CONFIG_TS_FORMAT, 4, 0, 1 },\n+};\n+\n+static nt_fpga_field_init_t tsm_int_config_fields[] = {\n+\t{ TSM_INT_CONFIG_AUTO_DISABLE, 1, 0, 0 },\n+\t{ TSM_INT_CONFIG_MASK, 19, 1, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_int_stat_fields[] = {\n+\t{ TSM_INT_STAT_CAUSE, 19, 1, 0 },\n+\t{ TSM_INT_STAT_ENABLE, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_led_fields[] = {\n+\t{ TSM_LED_LED0_BG_COLOR, 2, 3, 0 }, { TSM_LED_LED0_COLOR, 2, 1, 0 },\n+\t{ TSM_LED_LED0_MODE, 1, 0, 0 },\t { TSM_LED_LED0_SRC, 4, 5, 0 },\n+\t{ TSM_LED_LED1_BG_COLOR, 2, 12, 0 }, { TSM_LED_LED1_COLOR, 2, 10, 0 },\n+\t{ TSM_LED_LED1_MODE, 1, 9, 0 },\t { TSM_LED_LED1_SRC, 4, 14, 1 },\n+\t{ TSM_LED_LED2_BG_COLOR, 2, 21, 0 }, { TSM_LED_LED2_COLOR, 2, 19, 0 },\n+\t{ TSM_LED_LED2_MODE, 1, 18, 0 }, { TSM_LED_LED2_SRC, 4, 23, 2 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_config_fields[] = {\n+\t{ TSM_NTTS_CONFIG_AUTO_HARDSET, 1, 5, 1 },\n+\t{ TSM_NTTS_CONFIG_EXT_CLK_ADJ, 1, 6, 0 },\n+\t{ TSM_NTTS_CONFIG_HIGH_SAMPLE, 1, 4, 0 },\n+\t{ TSM_NTTS_CONFIG_TS_SRC_FORMAT, 4, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_limit_hi_fields[] = {\n+\t{ TSM_NTTS_LIMIT_HI_SEC, 16, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_limit_lo_fields[] = {\n+\t{ TSM_NTTS_LIMIT_LO_NS, 32, 0, 100000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_offset_fields[] = {\n+\t{ TSM_NTTS_OFFSET_NS, 30, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_sample_hi_fields[] = {\n+\t{ TSM_NTTS_SAMPLE_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_sample_lo_fields[] = {\n+\t{ TSM_NTTS_SAMPLE_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_stat_fields[] = {\n+\t{ TSM_NTTS_STAT_NTTS_VALID, 1, 0, 0 },\n+\t{ TSM_NTTS_STAT_SIGNAL_LOST, 8, 1, 0 },\n+\t{ TSM_NTTS_STAT_SYNC_LOST, 8, 9, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_ts_t0_hi_fields[] = {\n+\t{ TSM_NTTS_TS_T0_HI_TIME, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_ts_t0_lo_fields[] = {\n+\t{ TSM_NTTS_TS_T0_LO_TIME, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ntts_ts_t0_offset_fields[] = {\n+\t{ TSM_NTTS_TS_T0_OFFSET_COUNT, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_pb_ctrl_fields[] = {\n+\t{ TSM_PB_CTRL_INSTMEM_WR, 1, 1, 0 },\n+\t{ TSM_PB_CTRL_RST, 1, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_pb_instmem_fields[] = {\n+\t{ TSM_PB_INSTMEM_MEM_ADDR, 14, 0, 0 },\n+\t{ TSM_PB_INSTMEM_MEM_DATA, 18, 14, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_pi_ctrl_i_fields[] = {\n+\t{ TSM_PI_CTRL_I_VAL, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_pi_ctrl_ki_fields[] = {\n+\t{ TSM_PI_CTRL_KI_GAIN, 24, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_pi_ctrl_kp_fields[] = {\n+\t{ TSM_PI_CTRL_KP_GAIN, 24, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_pi_ctrl_shl_fields[] = {\n+\t{ TSM_PI_CTRL_SHL_VAL, 4, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_stat_fields[] = {\n+\t{ TSM_STAT_HARD_SYNC, 8, 8, 0 }, { TSM_STAT_LINK_CON0, 1, 0, 0 },\n+\t{ TSM_STAT_LINK_CON1, 1, 1, 0 }, { TSM_STAT_LINK_CON2, 1, 2, 0 },\n+\t{ TSM_STAT_LINK_CON3, 1, 3, 0 }, { TSM_STAT_LINK_CON4, 1, 4, 0 },\n+\t{ TSM_STAT_LINK_CON5, 1, 5, 0 }, { TSM_STAT_NTTS_INSYNC, 1, 6, 0 },\n+\t{ TSM_STAT_PTP_MI_PRESENT, 1, 7, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_timer_ctrl_fields[] = {\n+\t{ TSM_TIMER_CTRL_TIMER_EN_T0, 1, 0, 0 },\n+\t{ TSM_TIMER_CTRL_TIMER_EN_T1, 1, 1, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_timer_t0_fields[] = {\n+\t{ TSM_TIMER_T0_MAX_COUNT, 30, 0, 50000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_timer_t1_fields[] = {\n+\t{ TSM_TIMER_T1_MAX_COUNT, 30, 0, 50000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_time_hardset_hi_fields[] = {\n+\t{ TSM_TIME_HARDSET_HI_TIME, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_time_hardset_lo_fields[] = {\n+\t{ TSM_TIME_HARDSET_LO_TIME, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_time_hi_fields[] = {\n+\t{ TSM_TIME_HI_SEC, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_time_lo_fields[] = {\n+\t{ TSM_TIME_LO_NS, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_time_rate_adj_fields[] = {\n+\t{ TSM_TIME_RATE_ADJ_FRACTION, 29, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_hi_fields[] = {\n+\t{ TSM_TS_HI_TIME, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_lo_fields[] = {\n+\t{ TSM_TS_LO_TIME, 32, 0, 0x0000 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_offset_fields[] = {\n+\t{ TSM_TS_OFFSET_NS, 30, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_stat_fields[] = {\n+\t{ TSM_TS_STAT_OVERRUN, 1, 16, 0 },\n+\t{ TSM_TS_STAT_SAMPLES, 16, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_stat_hi_offset_fields[] = {\n+\t{ TSM_TS_STAT_HI_OFFSET_NS, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_stat_lo_offset_fields[] = {\n+\t{ TSM_TS_STAT_LO_OFFSET_NS, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_stat_tar_hi_fields[] = {\n+\t{ TSM_TS_STAT_TAR_HI_SEC, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_stat_tar_lo_fields[] = {\n+\t{ TSM_TS_STAT_TAR_LO_NS, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_stat_x_fields[] = {\n+\t{ TSM_TS_STAT_X_NS, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_stat_x2_hi_fields[] = {\n+\t{ TSM_TS_STAT_X2_HI_NS, 16, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_ts_stat_x2_lo_fields[] = {\n+\t{ TSM_TS_STAT_X2_LO_NS, 32, 0, 0 },\n+};\n+\n+static nt_fpga_field_init_t tsm_utc_offset_fields[] = {\n+\t{ TSM_UTC_OFFSET_SEC, 8, 0, 0 },\n+};\n+\n+static nt_fpga_register_init_t tsm_registers[] = {\n+\t{\tTSM_CON0_CONFIG, 24, 14, REGISTER_TYPE_RW, 2320, 5,\n+\t\ttsm_con0_config_fields\n+\t},\n+\t{\tTSM_CON0_INTERFACE, 25, 20, REGISTER_TYPE_RW, 524291, 5,\n+\t\ttsm_con0_interface_fields\n+\t},\n+\t{\tTSM_CON0_SAMPLE_HI, 27, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con0_sample_hi_fields\n+\t},\n+\t{\tTSM_CON0_SAMPLE_LO, 26, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con0_sample_lo_fields\n+\t},\n+\t{\tTSM_CON1_CONFIG, 28, 14, REGISTER_TYPE_RW, 2320, 5,\n+\t\ttsm_con1_config_fields\n+\t},\n+\t{\tTSM_CON1_SAMPLE_HI, 30, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con1_sample_hi_fields\n+\t},\n+\t{\tTSM_CON1_SAMPLE_LO, 29, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con1_sample_lo_fields\n+\t},\n+\t{\tTSM_CON2_CONFIG, 31, 14, REGISTER_TYPE_RW, 2320, 5,\n+\t\ttsm_con2_config_fields\n+\t},\n+\t{\tTSM_CON2_SAMPLE_HI, 33, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con2_sample_hi_fields\n+\t},\n+\t{\tTSM_CON2_SAMPLE_LO, 32, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con2_sample_lo_fields\n+\t},\n+\t{\tTSM_CON3_CONFIG, 34, 10, REGISTER_TYPE_RW, 841, 3,\n+\t\ttsm_con3_config_fields\n+\t},\n+\t{\tTSM_CON3_SAMPLE_HI, 36, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con3_sample_hi_fields\n+\t},\n+\t{\tTSM_CON3_SAMPLE_LO, 35, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con3_sample_lo_fields\n+\t},\n+\t{\tTSM_CON4_CONFIG, 37, 10, REGISTER_TYPE_RW, 841, 3,\n+\t\ttsm_con4_config_fields\n+\t},\n+\t{\tTSM_CON4_SAMPLE_HI, 39, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con4_sample_hi_fields\n+\t},\n+\t{\tTSM_CON4_SAMPLE_LO, 38, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con4_sample_lo_fields\n+\t},\n+\t{\tTSM_CON5_CONFIG, 40, 10, REGISTER_TYPE_RW, 841, 3,\n+\t\ttsm_con5_config_fields\n+\t},\n+\t{\tTSM_CON5_SAMPLE_HI, 42, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con5_sample_hi_fields\n+\t},\n+\t{\tTSM_CON5_SAMPLE_LO, 41, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con5_sample_lo_fields\n+\t},\n+\t{\tTSM_CON6_CONFIG, 43, 10, REGISTER_TYPE_RW, 841, 3,\n+\t\ttsm_con6_config_fields\n+\t},\n+\t{\tTSM_CON6_SAMPLE_HI, 45, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con6_sample_hi_fields\n+\t},\n+\t{\tTSM_CON6_SAMPLE_LO, 44, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con6_sample_lo_fields\n+\t},\n+\t{\tTSM_CON7_HOST_SAMPLE_HI, 47, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con7_host_sample_hi_fields\n+\t},\n+\t{\tTSM_CON7_HOST_SAMPLE_LO, 46, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_con7_host_sample_lo_fields\n+\t},\n+\t{ TSM_CONFIG, 0, 13, REGISTER_TYPE_RW, 257, 6, tsm_config_fields },\n+\t{\tTSM_INT_CONFIG, 2, 20, REGISTER_TYPE_RW, 0, 2,\n+\t\ttsm_int_config_fields\n+\t},\n+\t{ TSM_INT_STAT, 3, 20, REGISTER_TYPE_MIXED, 0, 2, tsm_int_stat_fields },\n+\t{ TSM_LED, 4, 27, REGISTER_TYPE_RW, 16793600, 12, tsm_led_fields },\n+\t{\tTSM_NTTS_CONFIG, 13, 7, REGISTER_TYPE_RW, 32, 4,\n+\t\ttsm_ntts_config_fields\n+\t},\n+\t{\tTSM_NTTS_LIMIT_HI, 23, 16, REGISTER_TYPE_RW, 0, 1,\n+\t\ttsm_ntts_limit_hi_fields\n+\t},\n+\t{\tTSM_NTTS_LIMIT_LO, 22, 32, REGISTER_TYPE_RW, 100000, 1,\n+\t\ttsm_ntts_limit_lo_fields\n+\t},\n+\t{\tTSM_NTTS_OFFSET, 21, 30, REGISTER_TYPE_RW, 0, 1,\n+\t\ttsm_ntts_offset_fields\n+\t},\n+\t{\tTSM_NTTS_SAMPLE_HI, 19, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ntts_sample_hi_fields\n+\t},\n+\t{\tTSM_NTTS_SAMPLE_LO, 18, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ntts_sample_lo_fields\n+\t},\n+\t{ TSM_NTTS_STAT, 14, 17, REGISTER_TYPE_RO, 0, 3, tsm_ntts_stat_fields },\n+\t{\tTSM_NTTS_TS_T0_HI, 17, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ntts_ts_t0_hi_fields\n+\t},\n+\t{\tTSM_NTTS_TS_T0_LO, 16, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ntts_ts_t0_lo_fields\n+\t},\n+\t{\tTSM_NTTS_TS_T0_OFFSET, 20, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ntts_ts_t0_offset_fields\n+\t},\n+\t{ TSM_PB_CTRL, 63, 2, REGISTER_TYPE_WO, 0, 2, tsm_pb_ctrl_fields },\n+\t{\tTSM_PB_INSTMEM, 64, 32, REGISTER_TYPE_WO, 0, 2,\n+\t\ttsm_pb_instmem_fields\n+\t},\n+\t{ TSM_PI_CTRL_I, 54, 32, REGISTER_TYPE_WO, 0, 1, tsm_pi_ctrl_i_fields },\n+\t{\tTSM_PI_CTRL_KI, 52, 24, REGISTER_TYPE_RW, 0, 1,\n+\t\ttsm_pi_ctrl_ki_fields\n+\t},\n+\t{\tTSM_PI_CTRL_KP, 51, 24, REGISTER_TYPE_RW, 0, 1,\n+\t\ttsm_pi_ctrl_kp_fields\n+\t},\n+\t{\tTSM_PI_CTRL_SHL, 53, 4, REGISTER_TYPE_WO, 0, 1,\n+\t\ttsm_pi_ctrl_shl_fields\n+\t},\n+\t{ TSM_STAT, 1, 16, REGISTER_TYPE_RO, 0, 9, tsm_stat_fields },\n+\t{\tTSM_TIMER_CTRL, 48, 2, REGISTER_TYPE_RW, 0, 2,\n+\t\ttsm_timer_ctrl_fields\n+\t},\n+\t{\tTSM_TIMER_T0, 49, 30, REGISTER_TYPE_RW, 50000, 1,\n+\t\ttsm_timer_t0_fields\n+\t},\n+\t{\tTSM_TIMER_T1, 50, 30, REGISTER_TYPE_RW, 50000, 1,\n+\t\ttsm_timer_t1_fields\n+\t},\n+\t{\tTSM_TIME_HARDSET_HI, 12, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_time_hardset_hi_fields\n+\t},\n+\t{\tTSM_TIME_HARDSET_LO, 11, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_time_hardset_lo_fields\n+\t},\n+\t{ TSM_TIME_HI, 9, 32, REGISTER_TYPE_RW, 0, 1, tsm_time_hi_fields },\n+\t{ TSM_TIME_LO, 8, 32, REGISTER_TYPE_RW, 0, 1, tsm_time_lo_fields },\n+\t{\tTSM_TIME_RATE_ADJ, 10, 29, REGISTER_TYPE_RW, 0, 1,\n+\t\ttsm_time_rate_adj_fields\n+\t},\n+\t{ TSM_TS_HI, 6, 32, REGISTER_TYPE_RO, 0, 1, tsm_ts_hi_fields },\n+\t{ TSM_TS_LO, 5, 32, REGISTER_TYPE_RO, 0, 1, tsm_ts_lo_fields },\n+\t{ TSM_TS_OFFSET, 7, 30, REGISTER_TYPE_RW, 0, 1, tsm_ts_offset_fields },\n+\t{ TSM_TS_STAT, 55, 17, REGISTER_TYPE_RO, 0, 2, tsm_ts_stat_fields },\n+\t{\tTSM_TS_STAT_HI_OFFSET, 62, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ts_stat_hi_offset_fields\n+\t},\n+\t{\tTSM_TS_STAT_LO_OFFSET, 61, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ts_stat_lo_offset_fields\n+\t},\n+\t{\tTSM_TS_STAT_TAR_HI, 57, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ts_stat_tar_hi_fields\n+\t},\n+\t{\tTSM_TS_STAT_TAR_LO, 56, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ts_stat_tar_lo_fields\n+\t},\n+\t{ TSM_TS_STAT_X, 58, 32, REGISTER_TYPE_RO, 0, 1, tsm_ts_stat_x_fields },\n+\t{\tTSM_TS_STAT_X2_HI, 60, 16, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ts_stat_x2_hi_fields\n+\t},\n+\t{\tTSM_TS_STAT_X2_LO, 59, 32, REGISTER_TYPE_RO, 0, 1,\n+\t\ttsm_ts_stat_x2_lo_fields\n+\t},\n+\t{\tTSM_UTC_OFFSET, 65, 8, REGISTER_TYPE_RW, 0, 1,\n+\t\ttsm_utc_offset_fields\n+\t},\n+};\n+\n+static nt_fpga_module_init_t fpga_modules[] = {\n+\t{\tMOD_CAT, 0, MOD_CAT, 0, 21, BUS_TYPE_RAB1, 768, 34,\n+\t\tcat_registers\n+\t}, /* CAT:0 CAT v0.21: CAT @ RAB1,768 (CAT CAT CAT) */\n+\t{\tMOD_CSU, 0, MOD_CSU, 0, 0, BUS_TYPE_RAB1, 9728, 2,\n+\t\tcsu_registers\n+\t}, /* CSU:0 CSU v0.0: CSU @ RAB1,9728 (CSU CSU CSU) */\n+\t{\tMOD_DBS, 0, MOD_DBS, 0, 11, BUS_TYPE_RAB2, 12832, 27,\n+\t\tdbs_registers\n+\t}, /* DBS:0 DBS v0.11: DBS @ RAB2,12832 (DBS DBS DBS) */\n+\t{\tMOD_FLM, 0, MOD_FLM, 0, 20, BUS_TYPE_RAB1, 1280, 43,\n+\t\tflm_registers\n+\t}, /* FLM:0 FLM v0.20: FLM @ RAB1,1280 (FLM FLM FLM) */\n+\t{\tMOD_GFG, 0, MOD_GFG, 1, 1, BUS_TYPE_RAB2, 8704, 10,\n+\t\tgfg_registers\n+\t}, /* GFG:0 GFG v1.1: GFG @ RAB2,8704 (GFG GFG GFG) */\n+\t{\tMOD_GMF, 0, MOD_GMF, 2, 5, BUS_TYPE_RAB2, 9216, 12,\n+\t\tgmf_registers\n+\t}, /* GMF:0 GMF v2.5: GMF_0 @ RAB2,9216 (GMF GMF_0 GMF) */\n+\t{\tMOD_GMF, 1, MOD_GMF, 2, 5, BUS_TYPE_RAB2, 9728, 12,\n+\t\tgmf_registers\n+\t}, /* GMF:1 GMF v2.5: GMF_1 @ RAB2,9728 (GMF GMF_1 GMF) */\n+\t{\tMOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0, BUS_TYPE_RAB0, 16386, 2,\n+\t\tgpio_phy_registers\n+\t}, /* GPIO_PHY:0 GPIO_PHY v1.0: GPIO_PHY @ RAB0,16386 (GPIO_PHY GPIO_PHY GPIO_PHY) */\n+\t{\tMOD_HFU, 0, MOD_HFU, 0, 1, BUS_TYPE_RAB1, 9472, 2,\n+\t\thfu_registers\n+\t}, /* HFU:0 HFU v0.1: HFU @ RAB1,9472 (HFU HFU HFU) */\n+\t{\tMOD_HIF, 0, MOD_HIF, 0, 0, BUS_TYPE_PCI, 0, 18,\n+\t\thif_registers\n+\t}, /* HIF:0 HIF v0.0: HIF @ PCI,0 (HIF HIF HIF) */\n+\t{\tMOD_HSH, 0, MOD_HSH, 0, 5, BUS_TYPE_RAB1, 1536, 2,\n+\t\thsh_registers\n+\t}, /* HSH:0 HSH v0.5: HSH @ RAB1,1536 (HSH HSH HSH) */\n+\t{\tMOD_HST, 0, MOD_HST, 0, 2, BUS_TYPE_RAB1, 2048, 2,\n+\t\thst_registers\n+\t}, /* HST:0 HST v0.2: HST @ RAB1,2048 (HST HST HST) */\n+\t{\tMOD_IFR, 0, MOD_IFR, 0, 1, BUS_TYPE_RAB1, 9984, 2,\n+\t\tifr_registers\n+\t}, /* IFR:0 IFR v0.1: IFR @ RAB1,9984 (IFR IFR IFR) */\n+\t{\tMOD_IIC, 0, MOD_IIC, 0, 1, BUS_TYPE_RAB0, 768, 22,\n+\t\tiic_registers\n+\t}, /* IIC:0 IIC v0.1: IIC0 @ RAB0,768 (IIC IIC0 IIC) */\n+\t{\tMOD_IIC, 1, MOD_IIC, 0, 1, BUS_TYPE_RAB0, 896, 22,\n+\t\tiic_registers\n+\t}, /* IIC:1 IIC v0.1: IIC1 @ RAB0,896 (IIC IIC1 IIC) */\n+\t{\tMOD_IIC, 2, MOD_IIC, 0, 1, BUS_TYPE_RAB0, 24832, 22,\n+\t\tiic_registers\n+\t}, /* IIC:2 IIC v0.1: IIC2 @ RAB0,24832 (IIC IIC2 IIC) */\n+\t{\tMOD_IIC, 3, MOD_IIC, 0, 1, BUS_TYPE_RAB0, 24960, 22,\n+\t\tiic_registers\n+\t}, /* IIC:3 IIC v0.1: IIC3 @ RAB0,24960 (IIC IIC3 IIC) */\n+\t{\tMOD_KM, 0, MOD_KM, 0, 7, BUS_TYPE_RAB1, 1024, 11,\n+\t\tkm_registers\n+\t}, /* KM:0 KM v0.7: KM @ RAB1,1024 (KM KM KM) */\n+\t{\tMOD_MAC_PCS, 0, MOD_MAC_PCS, 0, 2, BUS_TYPE_RAB2, 10240, 44,\n+\t\tmac_pcs_registers\n+\t}, /* MAC_PCS:0 MAC_PCS v0.2: MAC_PCS_0 @ RAB2,10240 (MAC_PCS MAC_PCS_0 MAC_PCS) */\n+\t{\tMOD_MAC_PCS, 1, MOD_MAC_PCS, 0, 2, BUS_TYPE_RAB2, 11776, 44,\n+\t\tmac_pcs_registers\n+\t}, /* MAC_PCS:1 MAC_PCS v0.2: MAC_PCS_1 @ RAB2,11776 (MAC_PCS MAC_PCS_1 MAC_PCS) */\n+\t{\tMOD_MAC_RX, 0, MOD_MAC_RX, 0, 0, BUS_TYPE_RAB2, 10752, 9,\n+\t\tmac_rx_registers\n+\t}, /* MAC_RX:0 MAC_RX v0.0: MAC_RX_0 @ RAB2,10752 (MAC_RX MAC_RX_0 MAC_RX) */\n+\t{\tMOD_MAC_RX, 1, MOD_MAC_RX, 0, 0, BUS_TYPE_RAB2, 12288, 9,\n+\t\tmac_rx_registers\n+\t}, /* MAC_RX:1 MAC_RX v0.0: MAC_RX_1 @ RAB2,12288 (MAC_RX MAC_RX_1 MAC_RX) */\n+\t{\tMOD_MAC_TX, 0, MOD_MAC_TX, 0, 0, BUS_TYPE_RAB2, 11264, 5,\n+\t\tmac_tx_registers\n+\t}, /* MAC_TX:0 MAC_TX v0.0: MAC_TX_0 @ RAB2,11264 (MAC_TX MAC_TX_0 MAC_TX) */\n+\t{\tMOD_MAC_TX, 1, MOD_MAC_TX, 0, 0, BUS_TYPE_RAB2, 12800, 5,\n+\t\tmac_tx_registers\n+\t}, /* MAC_TX:1 MAC_TX v0.0: MAC_TX_1 @ RAB2,12800 (MAC_TX MAC_TX_1 MAC_TX) */\n+\t{\tMOD_PCI_RD_TG, 0, MOD_PCI_RD_TG, 0, 1, BUS_TYPE_RAB0, 2320, 6,\n+\t\tpci_rd_tg_registers\n+\t}, /* PCI_RD_TG:0 PCI_RD_TG v0.1: PCI_RD_TG @ RAB0,2320 (PCI_RD_TG PCI_RD_TG PCI_RD_TG) */\n+\t{\tMOD_PCI_TA, 0, MOD_PCI_TA, 0, 0, BUS_TYPE_RAB0, 2336, 5,\n+\t\tpci_ta_registers\n+\t}, /* PCI_TA:0 PCI_TA v0.0: PCI_TA @ RAB0,2336 (PCI_TA PCI_TA PCI_TA) */\n+\t{\tMOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1, BUS_TYPE_RAB0, 2304, 7,\n+\t\tpci_wr_tg_registers\n+\t}, /* PCI_WR_TG:0 PCI_WR_TG v0.1: PCI_WR_TG @ RAB0,2304 (PCI_WR_TG PCI_WR_TG PCI_WR_TG) */\n+\t{\tMOD_PDB, 0, MOD_PDB, 0, 9, BUS_TYPE_RAB1, 2816, 3,\n+\t\tpdb_registers\n+\t}, /* PDB:0 PDB v0.9: PDB @ RAB1,2816 (PDB PDB PDB) */\n+\t{\tMOD_PDI, 0, MOD_PDI, 1, 1, BUS_TYPE_RAB0, 64, 6,\n+\t\tpdi_registers\n+\t}, /* PDI:0 PDI v1.1: PDI @ RAB0,64 (PDI PDI PDI) */\n+\t{\tMOD_PTP1588, 0, MOD_PTP1588, 2, 1, BUS_TYPE_RAB2, 512, 23,\n+\t\tptp1588_registers\n+\t}, /* PTP1588:0 PTP1588 v2.1: PTP1588 @ RAB2,512 (PTP1588 PTP1588 PTP1588) */\n+\t{\tMOD_QSL, 0, MOD_QSL, 0, 7, BUS_TYPE_RAB1, 1792, 8,\n+\t\tqsl_registers\n+\t}, /* QSL:0 QSL v0.7: QSL @ RAB1,1792 (QSL QSL QSL) */\n+\t{\tMOD_QSPI, 0, MOD_QSPI, 0, 0, BUS_TYPE_RAB0, 512, 11,\n+\t\tqspi_registers\n+\t}, /* QSPI:0 QSPI v0.0: QSPI @ RAB0,512 (QSPI QSPI QSPI) */\n+\t{\tMOD_RAC, 0, MOD_RAC, 3, 0, BUS_TYPE_PCI, 8192, 14,\n+\t\trac_registers\n+\t}, /* RAC:0 RAC v3.0: RAC @ PCI,8192 (RAC RAC RAC) */\n+\t{\tMOD_RFD, 0, MOD_RFD, 0, 4, BUS_TYPE_RAB1, 256, 5,\n+\t\trfd_registers\n+\t}, /* RFD:0 RFD v0.4: RFD @ RAB1,256 (RFD RFD RFD) */\n+\t{\tMOD_RMC, 0, MOD_RMC, 1, 3, BUS_TYPE_RAB0, 12288, 4,\n+\t\trmc_registers\n+\t}, /* RMC:0 RMC v1.3: RMC @ RAB0,12288 (RMC RMC RMC) */\n+\t{\tMOD_RPP_LR, 0, MOD_RPP_LR, 0, 1, BUS_TYPE_RAB1, 2560, 4,\n+\t\trpp_lr_registers\n+\t}, /* RPP_LR:0 RPP_LR v0.1: RPP_LR @ RAB1,2560 (RPP_LR RPP_LR RPP_LR) */\n+\t{\tMOD_RST9563, 0, MOD_RST9563, 0, 5, BUS_TYPE_RAB0, 1024, 5,\n+\t\trst9563_registers\n+\t}, /* RST9563:0 RST9563 v0.5: RST9563 @ RAB0,1024 (RST9563 RST9563 RST9563) */\n+\t{\tMOD_SLC_LR, 0, MOD_SLC, 0, 2, BUS_TYPE_RAB1, 2304, 2,\n+\t\tslc_registers\n+\t}, /* SLC_LR:0 SLC v0.2: SLC_LR @ RAB1,2304 (SLC SLC_LR SLC_LR) */\n+\t{\tMOD_SPIM, 0, MOD_SPIM, 1, 0, BUS_TYPE_RAB0, 80, 6,\n+\t\tspim_registers\n+\t}, /* SPIM:0 SPIM v1.0: SPIM @ RAB0,80 (SPIM SPIM SPIM) */\n+\t{\tMOD_SPIS, 0, MOD_SPIS, 1, 0, BUS_TYPE_RAB0, 256, 7,\n+\t\tspis_registers\n+\t}, /* SPIS:0 SPIS v1.0: SPIS @ RAB0,256 (SPIS SPIS SPIS) */\n+\t{\tMOD_STA, 0, MOD_STA, 0, 8, BUS_TYPE_RAB0, 2048, 8,\n+\t\tsta_registers\n+\t}, /* STA:0 STA v0.8: STA @ RAB0,2048 (STA STA STA) */\n+\t{\tMOD_TEMPMON, 0, MOD_TEMPMON, 0, 0, BUS_TYPE_RAB0, 16384, 2,\n+\t\ttempmon_registers\n+\t}, /* TEMPMON:0 TEMPMON v0.0: TEMPMON @ RAB0,16384 (TEMPMON TEMPMON TEMPMON) */\n+\t{\tMOD_TINT, 0, MOD_TINT, 0, 0, BUS_TYPE_RAB0, 1280, 2,\n+\t\ttint_registers\n+\t}, /* TINT:0 TINT v0.0: TINT @ RAB0,1280 (TINT TINT TINT) */\n+\t{\tMOD_TMC, 0, MOD_TMC, 0, 1, BUS_TYPE_RAB2, 8192, 1,\n+\t\ttmc_registers\n+\t}, /* TMC:0 TMC v0.1: TMC @ RAB2,8192 (TMC TMC TMC) */\n+\t{\tMOD_TSM, 0, MOD_TSM, 0, 8, BUS_TYPE_RAB2, 1024, 66,\n+\t\ttsm_registers\n+\t}, /* TSM:0 TSM v0.8: TSM @ RAB2,1024 (TSM TSM TSM) */\n+\t{\tMOD_TX_CPY, 0, MOD_CPY, 0, 1, BUS_TYPE_RAB1, 9216, 20,\n+\t\tcpy_registers\n+\t}, /* TX_CPY:0 CPY v0.1: TX_CPY @ RAB1,9216 (CPY TX_CPY TX_CPY) */\n+\t{\tMOD_TX_INS, 0, MOD_INS, 0, 1, BUS_TYPE_RAB1, 8704, 2,\n+\t\tins_registers\n+\t}, /* TX_INS:0 INS v0.1: TX_INS @ RAB1,8704 (INS TX_INS TX_INS) */\n+\t{\tMOD_TX_RPL, 0, MOD_RPL, 0, 2, BUS_TYPE_RAB1, 8960, 6,\n+\t\trpl_registers\n+\t}, /* TX_RPL:0 RPL v0.2: TX_RPL @ RAB1,8960 (RPL TX_RPL TX_RPL) */\n+};\n+\n+static nt_fpga_prod_param_t product_parameters[] = {\n+\t{ NT_BUILD_NUMBER, 0 },\n+\t{ NT_BUILD_TIME, 1693228548 },\n+\t{ NT_CATEGORIES, 64 },\n+\t{ NT_CAT_DCT_PRESENT, 0 },\n+\t{ NT_CAT_END_OFS_SUPPORT, 0 },\n+\t{ NT_CAT_FUNCS, 64 },\n+\t{ NT_CAT_KCC_BANKS, 3 },\n+\t{ NT_CAT_KCC_PRESENT, 0 },\n+\t{ NT_CAT_KCC_SIZE, 1536 },\n+\t{ NT_CAT_KM_IF_CNT, 2 },\n+\t{ NT_CAT_KM_IF_M0, 0 },\n+\t{ NT_CAT_KM_IF_M1, 1 },\n+\t{ NT_CAT_N_CMP, 8 },\n+\t{ NT_CAT_N_EXT, 4 },\n+\t{ NT_CAT_N_LEN, 8 },\n+\t{ NT_CB_DEBUG, 0 },\n+\t{ NT_COR_CATEGORIES, 16 },\n+\t{ NT_COR_PRESENT, 0 },\n+\t{ NT_CSU_PRESENT, 1 },\n+\t{ NT_DBS_PRESENT, 1 },\n+\t{ NT_DBS_RX_QUEUES, 128 },\n+\t{ NT_DBS_TX_PORTS, 2 },\n+\t{ NT_DBS_TX_QUEUES, 128 },\n+\t{ NT_DDP_PRESENT, 0 },\n+\t{ NT_DDP_TBL_DEPTH, 4096 },\n+\t{ NT_EMI_SPLIT_STEPS, 16 },\n+\t{ NT_EOF_TIMESTAMP_ONLY, 1 },\n+\t{ NT_EPP_CATEGORIES, 32 },\n+\t{ NT_FLM_CACHE, 1 },\n+\t{ NT_FLM_CATEGORIES, 32 },\n+\t{ NT_FLM_ENTRY_SIZE, 64 },\n+\t{ NT_FLM_PRESENT, 1 },\n+\t{ NT_FLM_PRIOS, 4 },\n+\t{ NT_FLM_PST_PROFILES, 16 },\n+\t{ NT_FLM_SIZE_MB, 12288 },\n+\t{ NT_FLM_STATEFUL, 1 },\n+\t{ NT_FLM_VARIANT, 2 },\n+\t{ NT_GFG_PRESENT, 1 },\n+\t{ NT_GFG_TX_LIVE_RECONFIG_SUPPORT, 1 },\n+\t{ NT_GMF_FCS_PRESENT, 0 },\n+\t{ NT_GMF_IFG_SPEED_DIV, 33 },\n+\t{ NT_GMF_IFG_SPEED_DIV100G, 33 },\n+\t{ NT_GMF_IFG_SPEED_MUL, 20 },\n+\t{ NT_GMF_IFG_SPEED_MUL100G, 20 },\n+\t{ NT_GROUP_ID, 9563 },\n+\t{ NT_HFU_PRESENT, 1 },\n+\t{ NT_HIF_MSIX_BAR, 1 },\n+\t{ NT_HIF_MSIX_PBA_OFS, 8192 },\n+\t{ NT_HIF_MSIX_PRESENT, 1 },\n+\t{ NT_HIF_MSIX_TBL_OFS, 0 },\n+\t{ NT_HIF_MSIX_TBL_SIZE, 8 },\n+\t{ NT_HIF_PER_PS, 4000 },\n+\t{ NT_HIF_SRIOV_PRESENT, 1 },\n+\t{ NT_HSH_CATEGORIES, 16 },\n+\t{ NT_HSH_TOEPLITZ, 1 },\n+\t{ NT_HST_CATEGORIES, 32 },\n+\t{ NT_HST_PRESENT, 1 },\n+\t{ NT_IOA_CATEGORIES, 1024 },\n+\t{ NT_IOA_PRESENT, 0 },\n+\t{ NT_IPF_PRESENT, 0 },\n+\t{ NT_KM_CAM_BANKS, 3 },\n+\t{ NT_KM_CAM_RECORDS, 2048 },\n+\t{ NT_KM_CAM_REC_WORDS, 6 },\n+\t{ NT_KM_CATEGORIES, 32 },\n+\t{ NT_KM_END_OFS_SUPPORT, 0 },\n+\t{ NT_KM_EXT_EXTRACTORS, 0 },\n+\t{ NT_KM_FLOW_TYPES, 16 },\n+\t{ NT_KM_PRESENT, 1 },\n+\t{ NT_KM_SWX_PRESENT, 0 },\n+\t{ NT_KM_SYNERGY_MATCH, 0 },\n+\t{ NT_KM_TCAM_BANKS, 12 },\n+\t{ NT_KM_TCAM_BANK_WIDTH, 72 },\n+\t{ NT_KM_TCAM_HIT_QUAL, 0 },\n+\t{ NT_KM_TCAM_KEYWAY, 1 },\n+\t{ NT_KM_WIDE, 1 },\n+\t{ NT_LR_PRESENT, 1 },\n+\t{ NT_MCU_PRESENT, 0 },\n+\t{ NT_MDG_DEBUG_FLOW_CONTROL, 0 },\n+\t{ NT_MDG_DEBUG_REG_READ_BACK, 0 },\n+\t{ NT_MSK_CATEGORIES, 32 },\n+\t{ NT_MSK_PRESENT, 0 },\n+\t{ NT_NFV_OVS_PRODUCT, 0 },\n+\t{ NT_NIMS, 2 },\n+\t{ NT_PCI_DEVICE_ID, 453 },\n+\t{ NT_PCI_TA_TG_PRESENT, 1 },\n+\t{ NT_PCI_VENDOR_ID, 6388 },\n+\t{ NT_PDB_CATEGORIES, 16 },\n+\t{ NT_PHY_ANEG_PRESENT, 0 },\n+\t{ NT_PHY_KRFEC_PRESENT, 0 },\n+\t{ NT_PHY_PORTS, 2 },\n+\t{ NT_PHY_PORTS_PER_QUAD, 1 },\n+\t{ NT_PHY_QUADS, 2 },\n+\t{ NT_PHY_RSFEC_PRESENT, 1 },\n+\t{ NT_QM_CELLS, 2097152 },\n+\t{ NT_QM_CELL_SIZE, 6144 },\n+\t{ NT_QM_PRESENT, 0 },\n+\t{ NT_QSL_CATEGORIES, 32 },\n+\t{ NT_QSL_COLOR_SEL_BW, 7 },\n+\t{ NT_QSL_QST_SIZE, 4096 },\n+\t{ NT_QUEUES, 128 },\n+\t{ NT_RAC_RAB_INTERFACES, 3 },\n+\t{ NT_RAC_RAB_OB_UPDATE, 0 },\n+\t{ NT_REVISION_ID, 24 },\n+\t{ NT_RMC_LAG_GROUPS, 1 },\n+\t{ NT_ROA_CATEGORIES, 1024 },\n+\t{ NT_ROA_PRESENT, 0 },\n+\t{ NT_RPP_PER_PS, 3333 },\n+\t{ NT_RTX_PRESENT, 0 },\n+\t{ NT_RX_HOST_BUFFERS, 128 },\n+\t{ NT_RX_PORTS, 2 },\n+\t{ NT_RX_PORT_REPLICATE, 0 },\n+\t{ NT_SLB_PRESENT, 0 },\n+\t{ NT_SLC_LR_PRESENT, 1 },\n+\t{ NT_STA_COLORS, 64 },\n+\t{ NT_STA_RX_PORTS, 2 },\n+\t{ NT_TBH_DEBUG_DLN, 1 },\n+\t{ NT_TBH_PRESENT, 0 },\n+\t{ NT_TFD_PRESENT, 1 },\n+\t{ NT_TPE_CATEGORIES, 16 },\n+\t{ NT_TSM_OST_ONLY, 0 },\n+\t{ NT_TS_APPEND, 0 },\n+\t{ NT_TS_INJECT_PRESENT, 0 },\n+\t{ NT_TX_CPY_PACKET_READERS, 0 },\n+\t{ NT_TX_CPY_PRESENT, 1 },\n+\t{ NT_TX_CPY_SIDEBAND_READERS, 6 },\n+\t{ NT_TX_CPY_VARIANT, 0 },\n+\t{ NT_TX_CPY_WRITERS, 5 },\n+\t{ NT_TX_HOST_BUFFERS, 128 },\n+\t{ NT_TX_INS_PRESENT, 1 },\n+\t{ NT_TX_MTU_PROFILE_IFR, 16 },\n+\t{ NT_TX_ON_TIMESTAMP, 1 },\n+\t{ NT_TX_PORTS, 2 },\n+\t{ NT_TX_PORT_REPLICATE, 1 },\n+\t{ NT_TX_RPL_DEPTH, 4096 },\n+\t{ NT_TX_RPL_EXT_CATEGORIES, 1024 },\n+\t{ NT_TX_RPL_PRESENT, 1 },\n+\t{ NT_TYPE_ID, 200 },\n+\t{ NT_USE_TRIPLE_SPEED, 0 },\n+\t{ NT_VERSION_ID, 55 },\n+\t{ NT_VLI_PRESENT, 0 },\n+\t{ 0, -1 }, /* END */\n+};\n+\n+nt_fpga_prod_init_t nthw_fpga_9563_055_024_0000 = {\n+\t200, /* fpgaTypeId */\n+\t9563, /* fpga_product_id */\n+\t55, /* fpga_version */\n+\t24, /* fpga_revision */\n+\t0, /* fpga_patch_no */\n+\t0, /* fpga_build_no */\n+\t1693228548, /* fpga_build_time */\n+\t140,\t product_parameters, 48, fpga_modules,\n+};\ndiff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h\nnew file mode 100644\nindex 0000000000..1d707d6925\n--- /dev/null\n+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Napatech A/S\n+ */\n+\n+#ifndef NTHW_FPGA_INSTANCES_H\n+#define NTHW_FPGA_INSTANCES_H\n+\n+#include \"fpga_model.h\"\n+\n+extern nt_fpga_prod_init_t *nthw_fpga_instances[];\n+\n+extern nt_fpga_prod_init_t nthw_fpga_9563_055_024_0000;\n+\n+#endif /* NTHW_FPGA_INSTANCES_H */\ndiff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_modules_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_modules_defs.h\nnew file mode 100644\nindex 0000000000..38a15bec87\n--- /dev/null\n+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_modules_defs.h\n@@ -0,0 +1,166 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Napatech A/S\n+ */\n+\n+#ifndef _NTHW_FPGA_MODULES_DEFS_H_\n+#define _NTHW_FPGA_MODULES_DEFS_H_\n+\n+/* Unknown/uninitialized - keep this as the first element */\n+#define MOD_UNKNOWN (0L)\n+#define MOD_CAT (1L)\n+#define MOD_CB (2L)\n+#define MOD_CCIP (3L)\n+#define MOD_CFP4_CTRL_GBOX (4L)\n+#define MOD_COR (5L)\n+#define MOD_CPY (6L)\n+#define MOD_CSU (7L)\n+#define MOD_DBS (8L)\n+#define MOD_DDP (9L)\n+#define MOD_EPP (10L)\n+#define MOD_EQM (11L)\n+#define MOD_FHM (12L)\n+#define MOD_FLM (13L)\n+#define MOD_GFG (14L)\n+#define MOD_GMF (15L)\n+#define MOD_GPIO_PHY (16L)\n+#define MOD_GPIO_PHY_PORTS (17L)\n+#define MOD_GPIO_SFPP (18L)\n+#define MOD_HFU (19L)\n+#define MOD_HIF (20L)\n+#define MOD_HSH (21L)\n+#define MOD_HST (22L)\n+#define MOD_ICORE_10G (23L)\n+#define MOD_IFR (24L)\n+#define MOD_IIC (25L)\n+#define MOD_INS (26L)\n+#define MOD_IOA (27L)\n+#define MOD_IPF (28L)\n+#define MOD_KM (29L)\n+#define MOD_LAO (30L)\n+#define MOD_MAC (31L)\n+#define MOD_MAC100 (33L)\n+#define MOD_MAC10G (34L)\n+#define MOD_MAC1G (35L)\n+#define MOD_MAC_PCS (36L)\n+#define MOD_MAC_PCS_XXV (37L)\n+#define MOD_MAC_RX (38L)\n+#define MOD_MAC_TFG (39L)\n+#define MOD_MAC_TX (40L)\n+#define MOD_MCU (41L)\n+#define MOD_MDG (42L)\n+#define MOD_MSK (43L)\n+#define MOD_NIF (44L)\n+#define MOD_PCIE3 (45L)\n+#define MOD_PCI_RD_TG (46L)\n+#define MOD_PCI_TA (47L)\n+#define MOD_PCI_WR_TG (48L)\n+#define MOD_PCM_NT100A01_01 (49L)\n+#define MOD_PCM_NT50B01_01 (50L)\n+#define MOD_PCS (51L)\n+#define MOD_PCS100 (52L)\n+#define MOD_PDB (53L)\n+#define MOD_PDI (54L)\n+#define MOD_PHY10G (55L)\n+#define MOD_PHY3S10G (56L)\n+#define MOD_PM (57L)\n+#define MOD_PRM_NT100A01_01 (58L)\n+#define MOD_PRM_NT50B01_01 (59L)\n+#define MOD_PTP1588 (60L)\n+#define MOD_QM (61L)\n+#define MOD_QSL (62L)\n+#define MOD_QSPI (63L)\n+#define MOD_R2DRP (64L)\n+#define MOD_RAC (65L)\n+#define MOD_RBH (66L)\n+#define MOD_RFD (67L)\n+#define MOD_RMC (68L)\n+#define MOD_RNTC (69L)\n+#define MOD_ROA (70L)\n+#define MOD_RPL (71L)\n+#define MOD_RPP_LR (72L)\n+#define MOD_RST7000 (73L)\n+#define MOD_RST7001 (74L)\n+#define MOD_RST9500 (75L)\n+#define MOD_RST9501 (76L)\n+#define MOD_RST9502 (77L)\n+#define MOD_RST9503 (78L)\n+#define MOD_RST9504 (79L)\n+#define MOD_RST9505 (80L)\n+#define MOD_RST9506 (81L)\n+#define MOD_RST9507 (82L)\n+#define MOD_RST9508 (83L)\n+#define MOD_RST9509 (84L)\n+#define MOD_RST9510 (85L)\n+#define MOD_RST9512 (86L)\n+#define MOD_RST9513 (87L)\n+#define MOD_RST9515 (88L)\n+#define MOD_RST9516 (89L)\n+#define MOD_RST9517 (90L)\n+#define MOD_RST9519 (91L)\n+#define MOD_RST9520 (92L)\n+#define MOD_RST9521 (93L)\n+#define MOD_RST9522 (94L)\n+#define MOD_RST9523 (95L)\n+#define MOD_RST9524 (96L)\n+#define MOD_RST9525 (97L)\n+#define MOD_RST9526 (98L)\n+#define MOD_RST9527 (99L)\n+#define MOD_RST9528 (100L)\n+#define MOD_RST9529 (101L)\n+#define MOD_RST9530 (102L)\n+#define MOD_RST9531 (103L)\n+#define MOD_RST9532 (104L)\n+#define MOD_RST9533 (105L)\n+#define MOD_RST9534 (106L)\n+#define MOD_RST9535 (107L)\n+#define MOD_RST9536 (108L)\n+#define MOD_RST9537 (109L)\n+#define MOD_RST9538 (110L)\n+#define MOD_RST9539 (111L)\n+#define MOD_RST9540 (112L)\n+#define MOD_RST9541 (113L)\n+#define MOD_RST9542 (114L)\n+#define MOD_RST9543 (115L)\n+#define MOD_RST9544 (116L)\n+#define MOD_RST9545 (117L)\n+#define MOD_RST9546 (118L)\n+#define MOD_RST9547 (119L)\n+#define MOD_RST9548 (120L)\n+#define MOD_RST9549 (121L)\n+#define MOD_RST9553 (122L)\n+#define MOD_RST9555 (123L)\n+#define MOD_RST9559 (124L)\n+#define MOD_RST9563 (125L)\n+#define MOD_RTD (126L)\n+#define MOD_RTD_HMP (127L)\n+#define MOD_RTX (128L)\n+#define MOD_SDC (129L)\n+#define MOD_SLC (130L)\n+#define MOD_SLC_LR (131L)\n+#define MOD_SMM (132L)\n+#define MOD_SMM_RX (133L)\n+#define MOD_SMM_TX (134L)\n+#define MOD_SPIM (135L)\n+#define MOD_SPIS (136L)\n+#define MOD_STA (137L)\n+#define MOD_TBH (138L)\n+#define MOD_TEMPMON (139L)\n+#define MOD_TINT (140L)\n+#define MOD_TMC (141L)\n+#define MOD_TSM (142L)\n+#define MOD_TX_CPY (143L)\n+#define MOD_TX_CSI (144L)\n+#define MOD_TX_CSO (145L)\n+#define MOD_TX_INS (146L)\n+#define MOD_TX_RPL (147L)\n+/*\n+ * NOTE: Keep this as the last element!\n+ * End indicator - keep this as the last element - only aliases go below this point\n+ */\n+#define MOD_UNKNOWN_MAX (148L)\n+/* End indicator - keep this as the last element - only aliases go below this point */\n+#define MOD_COUNT_MAX (148L)\n+/* aliases */\n+#define MOD_MAC10 (MOD_MAC10G) /* alias */\n+\n+#endif /* _NTHW_FPGA_MODULES_DEFS_H_ */\ndiff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_parameters_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_parameters_defs.h\nnew file mode 100644\nindex 0000000000..b6187a257f\n--- /dev/null\n+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_parameters_defs.h\n@@ -0,0 +1,209 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Napatech A/S\n+ */\n+\n+#ifndef _NTHW_FPGA_PARAMETERS_DEFS_\n+#define _NTHW_FPGA_PARAMETERS_DEFS_\n+\n+#define NT_PARAM_UNKNOWN (0L)\n+#define NT_BUILD_NUMBER (1L)\n+#define NT_BUILD_TIME (2L)\n+#define NT_CATEGORIES (3L)\n+#define NT_CAT_CCT_SIZE (4L)\n+#define NT_CAT_CTE_SIZE (5L)\n+#define NT_CAT_CTS_SIZE (6L)\n+#define NT_CAT_DCT_PRESENT (7L)\n+#define NT_CAT_DCT_SIZE (8L)\n+#define NT_CAT_END_OFS_SUPPORT (9L)\n+#define NT_CAT_FPC (10L)\n+#define NT_CAT_FTE_SIZE (11L)\n+#define NT_CAT_FUNCS (12L)\n+#define NT_CAT_KCC_BANKS (13L)\n+#define NT_CAT_KCC_PRESENT (14L)\n+#define NT_CAT_KCC_SIZE (15L)\n+#define NT_CAT_KCE_SIZE (16L)\n+#define NT_CAT_KM_IF_CNT (17L)\n+#define NT_CAT_KM_IF_M0 (18L)\n+#define NT_CAT_KM_IF_M1 (19L)\n+#define NT_CAT_N_CMP (20L)\n+#define NT_CAT_N_EXT (21L)\n+#define NT_CAT_N_LEN (22L)\n+#define NT_CAT_RCK_SIZE (23L)\n+#define NT_CAT_VALUES (24L)\n+#define NT_CB_DEBUG (25L)\n+#define NT_COR_CATEGORIES (26L)\n+#define NT_COR_PRESENT (27L)\n+#define NT_CPY_MASK_MEM (28L)\n+#define NT_CSU_PRESENT (29L)\n+#define NT_DBS_PRESENT (30L)\n+#define NT_DBS_RX_QUEUES (31L)\n+#define NT_DBS_TX_PORTS (32L)\n+#define NT_DBS_TX_QUEUES (33L)\n+#define NT_DDP_PRESENT (34L)\n+#define NT_DDP_TBL_DEPTH (35L)\n+#define NT_EMI_SPLIT_STEPS (36L)\n+#define NT_EOF_TIMESTAMP_ONLY (37L)\n+#define NT_EPP_CATEGORIES (38L)\n+#define NT_EXT_MEM_NUM (39L)\n+#define NT_EXT_MEM_SINGLE_SIZE_GB (40L)\n+#define NT_FLM_CACHE (41L)\n+#define NT_FLM_CATEGORIES (42L)\n+#define NT_FLM_ENTRY_SIZE (43L)\n+#define NT_FLM_PRESENT (44L)\n+#define NT_FLM_PRIOS (45L)\n+#define NT_FLM_PST_PROFILES (46L)\n+#define NT_FLM_SIZE_MB (47L)\n+#define NT_FLM_STATEFUL (48L)\n+#define NT_FLM_VARIANT (49L)\n+#define NT_GFG_PRESENT (50L)\n+#define NT_GFG_TX_LIVE_RECONFIG_SUPPORT (51L)\n+#define NT_GMF_FCS_PRESENT (52L)\n+#define NT_GMF_IFG_SPEED_DIV (53L)\n+#define NT_GMF_IFG_SPEED_DIV100G (54L)\n+#define NT_GMF_IFG_SPEED_DIV100M (55L)\n+#define NT_GMF_IFG_SPEED_DIV10G (56L)\n+#define NT_GMF_IFG_SPEED_DIV1G (57L)\n+#define NT_GMF_IFG_SPEED_DIV2 (58L)\n+#define NT_GMF_IFG_SPEED_DIV25G (59L)\n+#define NT_GMF_IFG_SPEED_DIV3 (60L)\n+#define NT_GMF_IFG_SPEED_DIV4 (61L)\n+#define NT_GMF_IFG_SPEED_DIV40G (62L)\n+#define NT_GMF_IFG_SPEED_DIV50G (63L)\n+#define NT_GMF_IFG_SPEED_MUL (64L)\n+#define NT_GMF_IFG_SPEED_MUL100G (65L)\n+#define NT_GMF_IFG_SPEED_MUL100M (66L)\n+#define NT_GMF_IFG_SPEED_MUL10G (67L)\n+#define NT_GMF_IFG_SPEED_MUL1G (68L)\n+#define NT_GMF_IFG_SPEED_MUL2 (69L)\n+#define NT_GMF_IFG_SPEED_MUL25G (70L)\n+#define NT_GMF_IFG_SPEED_MUL3 (71L)\n+#define NT_GMF_IFG_SPEED_MUL4 (72L)\n+#define NT_GMF_IFG_SPEED_MUL40G (73L)\n+#define NT_GMF_IFG_SPEED_MUL50G (74L)\n+#define NT_GROUP_ID (75L)\n+#define NT_HFU_PRESENT (76L)\n+#define NT_HIF_MSIX_BAR (77L)\n+#define NT_HIF_MSIX_PBA_OFS (78L)\n+#define NT_HIF_MSIX_PRESENT (79L)\n+#define NT_HIF_MSIX_TBL_OFS (80L)\n+#define NT_HIF_MSIX_TBL_SIZE (81L)\n+#define NT_HIF_PER_PS (82L)\n+#define NT_HIF_SRIOV_PRESENT (83L)\n+#define NT_HSH_CATEGORIES (84L)\n+#define NT_HSH_TOEPLITZ (85L)\n+#define NT_HST_CATEGORIES (86L)\n+#define NT_HST_PRESENT (87L)\n+#define NT_IOA_CATEGORIES (88L)\n+#define NT_IOA_PRESENT (89L)\n+#define NT_IPF_PRESENT (90L)\n+#define NT_KM_CAM_BANKS (91L)\n+#define NT_KM_CAM_RECORDS (92L)\n+#define NT_KM_CAM_REC_WORDS (93L)\n+#define NT_KM_CATEGORIES (94L)\n+#define NT_KM_END_OFS_SUPPORT (95L)\n+#define NT_KM_EXT_EXTRACTORS (96L)\n+#define NT_KM_FLOW_SETS (97L)\n+#define NT_KM_FLOW_TYPES (98L)\n+#define NT_KM_PRESENT (99L)\n+#define NT_KM_SWX_PRESENT (100L)\n+#define NT_KM_SYNERGY_MATCH (101L)\n+#define NT_KM_TCAM_BANKS (102L)\n+#define NT_KM_TCAM_BANK_WIDTH (103L)\n+#define NT_KM_TCAM_HIT_QUAL (104L)\n+#define NT_KM_TCAM_KEYWAY (105L)\n+#define NT_KM_WIDE (106L)\n+#define NT_LR_PRESENT (107L)\n+#define NT_LTX_CATEGORIES (108L)\n+#define NT_MCU_DRAM_SIZE (109L)\n+#define NT_MCU_PRESENT (110L)\n+#define NT_MCU_TYPE (111L)\n+#define NT_MDG_DEBUG_FLOW_CONTROL (112L)\n+#define NT_MDG_DEBUG_REG_READ_BACK (113L)\n+#define NT_MSK_CATEGORIES (114L)\n+#define NT_MSK_PRESENT (115L)\n+#define NT_NAME (116L)\n+#define NT_NFV_OVS_PRODUCT (117L)\n+#define NT_NIMS (118L)\n+#define NT_PATCH_NUMBER (119L)\n+#define NT_PCI_DEVICE_ID (120L)\n+#define NT_PCI_INT_AVR (121L)\n+#define NT_PCI_INT_EQM (122L)\n+#define NT_PCI_INT_IIC0 (123L)\n+#define NT_PCI_INT_IIC1 (124L)\n+#define NT_PCI_INT_IIC2 (125L)\n+#define NT_PCI_INT_IIC3 (126L)\n+#define NT_PCI_INT_IIC4 (127L)\n+#define NT_PCI_INT_IIC5 (128L)\n+#define NT_PCI_INT_PORT (129L)\n+#define NT_PCI_INT_PORT0 (130L)\n+#define NT_PCI_INT_PORT1 (131L)\n+#define NT_PCI_INT_PPS (132L)\n+#define NT_PCI_INT_QSPI (133L)\n+#define NT_PCI_INT_SPIM (134L)\n+#define NT_PCI_INT_SPIS (135L)\n+#define NT_PCI_INT_STA (136L)\n+#define NT_PCI_INT_TIMER (137L)\n+#define NT_PCI_INT_TINT (138L)\n+#define NT_PCI_TA_TG_PRESENT (139L)\n+#define NT_PCI_VENDOR_ID (140L)\n+#define NT_PDB_CATEGORIES (141L)\n+#define NT_PHY_ANEG_PRESENT (142L)\n+#define NT_PHY_KRFEC_PRESENT (143L)\n+#define NT_PHY_PORTS (144L)\n+#define NT_PHY_PORTS_PER_QUAD (145L)\n+#define NT_PHY_QUADS (146L)\n+#define NT_PHY_RSFEC_PRESENT (147L)\n+#define NT_PORTS (148L)\n+#define NT_PROD_ID_LAYOUT_VERSION (149L)\n+#define NT_QM_BLOCKS (150L)\n+#define NT_QM_CELLS (151L)\n+#define NT_QM_CELL_SIZE (152L)\n+#define NT_QM_PRESENT (153L)\n+#define NT_QSL_CATEGORIES (154L)\n+#define NT_QSL_COLOR_SEL_BW (155L)\n+#define NT_QSL_QST_SIZE (156L)\n+#define NT_QUEUES (157L)\n+#define NT_RAC_RAB_INTERFACES (158L)\n+#define NT_RAC_RAB_OB_UPDATE (159L)\n+#define NT_REVISION_ID (160L)\n+#define NT_RMC_LAG_GROUPS (161L)\n+#define NT_ROA_CATEGORIES (162L)\n+#define NT_ROA_PRESENT (163L)\n+#define NT_RPP_PER_PS (164L)\n+#define NT_RTX_PRESENT (165L)\n+#define NT_RX_HOST_BUFFERS (166L)\n+#define NT_RX_PORTS (167L)\n+#define NT_RX_PORT_REPLICATE (168L)\n+#define NT_SLB_PRESENT (169L)\n+#define NT_SLC_LR_PRESENT (170L)\n+#define NT_STA_COLORS (171L)\n+#define NT_STA_RX_PORTS (172L)\n+#define NT_TBH_DEBUG_DLN (173L)\n+#define NT_TBH_PRESENT (174L)\n+#define NT_TFD_PRESENT (175L)\n+#define NT_TPE_CATEGORIES (176L)\n+#define NT_TSM_OST_ONLY (177L)\n+#define NT_TS_APPEND (178L)\n+#define NT_TS_INJECT_PRESENT (179L)\n+#define NT_TX_CPY_PACKET_READERS (180L)\n+#define NT_TX_CPY_PRESENT (181L)\n+#define NT_TX_CPY_SIDEBAND_READERS (182L)\n+#define NT_TX_CPY_VARIANT (183L)\n+#define NT_TX_CPY_WRITERS (184L)\n+#define NT_TX_HOST_BUFFERS (185L)\n+#define NT_TX_INS_PRESENT (186L)\n+#define NT_TX_MTU_PROFILE_IFR (187L)\n+#define NT_TX_ON_TIMESTAMP (188L)\n+#define NT_TX_PORTS (189L)\n+#define NT_TX_PORT_REPLICATE (190L)\n+#define NT_TX_RPL_DEPTH (191L)\n+#define NT_TX_RPL_EXT_CATEGORIES (192L)\n+#define NT_TX_RPL_PRESENT (193L)\n+#define NT_TYPE_ID (194L)\n+#define NT_USE_TRIPLE_SPEED (195L)\n+#define NT_UUID (196L)\n+#define NT_VERSION (197L)\n+#define NT_VERSION_ID (198L)\n+#define NT_VLI_PRESENT (199L)\n+\n+#endif /* _NTHW_FPGA_PARAMETERS_DEFS_ */\ndiff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_registers_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_registers_defs.h\nnew file mode 100644\nindex 0000000000..54db76b73e\n--- /dev/null\n+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_registers_defs.h\n@@ -0,0 +1,7211 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Napatech A/S\n+ */\n+\n+#ifndef _NTHW_FPGA_REGISTERS_DEFS_\n+#define _NTHW_FPGA_REGISTERS_DEFS_\n+\n+/* CAT */\n+#define CAT_CCE_CTRL (1000L)\n+#define CAT_CCE_CTRL_ADR (1001L)\n+#define CAT_CCE_CTRL_CNT (1002L)\n+#define CAT_CCE_DATA (1003L)\n+#define CAT_CCE_DATA_IMM (1004L)\n+#define CAT_CCE_DATA_IND (1005L)\n+#define CAT_CCS_CTRL (1006L)\n+#define CAT_CCS_CTRL_ADR (1007L)\n+#define CAT_CCS_CTRL_CNT (1008L)\n+#define CAT_CCS_DATA (1009L)\n+#define CAT_CCS_DATA_COR (1010L)\n+#define CAT_CCS_DATA_COR_EN (1011L)\n+#define CAT_CCS_DATA_EPP (1012L)\n+#define CAT_CCS_DATA_EPP_EN (1013L)\n+#define CAT_CCS_DATA_HSH (1014L)\n+#define CAT_CCS_DATA_HSH_EN (1015L)\n+#define CAT_CCS_DATA_HST (1016L)\n+#define CAT_CCS_DATA_HST_EN (1017L)\n+#define CAT_CCS_DATA_IPF (1018L)\n+#define CAT_CCS_DATA_IPF_EN (1019L)\n+#define CAT_CCS_DATA_MSK (1020L)\n+#define CAT_CCS_DATA_MSK_EN (1021L)\n+#define CAT_CCS_DATA_PDB (1022L)\n+#define CAT_CCS_DATA_PDB_EN (1023L)\n+#define CAT_CCS_DATA_QSL (1024L)\n+#define CAT_CCS_DATA_QSL_EN (1025L)\n+#define CAT_CCS_DATA_RRB (1026L)\n+#define CAT_CCS_DATA_RRB_EN (1027L)\n+#define CAT_CCS_DATA_SB0_DATA (1028L)\n+#define CAT_CCS_DATA_SB0_TYPE (1029L)\n+#define CAT_CCS_DATA_SB1_DATA (1030L)\n+#define CAT_CCS_DATA_SB1_TYPE (1031L)\n+#define CAT_CCS_DATA_SB2_DATA (1032L)\n+#define CAT_CCS_DATA_SB2_TYPE (1033L)\n+#define CAT_CCS_DATA_SLC (1034L)\n+#define CAT_CCS_DATA_SLC_EN (1035L)\n+#define CAT_CCS_DATA_TPE (1036L)\n+#define CAT_CCS_DATA_TPE_EN (1037L)\n+#define CAT_CCT_CTRL (1038L)\n+#define CAT_CCT_CTRL_ADR (1039L)\n+#define CAT_CCT_CTRL_CNT (1040L)\n+#define CAT_CCT_DATA (1041L)\n+#define CAT_CCT_DATA_COLOR (1042L)\n+#define CAT_CCT_DATA_KM (1043L)\n+#define CAT_CFN_CTRL (1044L)\n+#define CAT_CFN_CTRL_ADR (1045L)\n+#define CAT_CFN_CTRL_CNT (1046L)\n+#define CAT_CFN_DATA (1047L)\n+#define CAT_CFN_DATA_ENABLE (1048L)\n+#define CAT_CFN_DATA_ERR_CV (1049L)\n+#define CAT_CFN_DATA_ERR_FCS (1050L)\n+#define CAT_CFN_DATA_ERR_INV (1051L)\n+#define CAT_CFN_DATA_ERR_L3_CS (1052L)\n+#define CAT_CFN_DATA_ERR_L4_CS (1053L)\n+#define CAT_CFN_DATA_ERR_TNL_L3_CS (1054L)\n+#define CAT_CFN_DATA_ERR_TNL_L4_CS (1055L)\n+#define CAT_CFN_DATA_ERR_TNL_TTL_EXP (1056L)\n+#define CAT_CFN_DATA_ERR_TRUNC (1057L)\n+#define CAT_CFN_DATA_ERR_TTL_EXP (1058L)\n+#define CAT_CFN_DATA_FLM_OR (1059L)\n+#define CAT_CFN_DATA_INV (1060L)\n+#define CAT_CFN_DATA_KM0_OR (1061L)\n+#define CAT_CFN_DATA_KM1_OR (1062L)\n+#define CAT_CFN_DATA_KM_OR (1063L)\n+#define CAT_CFN_DATA_LC (1064L)\n+#define CAT_CFN_DATA_LC_INV (1065L)\n+#define CAT_CFN_DATA_MAC_PORT (1066L)\n+#define CAT_CFN_DATA_PM_AND_INV (1067L)\n+#define CAT_CFN_DATA_PM_CMB (1068L)\n+#define CAT_CFN_DATA_PM_CMP (1069L)\n+#define CAT_CFN_DATA_PM_DCT (1070L)\n+#define CAT_CFN_DATA_PM_EXT_INV (1071L)\n+#define CAT_CFN_DATA_PM_INV (1072L)\n+#define CAT_CFN_DATA_PM_OR_INV (1073L)\n+#define CAT_CFN_DATA_PTC_CFP (1074L)\n+#define CAT_CFN_DATA_PTC_FRAG (1075L)\n+#define CAT_CFN_DATA_PTC_INV (1076L)\n+#define CAT_CFN_DATA_PTC_IP_PROT (1077L)\n+#define CAT_CFN_DATA_PTC_ISL (1078L)\n+#define CAT_CFN_DATA_PTC_L2 (1079L)\n+#define CAT_CFN_DATA_PTC_L3 (1080L)\n+#define CAT_CFN_DATA_PTC_L4 (1081L)\n+#define CAT_CFN_DATA_PTC_MAC (1082L)\n+#define CAT_CFN_DATA_PTC_MPLS (1083L)\n+#define CAT_CFN_DATA_PTC_TNL_FRAG (1084L)\n+#define CAT_CFN_DATA_PTC_TNL_IP_PROT (1085L)\n+#define CAT_CFN_DATA_PTC_TNL_L2 (1086L)\n+#define CAT_CFN_DATA_PTC_TNL_L3 (1087L)\n+#define CAT_CFN_DATA_PTC_TNL_L4 (1088L)\n+#define CAT_CFN_DATA_PTC_TNL_MPLS (1089L)\n+#define CAT_CFN_DATA_PTC_TNL_VLAN (1090L)\n+#define CAT_CFN_DATA_PTC_TUNNEL (1091L)\n+#define CAT_CFN_DATA_PTC_VLAN (1092L)\n+#define CAT_CFN_DATA_PTC_VNTAG (1093L)\n+#define CAT_COT_CTRL (1094L)\n+#define CAT_COT_CTRL_ADR (1095L)\n+#define CAT_COT_CTRL_CNT (1096L)\n+#define CAT_COT_DATA (1097L)\n+#define CAT_COT_DATA_COLOR (1098L)\n+#define CAT_COT_DATA_KM (1099L)\n+#define CAT_COT_DATA_NFV_SB (1100L)\n+#define CAT_CTE_CTRL (1101L)\n+#define CAT_CTE_CTRL_ADR (1102L)\n+#define CAT_CTE_CTRL_CNT (1103L)\n+#define CAT_CTE_DATA (1104L)\n+#define CAT_CTE_DATA_COL_ENABLE (1105L)\n+#define CAT_CTE_DATA_COR_ENABLE (1106L)\n+#define CAT_CTE_DATA_EPP_ENABLE (1107L)\n+#define CAT_CTE_DATA_HSH_ENABLE (1108L)\n+#define CAT_CTE_DATA_HST_ENABLE (1109L)\n+#define CAT_CTE_DATA_IPF_ENABLE (1110L)\n+#define CAT_CTE_DATA_MSK_ENABLE (1111L)\n+#define CAT_CTE_DATA_PDB_ENABLE (1112L)\n+#define CAT_CTE_DATA_QSL_ENABLE (1113L)\n+#define CAT_CTE_DATA_RRB_ENABLE (1114L)\n+#define CAT_CTE_DATA_SLC_ENABLE (1115L)\n+#define CAT_CTE_DATA_TPE_ENABLE (1116L)\n+#define CAT_CTE_DATA_TX_INS_ENABLE (1117L)\n+#define CAT_CTE_DATA_TX_RPL_ENABLE (1118L)\n+#define CAT_CTS_CTRL (1119L)\n+#define CAT_CTS_CTRL_ADR (1120L)\n+#define CAT_CTS_CTRL_CNT (1121L)\n+#define CAT_CTS_DATA (1122L)\n+#define CAT_CTS_DATA_CAT_A (1123L)\n+#define CAT_CTS_DATA_CAT_B (1124L)\n+#define CAT_DCT_CTRL (1125L)\n+#define CAT_DCT_CTRL_ADR (1126L)\n+#define CAT_DCT_CTRL_CNT (1127L)\n+#define CAT_DCT_DATA (1128L)\n+#define CAT_DCT_DATA_RES (1129L)\n+#define CAT_DCT_SEL (1130L)\n+#define CAT_DCT_SEL_LU (1131L)\n+#define CAT_EXO_CTRL (1132L)\n+#define CAT_EXO_CTRL_ADR (1133L)\n+#define CAT_EXO_CTRL_CNT (1134L)\n+#define CAT_EXO_DATA (1135L)\n+#define CAT_EXO_DATA_DYN (1136L)\n+#define CAT_EXO_DATA_OFS (1137L)\n+#define CAT_FCE_CTRL (1138L)\n+#define CAT_FCE_CTRL_ADR (1139L)\n+#define CAT_FCE_CTRL_CNT (1140L)\n+#define CAT_FCE_DATA (1141L)\n+#define CAT_FCE_DATA_ENABLE (1142L)\n+#define CAT_FCS_CTRL (1143L)\n+#define CAT_FCS_CTRL_ADR (1144L)\n+#define CAT_FCS_CTRL_CNT (1145L)\n+#define CAT_FCS_DATA (1146L)\n+#define CAT_FCS_DATA_CATEGORY (1147L)\n+#define CAT_FTE0_CTRL (1148L)\n+#define CAT_FTE0_CTRL_ADR (1149L)\n+#define CAT_FTE0_CTRL_CNT (1150L)\n+#define CAT_FTE0_DATA (1151L)\n+#define CAT_FTE0_DATA_ENABLE (1152L)\n+#define CAT_FTE1_CTRL (1153L)\n+#define CAT_FTE1_CTRL_ADR (1154L)\n+#define CAT_FTE1_CTRL_CNT (1155L)\n+#define CAT_FTE1_DATA (1156L)\n+#define CAT_FTE1_DATA_ENABLE (1157L)\n+#define CAT_FTE_CTRL (1158L)\n+#define CAT_FTE_CTRL_ADR (1159L)\n+#define CAT_FTE_CTRL_CNT (1160L)\n+#define CAT_FTE_DATA (1161L)\n+#define CAT_FTE_DATA_ENABLE (1162L)\n+#define CAT_FTE_FLM_CTRL (1163L)\n+#define CAT_FTE_FLM_CTRL_ADR (1164L)\n+#define CAT_FTE_FLM_CTRL_CNT (1165L)\n+#define CAT_FTE_FLM_DATA (1166L)\n+#define CAT_FTE_FLM_DATA_ENABLE (1167L)\n+#define CAT_JOIN (1168L)\n+#define CAT_JOIN_J1 (1169L)\n+#define CAT_JOIN_J2 (1170L)\n+#define CAT_KCC (1171L)\n+#define CAT_KCC_CTRL (1172L)\n+#define CAT_KCC_CTRL_ADR (1173L)\n+#define CAT_KCC_CTRL_CNT (1174L)\n+#define CAT_KCC_DATA (1175L)\n+#define CAT_KCC_DATA_CATEGORY (1176L)\n+#define CAT_KCC_DATA_ID (1177L)\n+#define CAT_KCC_DATA_KEY (1178L)\n+#define CAT_KCE0_CTRL (1179L)\n+#define CAT_KCE0_CTRL_ADR (1180L)\n+#define CAT_KCE0_CTRL_CNT (1181L)\n+#define CAT_KCE0_DATA (1182L)\n+#define CAT_KCE0_DATA_ENABLE (1183L)\n+#define CAT_KCE1_CTRL (1184L)\n+#define CAT_KCE1_CTRL_ADR (1185L)\n+#define CAT_KCE1_CTRL_CNT (1186L)\n+#define CAT_KCE1_DATA (1187L)\n+#define CAT_KCE1_DATA_ENABLE (1188L)\n+#define CAT_KCE_CTRL (1189L)\n+#define CAT_KCE_CTRL_ADR (1190L)\n+#define CAT_KCE_CTRL_CNT (1191L)\n+#define CAT_KCE_DATA (1192L)\n+#define CAT_KCE_DATA_ENABLE (1193L)\n+#define CAT_KCS0_CTRL (1194L)\n+#define CAT_KCS0_CTRL_ADR (1195L)\n+#define CAT_KCS0_CTRL_CNT (1196L)\n+#define CAT_KCS0_DATA (1197L)\n+#define CAT_KCS0_DATA_CATEGORY (1198L)\n+#define CAT_KCS1_CTRL (1199L)\n+#define CAT_KCS1_CTRL_ADR (1200L)\n+#define CAT_KCS1_CTRL_CNT (1201L)\n+#define CAT_KCS1_DATA (1202L)\n+#define CAT_KCS1_DATA_CATEGORY (1203L)\n+#define CAT_KCS_CTRL (1204L)\n+#define CAT_KCS_CTRL_ADR (1205L)\n+#define CAT_KCS_CTRL_CNT (1206L)\n+#define CAT_KCS_DATA (1207L)\n+#define CAT_KCS_DATA_CATEGORY (1208L)\n+#define CAT_LEN_CTRL (1209L)\n+#define CAT_LEN_CTRL_ADR (1210L)\n+#define CAT_LEN_CTRL_CNT (1211L)\n+#define CAT_LEN_DATA (1212L)\n+#define CAT_LEN_DATA_DYN1 (1213L)\n+#define CAT_LEN_DATA_DYN2 (1214L)\n+#define CAT_LEN_DATA_INV (1215L)\n+#define CAT_LEN_DATA_LOWER (1216L)\n+#define CAT_LEN_DATA_UPPER (1217L)\n+#define CAT_RCK_CTRL (1218L)\n+#define CAT_RCK_CTRL_ADR (1219L)\n+#define CAT_RCK_CTRL_CNT (1220L)\n+#define CAT_RCK_DATA (1221L)\n+#define CAT_RCK_DATA_CM0U (1222L)\n+#define CAT_RCK_DATA_CM1U (1223L)\n+#define CAT_RCK_DATA_CM2U (1224L)\n+#define CAT_RCK_DATA_CM3U (1225L)\n+#define CAT_RCK_DATA_CM4U (1226L)\n+#define CAT_RCK_DATA_CM5U (1227L)\n+#define CAT_RCK_DATA_CM6U (1228L)\n+#define CAT_RCK_DATA_CM7U (1229L)\n+#define CAT_RCK_DATA_CML0 (1230L)\n+#define CAT_RCK_DATA_CML1 (1231L)\n+#define CAT_RCK_DATA_CML2 (1232L)\n+#define CAT_RCK_DATA_CML3 (1233L)\n+#define CAT_RCK_DATA_CML4 (1234L)\n+#define CAT_RCK_DATA_CML5 (1235L)\n+#define CAT_RCK_DATA_CML6 (1236L)\n+#define CAT_RCK_DATA_CML7 (1237L)\n+#define CAT_RCK_DATA_SEL0 (1238L)\n+#define CAT_RCK_DATA_SEL1 (1239L)\n+#define CAT_RCK_DATA_SEL2 (1240L)\n+#define CAT_RCK_DATA_SEL3 (1241L)\n+#define CAT_RCK_DATA_SEL4 (1242L)\n+#define CAT_RCK_DATA_SEL5 (1243L)\n+#define CAT_RCK_DATA_SEL6 (1244L)\n+#define CAT_RCK_DATA_SEL7 (1245L)\n+#define CAT_RCK_DATA_SEU0 (1246L)\n+#define CAT_RCK_DATA_SEU1 (1247L)\n+#define CAT_RCK_DATA_SEU2 (1248L)\n+#define CAT_RCK_DATA_SEU3 (1249L)\n+#define CAT_RCK_DATA_SEU4 (1250L)\n+#define CAT_RCK_DATA_SEU5 (1251L)\n+#define CAT_RCK_DATA_SEU6 (1252L)\n+#define CAT_RCK_DATA_SEU7 (1253L)\n+/* CB */\n+#define CB_CTRL (1254L)\n+#define CB_CTRL_BP (1255L)\n+#define CB_CTRL_BYPASS (1256L)\n+#define CB_CTRL_ENABLE (1257L)\n+#define CB_CTRL_QMA (1258L)\n+#define CB_CTRL_QME (1259L)\n+#define CB_DBG_BP (1260L)\n+#define CB_DBG_BP_CNT (1261L)\n+#define CB_DBG_DQ (1262L)\n+#define CB_DBG_DQ_MAX (1263L)\n+#define CB_DBG_EGS_QUEUE (1264L)\n+#define CB_DBG_EGS_QUEUE_ADD (1265L)\n+#define CB_DBG_EGS_QUEUE_AND (1266L)\n+#define CB_DBG_FREE1200 (1267L)\n+#define CB_DBG_FREE1200_CNT (1268L)\n+#define CB_DBG_FREE1800 (1269L)\n+#define CB_DBG_FREE1800_CNT (1270L)\n+#define CB_DBG_FREE600 (1271L)\n+#define CB_DBG_FREE600_CNT (1272L)\n+#define CB_DBG_H16 (1273L)\n+#define CB_DBG_H16_CNT (1274L)\n+#define CB_DBG_H32 (1275L)\n+#define CB_DBG_H32_CNT (1276L)\n+#define CB_DBG_H64 (1277L)\n+#define CB_DBG_H64_CNT (1278L)\n+#define CB_DBG_HAVE (1279L)\n+#define CB_DBG_HAVE_CNT (1280L)\n+#define CB_DBG_IGS_QUEUE (1281L)\n+#define CB_DBG_IGS_QUEUE_ADD (1282L)\n+#define CB_DBG_IGS_QUEUE_AND (1283L)\n+#define CB_DBG_QM_CELL_CNT (1284L)\n+#define CB_DBG_QM_CELL_CNT_CNT (1285L)\n+#define CB_DBG_QM_CELL_XOR (1286L)\n+#define CB_DBG_QM_CELL_XOR_XOR (1287L)\n+#define CB_QPM_CTRL (1288L)\n+#define CB_QPM_CTRL_ADR (1289L)\n+#define CB_QPM_CTRL_CNT (1290L)\n+#define CB_QPM_DATA (1291L)\n+#define CB_QPM_DATA_P (1292L)\n+#define CB_QUEUE_MAX (1293L)\n+#define CB_QUEUE_MAX_MAX (1294L)\n+#define CB_STATUS (1295L)\n+#define CB_STATUS_BP (1296L)\n+#define CB_STATUS_DB (1297L)\n+#define CB_STATUS_EMPTY (1298L)\n+#define CB_STATUS_IDLE (1299L)\n+#define CB_STATUS_OVF (1300L)\n+#define CB_TS_RATE (1301L)\n+#define CB_TS_RATE_CNT (1302L)\n+#define CB_TS_SAVE (1303L)\n+#define CB_TS_SAVE_MAX (1304L)\n+/* CCIP */\n+#define CCIP_AFU_ID_L (1305L)\n+#define CCIP_AFU_ID_L_ID (1306L)\n+#define CCIP_AFU_ID_U (1307L)\n+#define CCIP_AFU_ID_U_ID (1308L)\n+#define CCIP_CONTROL (1309L)\n+#define CCIP_CONTROL_FENCE (1310L)\n+#define CCIP_DFH (1311L)\n+#define CCIP_DFH_AFU_VER_MAJOR (1312L)\n+#define CCIP_DFH_AFU_VER_MINOR (1313L)\n+#define CCIP_DFH_CCIP_VER (1314L)\n+#define CCIP_DFH_END (1315L)\n+#define CCIP_DFH_FEATURE_TYPE (1316L)\n+#define CCIP_DFH_NEXT (1317L)\n+#define CCIP_RSVD0 (1318L)\n+#define CCIP_RSVD0_RSVD (1319L)\n+#define CCIP_RSVD1 (1320L)\n+#define CCIP_RSVD1_RSVD (1321L)\n+#define CCIP_STATUS (1322L)\n+#define CCIP_STATUS_ERR (1323L)\n+#define CCIP_STATUS_PWR (1324L)\n+/* CFP4_CTRL_GBOX */\n+#define CFP4_CTRL_GBOX_CFG (1325L)\n+#define CFP4_CTRL_GBOX_CFG_GLB_ALARMN (1326L)\n+#define CFP4_CTRL_GBOX_CFG_INTERR (1327L)\n+#define CFP4_CTRL_GBOX_CFG_MOD_ABS (1328L)\n+#define CFP4_CTRL_GBOX_CFG_MOD_LOPWR (1329L)\n+#define CFP4_CTRL_GBOX_CFG_MOD_RSTN (1330L)\n+#define CFP4_CTRL_GBOX_CFG_NRESET (1331L)\n+#define CFP4_CTRL_GBOX_CFG_RXLOS (1332L)\n+#define CFP4_CTRL_GBOX_CFG_TXDIS (1333L)\n+#define CFP4_CTRL_GBOX_CFP4 (1334L)\n+#define CFP4_CTRL_GBOX_CFP4_GLB_ALARMN (1335L)\n+#define CFP4_CTRL_GBOX_CFP4_MOD_ABS (1336L)\n+#define CFP4_CTRL_GBOX_CFP4_MOD_LOPWR (1337L)\n+#define CFP4_CTRL_GBOX_CFP4_MOD_RSTN (1338L)\n+#define CFP4_CTRL_GBOX_CFP4_RXLOS (1339L)\n+#define CFP4_CTRL_GBOX_CFP4_TXDIS (1340L)\n+#define CFP4_CTRL_GBOX_GBOX (1341L)\n+#define CFP4_CTRL_GBOX_GBOX_INTERR (1342L)\n+#define CFP4_CTRL_GBOX_GBOX_NRESET (1343L)\n+#define CFP4_CTRL_GBOX_GPIO (1344L)\n+#define CFP4_CTRL_GBOX_GPIO_GLB_ALARMN (1345L)\n+#define CFP4_CTRL_GBOX_GPIO_INTERR (1346L)\n+#define CFP4_CTRL_GBOX_GPIO_MOD_ABS (1347L)\n+#define CFP4_CTRL_GBOX_GPIO_MOD_LOPWR (1348L)\n+#define CFP4_CTRL_GBOX_GPIO_MOD_RSTN (1349L)\n+#define CFP4_CTRL_GBOX_GPIO_NRESET (1350L)\n+#define CFP4_CTRL_GBOX_GPIO_RXLOS (1351L)\n+#define CFP4_CTRL_GBOX_GPIO_TXDIS (1352L)\n+/* COR */\n+#define COR_CTRL (1393L)\n+#define COR_CTRL_EN (1394L)\n+#define COR_DBG_COR_CNT (1395L)\n+#define COR_DBG_COR_CNT_VAL (1396L)\n+#define COR_DBG_COR_ID (1397L)\n+#define COR_DBG_COR_ID_VAL (1398L)\n+#define COR_DBG_COR_LO (1399L)\n+#define COR_DBG_COR_LO_VAL (1400L)\n+#define COR_DBG_COR_UP (1401L)\n+#define COR_DBG_COR_UP_VAL (1402L)\n+#define COR_DCEO (1403L)\n+#define COR_DCEO_VAL (1404L)\n+#define COR_DCSO (1405L)\n+#define COR_DCSO_VAL (1406L)\n+#define COR_DEEO (1407L)\n+#define COR_DEEO_VAL (1408L)\n+#define COR_DEO (1409L)\n+#define COR_DEO_VAL (1410L)\n+#define COR_DESO (1411L)\n+#define COR_DESO_VAL (1412L)\n+#define COR_DSEO (1413L)\n+#define COR_DSEO_VAL (1414L)\n+#define COR_DSO (1415L)\n+#define COR_DSO_VAL (1416L)\n+#define COR_DSSO (1417L)\n+#define COR_DSSO_VAL (1418L)\n+#define COR_RCP_CTRL (1419L)\n+#define COR_RCP_CTRL_ADR (1420L)\n+#define COR_RCP_CTRL_CNT (1421L)\n+#define COR_RCP_DATA (1422L)\n+#define COR_RCP_DATA_CBM1 (1423L)\n+#define COR_RCP_DATA_EN (1424L)\n+#define COR_RCP_DATA_END_PROT (1425L)\n+#define COR_RCP_DATA_END_STATIC (1426L)\n+#define COR_RCP_DATA_IP_CHK (1427L)\n+#define COR_RCP_DATA_IP_DSCP (1428L)\n+#define COR_RCP_DATA_IP_DST (1429L)\n+#define COR_RCP_DATA_IP_ECN (1430L)\n+#define COR_RCP_DATA_IP_FLAGS (1431L)\n+#define COR_RCP_DATA_IP_FLOW (1432L)\n+#define COR_RCP_DATA_IP_HOP (1433L)\n+#define COR_RCP_DATA_IP_IDENT (1434L)\n+#define COR_RCP_DATA_IP_NXTHDR (1435L)\n+#define COR_RCP_DATA_IP_SRC (1436L)\n+#define COR_RCP_DATA_IP_TC (1437L)\n+#define COR_RCP_DATA_IP_TTL (1438L)\n+#define COR_RCP_DATA_MAX_LEN (1439L)\n+#define COR_RCP_DATA_PROT_OFS1 (1440L)\n+#define COR_RCP_DATA_START_PROT (1441L)\n+#define COR_RCP_DATA_START_STATIC (1442L)\n+#define COR_RCP_DATA_STTC_OFS1 (1443L)\n+#define COR_RCP_DATA_TCP_CHK (1444L)\n+#define COR_RCP_DATA_TCP_DST (1445L)\n+#define COR_RCP_DATA_TCP_SEQ (1446L)\n+#define COR_RCP_DATA_TCP_SRC (1447L)\n+#define COR_RCP_DATA_TNL (1448L)\n+#define COR_RCP_DATA_UDP_CHK (1449L)\n+#define COR_RCP_DATA_UDP_DST (1450L)\n+#define COR_RCP_DATA_UDP_SRC (1451L)\n+/* CPY */\n+#define CPY_WRITER0_CTRL (1452L)\n+#define CPY_WRITER0_CTRL_ADR (1453L)\n+#define CPY_WRITER0_CTRL_CNT (1454L)\n+#define CPY_WRITER0_DATA (1455L)\n+#define CPY_WRITER0_DATA_DYN (1456L)\n+#define CPY_WRITER0_DATA_LEN (1457L)\n+#define CPY_WRITER0_DATA_MASK_POINTER (1458L)\n+#define CPY_WRITER0_DATA_OFS (1459L)\n+#define CPY_WRITER0_DATA_READER_SELECT (1460L)\n+#define CPY_WRITER0_MASK_CTRL (1461L)\n+#define CPY_WRITER0_MASK_CTRL_ADR (1462L)\n+#define CPY_WRITER0_MASK_CTRL_CNT (1463L)\n+#define CPY_WRITER0_MASK_DATA (1464L)\n+#define CPY_WRITER0_MASK_DATA_BYTE_MASK (1465L)\n+#define CPY_WRITER1_CTRL (1466L)\n+#define CPY_WRITER1_CTRL_ADR (1467L)\n+#define CPY_WRITER1_CTRL_CNT (1468L)\n+#define CPY_WRITER1_DATA (1469L)\n+#define CPY_WRITER1_DATA_DYN (1470L)\n+#define CPY_WRITER1_DATA_LEN (1471L)\n+#define CPY_WRITER1_DATA_MASK_POINTER (1472L)\n+#define CPY_WRITER1_DATA_OFS (1473L)\n+#define CPY_WRITER1_DATA_READER_SELECT (1474L)\n+#define CPY_WRITER1_MASK_CTRL (1475L)\n+#define CPY_WRITER1_MASK_CTRL_ADR (1476L)\n+#define CPY_WRITER1_MASK_CTRL_CNT (1477L)\n+#define CPY_WRITER1_MASK_DATA (1478L)\n+#define CPY_WRITER1_MASK_DATA_BYTE_MASK (1479L)\n+#define CPY_WRITER2_CTRL (1480L)\n+#define CPY_WRITER2_CTRL_ADR (1481L)\n+#define CPY_WRITER2_CTRL_CNT (1482L)\n+#define CPY_WRITER2_DATA (1483L)\n+#define CPY_WRITER2_DATA_DYN (1484L)\n+#define CPY_WRITER2_DATA_LEN (1485L)\n+#define CPY_WRITER2_DATA_MASK_POINTER (1486L)\n+#define CPY_WRITER2_DATA_OFS (1487L)\n+#define CPY_WRITER2_DATA_READER_SELECT (1488L)\n+#define CPY_WRITER2_MASK_CTRL (1489L)\n+#define CPY_WRITER2_MASK_CTRL_ADR (1490L)\n+#define CPY_WRITER2_MASK_CTRL_CNT (1491L)\n+#define CPY_WRITER2_MASK_DATA (1492L)\n+#define CPY_WRITER2_MASK_DATA_BYTE_MASK (1493L)\n+#define CPY_WRITER3_CTRL (1494L)\n+#define CPY_WRITER3_CTRL_ADR (1495L)\n+#define CPY_WRITER3_CTRL_CNT (1496L)\n+#define CPY_WRITER3_DATA (1497L)\n+#define CPY_WRITER3_DATA_DYN (1498L)\n+#define CPY_WRITER3_DATA_LEN (1499L)\n+#define CPY_WRITER3_DATA_MASK_POINTER (1500L)\n+#define CPY_WRITER3_DATA_OFS (1501L)\n+#define CPY_WRITER3_DATA_READER_SELECT (1502L)\n+#define CPY_WRITER3_MASK_CTRL (1503L)\n+#define CPY_WRITER3_MASK_CTRL_ADR (1504L)\n+#define CPY_WRITER3_MASK_CTRL_CNT (1505L)\n+#define CPY_WRITER3_MASK_DATA (1506L)\n+#define CPY_WRITER3_MASK_DATA_BYTE_MASK (1507L)\n+#define CPY_WRITER4_CTRL (1508L)\n+#define CPY_WRITER4_CTRL_ADR (1509L)\n+#define CPY_WRITER4_CTRL_CNT (1510L)\n+#define CPY_WRITER4_DATA (1511L)\n+#define CPY_WRITER4_DATA_DYN (1512L)\n+#define CPY_WRITER4_DATA_LEN (1513L)\n+#define CPY_WRITER4_DATA_MASK_POINTER (1514L)\n+#define CPY_WRITER4_DATA_OFS (1515L)\n+#define CPY_WRITER4_DATA_READER_SELECT (1516L)\n+#define CPY_WRITER4_MASK_CTRL (1517L)\n+#define CPY_WRITER4_MASK_CTRL_ADR (1518L)\n+#define CPY_WRITER4_MASK_CTRL_CNT (1519L)\n+#define CPY_WRITER4_MASK_DATA (1520L)\n+#define CPY_WRITER4_MASK_DATA_BYTE_MASK (1521L)\n+#define CPY_WRITER5_CTRL (1522L)\n+#define CPY_WRITER5_CTRL_ADR (1523L)\n+#define CPY_WRITER5_CTRL_CNT (1524L)\n+#define CPY_WRITER5_DATA (1525L)\n+#define CPY_WRITER5_DATA_DYN (1526L)\n+#define CPY_WRITER5_DATA_LEN (1527L)\n+#define CPY_WRITER5_DATA_MASK_POINTER (1528L)\n+#define CPY_WRITER5_DATA_OFS (1529L)\n+#define CPY_WRITER5_DATA_READER_SELECT (1530L)\n+#define CPY_WRITER5_MASK_CTRL (1531L)\n+#define CPY_WRITER5_MASK_CTRL_ADR (1532L)\n+#define CPY_WRITER5_MASK_CTRL_CNT (1533L)\n+#define CPY_WRITER5_MASK_DATA (1534L)\n+#define CPY_WRITER5_MASK_DATA_BYTE_MASK (1535L)\n+/* CSU */\n+#define CSU_RCP_CTRL (1536L)\n+#define CSU_RCP_CTRL_ADR (1537L)\n+#define CSU_RCP_CTRL_CNT (1538L)\n+#define CSU_RCP_DATA (1539L)\n+#define CSU_RCP_DATA_IL3_CMD (1540L)\n+#define CSU_RCP_DATA_IL4_CMD (1541L)\n+#define CSU_RCP_DATA_OL3_CMD (1542L)\n+#define CSU_RCP_DATA_OL4_CMD (1543L)\n+/* DBS */\n+#define DBS_RX_AM_CTRL (1544L)\n+#define DBS_RX_AM_CTRL_ADR (1545L)\n+#define DBS_RX_AM_CTRL_CNT (1546L)\n+#define DBS_RX_AM_DATA (1547L)\n+#define DBS_RX_AM_DATA_ENABLE (1548L)\n+#define DBS_RX_AM_DATA_GPA (1549L)\n+#define DBS_RX_AM_DATA_HID (1550L)\n+#define DBS_RX_AM_DATA_INT (1551L)\n+#define DBS_RX_AM_DATA_PCKED (1552L)\n+#define DBS_RX_CONTROL (1553L)\n+#define DBS_RX_CONTROL_AME (1554L)\n+#define DBS_RX_CONTROL_AMS (1555L)\n+#define DBS_RX_CONTROL_LQ (1556L)\n+#define DBS_RX_CONTROL_QE (1557L)\n+#define DBS_RX_CONTROL_UWE (1558L)\n+#define DBS_RX_CONTROL_UWS (1559L)\n+#define DBS_RX_DR_CTRL (1560L)\n+#define DBS_RX_DR_CTRL_ADR (1561L)\n+#define DBS_RX_DR_CTRL_CNT (1562L)\n+#define DBS_RX_DR_DATA (1563L)\n+#define DBS_RX_DR_DATA_GPA (1564L)\n+#define DBS_RX_DR_DATA_HDR (1565L)\n+#define DBS_RX_DR_DATA_HID (1566L)\n+#define DBS_RX_DR_DATA_PCKED (1567L)\n+#define DBS_RX_DR_DATA_QS (1568L)\n+#define DBS_RX_IDLE (1569L)\n+#define DBS_RX_IDLE_BUSY (1570L)\n+#define DBS_RX_IDLE_IDLE (1571L)\n+#define DBS_RX_IDLE_QUEUE (1572L)\n+#define DBS_RX_INIT (1573L)\n+#define DBS_RX_INIT_BUSY (1574L)\n+#define DBS_RX_INIT_INIT (1575L)\n+#define DBS_RX_INIT_QUEUE (1576L)\n+#define DBS_RX_INIT_VAL (1577L)\n+#define DBS_RX_INIT_VAL_IDX (1578L)\n+#define DBS_RX_INIT_VAL_PTR (1579L)\n+#define DBS_RX_PTR (1580L)\n+#define DBS_RX_PTR_PTR (1581L)\n+#define DBS_RX_PTR_QUEUE (1582L)\n+#define DBS_RX_PTR_VALID (1583L)\n+#define DBS_RX_UW_CTRL (1584L)\n+#define DBS_RX_UW_CTRL_ADR (1585L)\n+#define DBS_RX_UW_CTRL_CNT (1586L)\n+#define DBS_RX_UW_DATA (1587L)\n+#define DBS_RX_UW_DATA_GPA (1588L)\n+#define DBS_RX_UW_DATA_HID (1589L)\n+#define DBS_RX_UW_DATA_INT (1590L)\n+#define DBS_RX_UW_DATA_ISTK (1591L)\n+#define DBS_RX_UW_DATA_PCKED (1592L)\n+#define DBS_RX_UW_DATA_QS (1593L)\n+#define DBS_RX_UW_DATA_VEC (1594L)\n+#define DBS_STATUS (1595L)\n+#define DBS_STATUS_OK (1596L)\n+#define DBS_TX_AM_CTRL (1597L)\n+#define DBS_TX_AM_CTRL_ADR (1598L)\n+#define DBS_TX_AM_CTRL_CNT (1599L)\n+#define DBS_TX_AM_DATA (1600L)\n+#define DBS_TX_AM_DATA_ENABLE (1601L)\n+#define DBS_TX_AM_DATA_GPA (1602L)\n+#define DBS_TX_AM_DATA_HID (1603L)\n+#define DBS_TX_AM_DATA_INT (1604L)\n+#define DBS_TX_AM_DATA_PCKED (1605L)\n+#define DBS_TX_CONTROL (1606L)\n+#define DBS_TX_CONTROL_AME (1607L)\n+#define DBS_TX_CONTROL_AMS (1608L)\n+#define DBS_TX_CONTROL_LQ (1609L)\n+#define DBS_TX_CONTROL_QE (1610L)\n+#define DBS_TX_CONTROL_UWE (1611L)\n+#define DBS_TX_CONTROL_UWS (1612L)\n+#define DBS_TX_DR_CTRL (1613L)\n+#define DBS_TX_DR_CTRL_ADR (1614L)\n+#define DBS_TX_DR_CTRL_CNT (1615L)\n+#define DBS_TX_DR_DATA (1616L)\n+#define DBS_TX_DR_DATA_GPA (1617L)\n+#define DBS_TX_DR_DATA_HDR (1618L)\n+#define DBS_TX_DR_DATA_HID (1619L)\n+#define DBS_TX_DR_DATA_PCKED (1620L)\n+#define DBS_TX_DR_DATA_PORT (1621L)\n+#define DBS_TX_DR_DATA_QS (1622L)\n+#define DBS_TX_IDLE (1623L)\n+#define DBS_TX_IDLE_BUSY (1624L)\n+#define DBS_TX_IDLE_IDLE (1625L)\n+#define DBS_TX_IDLE_QUEUE (1626L)\n+#define DBS_TX_INIT (1627L)\n+#define DBS_TX_INIT_BUSY (1628L)\n+#define DBS_TX_INIT_INIT (1629L)\n+#define DBS_TX_INIT_QUEUE (1630L)\n+#define DBS_TX_INIT_VAL (1631L)\n+#define DBS_TX_INIT_VAL_IDX (1632L)\n+#define DBS_TX_INIT_VAL_PTR (1633L)\n+#define DBS_TX_PTR (1634L)\n+#define DBS_TX_PTR_PTR (1635L)\n+#define DBS_TX_PTR_QUEUE (1636L)\n+#define DBS_TX_PTR_VALID (1637L)\n+#define DBS_TX_QOS_CTRL (1638L)\n+#define DBS_TX_QOS_CTRL_ADR (1639L)\n+#define DBS_TX_QOS_CTRL_CNT (1640L)\n+#define DBS_TX_QOS_DATA (1641L)\n+#define DBS_TX_QOS_DATA_BS (1642L)\n+#define DBS_TX_QOS_DATA_EN (1643L)\n+#define DBS_TX_QOS_DATA_IR (1644L)\n+#define DBS_TX_QOS_DATA_MUL (1645L)\n+#define DBS_TX_QOS_RATE (1646L)\n+#define DBS_TX_QOS_RATE_DIV (1647L)\n+#define DBS_TX_QOS_RATE_MUL (1648L)\n+#define DBS_TX_QP_CTRL (1649L)\n+#define DBS_TX_QP_CTRL_ADR (1650L)\n+#define DBS_TX_QP_CTRL_CNT (1651L)\n+#define DBS_TX_QP_DATA (1652L)\n+#define DBS_TX_QP_DATA_VPORT (1653L)\n+#define DBS_TX_UW_CTRL (1654L)\n+#define DBS_TX_UW_CTRL_ADR (1655L)\n+#define DBS_TX_UW_CTRL_CNT (1656L)\n+#define DBS_TX_UW_DATA (1657L)\n+#define DBS_TX_UW_DATA_GPA (1658L)\n+#define DBS_TX_UW_DATA_HID (1659L)\n+#define DBS_TX_UW_DATA_INO (1660L)\n+#define DBS_TX_UW_DATA_INT (1661L)\n+#define DBS_TX_UW_DATA_ISTK (1662L)\n+#define DBS_TX_UW_DATA_PCKED (1663L)\n+#define DBS_TX_UW_DATA_QS (1664L)\n+#define DBS_TX_UW_DATA_VEC (1665L)\n+/* DDP */\n+#define DDP_AGING_CTRL (1666L)\n+#define DDP_AGING_CTRL_AGING_RATE (1667L)\n+#define DDP_AGING_CTRL_MAX_CNT (1668L)\n+#define DDP_CTRL (1669L)\n+#define DDP_CTRL_INIT (1670L)\n+#define DDP_CTRL_INIT_DONE (1671L)\n+#define DDP_RCP_CTRL (1672L)\n+#define DDP_RCP_CTRL_ADR (1673L)\n+#define DDP_RCP_CTRL_CNT (1674L)\n+#define DDP_RCP_DATA (1675L)\n+#define DDP_RCP_DATA_EN (1676L)\n+#define DDP_RCP_DATA_GROUPID (1677L)\n+/* EPP */\n+#define EPP_QUEUE_MTU_CTRL (1755L)\n+#define EPP_QUEUE_MTU_CTRL_ADR (1756L)\n+#define EPP_QUEUE_MTU_CTRL_CNT (1757L)\n+#define EPP_QUEUE_MTU_DATA (1758L)\n+#define EPP_QUEUE_MTU_DATA_MAX_MTU (1759L)\n+#define EPP_QUEUE_VPORT_CTRL (1760L)\n+#define EPP_QUEUE_VPORT_CTRL_ADR (1761L)\n+#define EPP_QUEUE_VPORT_CTRL_CNT (1762L)\n+#define EPP_QUEUE_VPORT_DATA (1763L)\n+#define EPP_QUEUE_VPORT_DATA_VPORT (1764L)\n+#define EPP_RCP_CTRL (1765L)\n+#define EPP_RCP_CTRL_ADR (1766L)\n+#define EPP_RCP_CTRL_CNT (1767L)\n+#define EPP_RCP_DATA (1768L)\n+#define EPP_RCP_DATA_FIXED_18B_L2_MTU (1769L)\n+#define EPP_RCP_DATA_QUEUE_MTU_EPP_EN (1770L)\n+#define EPP_RCP_DATA_QUEUE_QOS_EPP_EN (1771L)\n+#define EPP_RCP_DATA_SIZE_ADJUST_TXP (1772L)\n+#define EPP_RCP_DATA_SIZE_ADJUST_VPORT (1773L)\n+#define EPP_RCP_DATA_TX_MTU_EPP_EN (1774L)\n+#define EPP_RCP_DATA_TX_QOS_EPP_EN (1775L)\n+#define EPP_TXP_MTU_CTRL (1776L)\n+#define EPP_TXP_MTU_CTRL_ADR (1777L)\n+#define EPP_TXP_MTU_CTRL_CNT (1778L)\n+#define EPP_TXP_MTU_DATA (1779L)\n+#define EPP_TXP_MTU_DATA_MAX_MTU (1780L)\n+#define EPP_TXP_QOS_CTRL (1781L)\n+#define EPP_TXP_QOS_CTRL_ADR (1782L)\n+#define EPP_TXP_QOS_CTRL_CNT (1783L)\n+#define EPP_TXP_QOS_DATA (1784L)\n+#define EPP_TXP_QOS_DATA_BS (1785L)\n+#define EPP_TXP_QOS_DATA_EN (1786L)\n+#define EPP_TXP_QOS_DATA_IR (1787L)\n+#define EPP_TXP_QOS_DATA_IR_FRACTION (1788L)\n+#define EPP_VPORT_QOS_CTRL (1789L)\n+#define EPP_VPORT_QOS_CTRL_ADR (1790L)\n+#define EPP_VPORT_QOS_CTRL_CNT (1791L)\n+#define EPP_VPORT_QOS_DATA (1792L)\n+#define EPP_VPORT_QOS_DATA_BS (1793L)\n+#define EPP_VPORT_QOS_DATA_EN (1794L)\n+#define EPP_VPORT_QOS_DATA_IR (1795L)\n+#define EPP_VPORT_QOS_DATA_IR_FRACTION (1796L)\n+/* EQM */\n+#define EQM_CTRL (1797L)\n+#define EQM_CTRL_DBG_CRC_ERR (1798L)\n+#define EQM_CTRL_DBG_FORCE_ERR (1799L)\n+#define EQM_CTRL_DBG_RMT_ERR (1800L)\n+#define EQM_CTRL_DBG_SYNC_ERR (1801L)\n+#define EQM_CTRL_ENABLE (1802L)\n+#define EQM_CTRL_MODE (1803L)\n+#define EQM_CTRL_PP_RST (1804L)\n+#define EQM_DBG (1805L)\n+#define EQM_DBG_FIFO_OF (1806L)\n+#define EQM_DBG_LCL_EGS_QKA_OF (1807L)\n+#define EQM_DBG_LCL_EGS_QLVL_OF (1808L)\n+#define EQM_DBG_QBLK_CREDITS (1809L)\n+#define EQM_STATUS (1810L)\n+#define EQM_STATUS_LCL_EGS_OF_ERR (1811L)\n+#define EQM_STATUS_NIF_CRC_ERR (1812L)\n+#define EQM_STATUS_NIF_PP_LOOP_LCK (1813L)\n+#define EQM_STATUS_NIF_RX_OF_ERR (1814L)\n+#define EQM_STATUS_NIF_SYNC_ERR (1815L)\n+#define EQM_STATUS_QM_CRC_ERR (1816L)\n+#define EQM_STATUS_RMT_EGS_OF_ERR (1817L)\n+#define EQM_STATUS_RMT_ERR (1818L)\n+#define EQM_STATUS_RMT_IGS_OF_ERR (1819L)\n+/* FHM */\n+#define FHM_BACK_PRESSURE (1820L)\n+#define FHM_BACK_PRESSURE_NIF (1821L)\n+#define FHM_BACK_PRESSURE_RMC (1822L)\n+#define FHM_BACK_PRESSURE_RMC_S (1823L)\n+#define FHM_CRC_ERROR_NIF (1824L)\n+#define FHM_CRC_ERROR_NIF_CNT (1825L)\n+#define FHM_CRC_ERROR_SDC (1826L)\n+#define FHM_CRC_ERROR_SDC_CNT (1827L)\n+#define FHM_CTRL (1828L)\n+#define FHM_CTRL_CNT_CLR (1829L)\n+#define FHM_CTRL_ENABLE (1830L)\n+#define FHM_CTRL_MODE (1831L)\n+#define FHM_DEBUG_CRC (1832L)\n+#define FHM_DEBUG_CRC_FORCE_ERROR (1833L)\n+#define FHM_DEBUG_SDRAM_SIZE (1834L)\n+#define FHM_DEBUG_SDRAM_SIZE_MASK (1835L)\n+#define FHM_FILL_LEVEL (1836L)\n+#define FHM_FILL_LEVEL_CELLS (1837L)\n+#define FHM_MAC_MICRO_DROP (1838L)\n+#define FHM_MAC_MICRO_DROP_CNT (1839L)\n+#define FHM_MAX_FILL_LEVEL (1840L)\n+#define FHM_MAX_FILL_LEVEL_CELLS (1841L)\n+#define FHM_PKT_DROP (1842L)\n+#define FHM_PKT_DROP_CNT (1843L)\n+#define FHM_PKT_DROP_BYTES (1844L)\n+#define FHM_PKT_DROP_BYTES_CNT (1845L)\n+/* FLM */\n+#define FLM_BUF_CTRL (1855L)\n+#define FLM_BUF_CTRL_INF_AVAIL (1856L)\n+#define FLM_BUF_CTRL_LRN_FREE (1857L)\n+#define FLM_BUF_CTRL_STA_AVAIL (1858L)\n+#define FLM_CONTROL (1859L)\n+#define FLM_CONTROL_CRCRD (1860L)\n+#define FLM_CONTROL_CRCWR (1861L)\n+#define FLM_CONTROL_EAB (1862L)\n+#define FLM_CONTROL_ENABLE (1863L)\n+#define FLM_CONTROL_INIT (1864L)\n+#define FLM_CONTROL_LDS (1865L)\n+#define FLM_CONTROL_LFS (1866L)\n+#define FLM_CONTROL_LIS (1867L)\n+#define FLM_CONTROL_PDS (1868L)\n+#define FLM_CONTROL_PIS (1869L)\n+#define FLM_CONTROL_RBL (1870L)\n+#define FLM_CONTROL_RDS (1871L)\n+#define FLM_CONTROL_RIS (1872L)\n+#define FLM_CONTROL_SPLIT_SDRAM_USAGE (1873L)\n+#define FLM_CONTROL_UDS (1874L)\n+#define FLM_CONTROL_UIS (1875L)\n+#define FLM_CONTROL_WPD (1876L)\n+#define FLM_INF_DATA (1877L)\n+#define FLM_INF_DATA_BYTES (1878L)\n+#define FLM_INF_DATA_BYT_A (1879L)\n+#define FLM_INF_DATA_BYT_B (1880L)\n+#define FLM_INF_DATA_CAUSE (1881L)\n+#define FLM_INF_DATA_EOR (1882L)\n+#define FLM_INF_DATA_ID (1883L)\n+#define FLM_INF_DATA_PACKETS (1884L)\n+#define FLM_INF_DATA_PCK_A (1885L)\n+#define FLM_INF_DATA_PCK_B (1886L)\n+#define FLM_INF_DATA_RTX_A (1887L)\n+#define FLM_INF_DATA_RTX_B (1888L)\n+#define FLM_INF_DATA_TCP_A (1889L)\n+#define FLM_INF_DATA_TCP_B (1890L)\n+#define FLM_INF_DATA_TS (1891L)\n+#define FLM_LOAD_APS (1892L)\n+#define FLM_LOAD_APS_APS (1893L)\n+#define FLM_LOAD_BIN (1894L)\n+#define FLM_LOAD_BIN_BIN (1895L)\n+#define FLM_LOAD_LPS (1896L)\n+#define FLM_LOAD_LPS_LPS (1897L)\n+#define FLM_LOAD_PPS (1898L)\n+#define FLM_LOAD_PPS_PPS (1899L)\n+#define FLM_LRN_CTRL (1900L)\n+#define FLM_LRN_CTRL_FREE (1901L)\n+#define FLM_LRN_DATA (1902L)\n+#define FLM_LRN_DATA_ADJ (1903L)\n+#define FLM_LRN_DATA_COLOR (1904L)\n+#define FLM_LRN_DATA_DSCP (1905L)\n+#define FLM_LRN_DATA_ENT (1906L)\n+#define FLM_LRN_DATA_EOR (1907L)\n+#define FLM_LRN_DATA_FILL (1908L)\n+#define FLM_LRN_DATA_FT (1909L)\n+#define FLM_LRN_DATA_FT_MBR (1910L)\n+#define FLM_LRN_DATA_FT_MISS (1911L)\n+#define FLM_LRN_DATA_GFI (1912L)\n+#define FLM_LRN_DATA_ID (1913L)\n+#define FLM_LRN_DATA_KID (1914L)\n+#define FLM_LRN_DATA_MBR_ID1 (1915L)\n+#define FLM_LRN_DATA_MBR_ID2 (1916L)\n+#define FLM_LRN_DATA_MBR_ID3 (1917L)\n+#define FLM_LRN_DATA_MBR_ID4 (1918L)\n+#define FLM_LRN_DATA_NAT_EN (1919L)\n+#define FLM_LRN_DATA_NAT_IP (1920L)\n+#define FLM_LRN_DATA_NAT_PORT (1921L)\n+#define FLM_LRN_DATA_OP (1922L)\n+#define FLM_LRN_DATA_PRIO (1923L)\n+#define FLM_LRN_DATA_PROT (1924L)\n+#define FLM_LRN_DATA_QFI (1925L)\n+#define FLM_LRN_DATA_QW0 (1926L)\n+#define FLM_LRN_DATA_QW4 (1927L)\n+#define FLM_LRN_DATA_RATE (1928L)\n+#define FLM_LRN_DATA_RQI (1929L)\n+#define FLM_LRN_DATA_SIZE (1930L)\n+#define FLM_LRN_DATA_STAT_PROF (1931L)\n+#define FLM_LRN_DATA_SW8 (1932L)\n+#define FLM_LRN_DATA_SW9 (1933L)\n+#define FLM_LRN_DATA_TAU (1934L)\n+#define FLM_LRN_DATA_TEID (1935L)\n+#define FLM_LRN_DATA_TTL (1936L)\n+#define FLM_LRN_DATA_VOL_IDX (1937L)\n+#define FLM_PRIO (1938L)\n+#define FLM_PRIO_FT0 (1939L)\n+#define FLM_PRIO_FT1 (1940L)\n+#define FLM_PRIO_FT2 (1941L)\n+#define FLM_PRIO_FT3 (1942L)\n+#define FLM_PRIO_LIMIT0 (1943L)\n+#define FLM_PRIO_LIMIT1 (1944L)\n+#define FLM_PRIO_LIMIT2 (1945L)\n+#define FLM_PRIO_LIMIT3 (1946L)\n+#define FLM_PST_CTRL (1947L)\n+#define FLM_PST_CTRL_ADR (1948L)\n+#define FLM_PST_CTRL_CNT (1949L)\n+#define FLM_PST_DATA (1950L)\n+#define FLM_PST_DATA_BP (1951L)\n+#define FLM_PST_DATA_PP (1952L)\n+#define FLM_PST_DATA_TP (1953L)\n+#define FLM_RCP_CTRL (1954L)\n+#define FLM_RCP_CTRL_ADR (1955L)\n+#define FLM_RCP_CTRL_CNT (1956L)\n+#define FLM_RCP_DATA (1957L)\n+#define FLM_RCP_DATA_A (1958L)\n+#define FLM_RCP_DATA_AUTO_IPV4_MASK (1959L)\n+#define FLM_RCP_DATA_B (1960L)\n+#define FLM_RCP_DATA_BYT_DYN (1961L)\n+#define FLM_RCP_DATA_BYT_OFS (1962L)\n+#define FLM_RCP_DATA_IPN (1963L)\n+#define FLM_RCP_DATA_ITF (1964L)\n+#define FLM_RCP_DATA_KID (1965L)\n+#define FLM_RCP_DATA_LOOKUP (1966L)\n+#define FLM_RCP_DATA_MASK (1967L)\n+#define FLM_RCP_DATA_OPN (1968L)\n+#define FLM_RCP_DATA_QW0_DYN (1969L)\n+#define FLM_RCP_DATA_QW0_OFS (1970L)\n+#define FLM_RCP_DATA_QW0_SEL (1971L)\n+#define FLM_RCP_DATA_QW4_DYN (1972L)\n+#define FLM_RCP_DATA_QW4_OFS (1973L)\n+#define FLM_RCP_DATA_SW8_DYN (1974L)\n+#define FLM_RCP_DATA_SW8_OFS (1975L)\n+#define FLM_RCP_DATA_SW8_SEL (1976L)\n+#define FLM_RCP_DATA_SW9_DYN (1977L)\n+#define FLM_RCP_DATA_SW9_OFS (1978L)\n+#define FLM_RCP_DATA_TXPLM (1979L)\n+#define FLM_SCRUB (1980L)\n+#define FLM_SCRUB_I (1981L)\n+#define FLM_STATUS (1982L)\n+#define FLM_STATUS_CALIBDONE (1983L)\n+#define FLM_STATUS_CRCERR (1984L)\n+#define FLM_STATUS_CRITICAL (1985L)\n+#define FLM_STATUS_EFT_BP (1986L)\n+#define FLM_STATUS_EFT_EVICT_BP (1987L)\n+#define FLM_STATUS_IDLE (1988L)\n+#define FLM_STATUS_INITDONE (1989L)\n+#define FLM_STATUS_PANIC (1990L)\n+#define FLM_STAT_AUL_DONE (1991L)\n+#define FLM_STAT_AUL_DONE_CNT (1992L)\n+#define FLM_STAT_AUL_FAIL (1993L)\n+#define FLM_STAT_AUL_FAIL_CNT (1994L)\n+#define FLM_STAT_AUL_IGNORE (1995L)\n+#define FLM_STAT_AUL_IGNORE_CNT (1996L)\n+#define FLM_STAT_CSH_HIT (1997L)\n+#define FLM_STAT_CSH_HIT_CNT (1998L)\n+#define FLM_STAT_CSH_MISS (1999L)\n+#define FLM_STAT_CSH_MISS_CNT (2000L)\n+#define FLM_STAT_CSH_UNH (2001L)\n+#define FLM_STAT_CSH_UNH_CNT (2002L)\n+#define FLM_STAT_CUC_MOVE (2003L)\n+#define FLM_STAT_CUC_MOVE_CNT (2004L)\n+#define FLM_STAT_CUC_START (2005L)\n+#define FLM_STAT_CUC_START_CNT (2006L)\n+#define FLM_STAT_FLOWS (2007L)\n+#define FLM_STAT_FLOWS_CNT (2008L)\n+#define FLM_STAT_INF_DONE (2009L)\n+#define FLM_STAT_INF_DONE_CNT (2010L)\n+#define FLM_STAT_INF_SKIP (2011L)\n+#define FLM_STAT_INF_SKIP_CNT (2012L)\n+#define FLM_STAT_LRN_DONE (2013L)\n+#define FLM_STAT_LRN_DONE_CNT (2014L)\n+#define FLM_STAT_LRN_FAIL (2015L)\n+#define FLM_STAT_LRN_FAIL_CNT (2016L)\n+#define FLM_STAT_LRN_IGNORE (2017L)\n+#define FLM_STAT_LRN_IGNORE_CNT (2018L)\n+#define FLM_STAT_PCK_DIS (2019L)\n+#define FLM_STAT_PCK_DIS_CNT (2020L)\n+#define FLM_STAT_PCK_HIT (2021L)\n+#define FLM_STAT_PCK_HIT_CNT (2022L)\n+#define FLM_STAT_PCK_MISS (2023L)\n+#define FLM_STAT_PCK_MISS_CNT (2024L)\n+#define FLM_STAT_PCK_UNH (2025L)\n+#define FLM_STAT_PCK_UNH_CNT (2026L)\n+#define FLM_STAT_PRB_DONE (2027L)\n+#define FLM_STAT_PRB_DONE_CNT (2028L)\n+#define FLM_STAT_PRB_IGNORE (2029L)\n+#define FLM_STAT_PRB_IGNORE_CNT (2030L)\n+#define FLM_STAT_REL_DONE (2031L)\n+#define FLM_STAT_REL_DONE_CNT (2032L)\n+#define FLM_STAT_REL_IGNORE (2033L)\n+#define FLM_STAT_REL_IGNORE_CNT (2034L)\n+#define FLM_STAT_STA_DONE (2035L)\n+#define FLM_STAT_STA_DONE_CNT (2036L)\n+#define FLM_STAT_TUL_DONE (2037L)\n+#define FLM_STAT_TUL_DONE_CNT (2038L)\n+#define FLM_STAT_UNL_DONE (2039L)\n+#define FLM_STAT_UNL_DONE_CNT (2040L)\n+#define FLM_STAT_UNL_IGNORE (2041L)\n+#define FLM_STAT_UNL_IGNORE_CNT (2042L)\n+#define FLM_STA_DATA (2043L)\n+#define FLM_STA_DATA_EOR (2044L)\n+#define FLM_STA_DATA_ID (2045L)\n+#define FLM_STA_DATA_LDS (2046L)\n+#define FLM_STA_DATA_LFS (2047L)\n+#define FLM_STA_DATA_LIS (2048L)\n+#define FLM_STA_DATA_PDS (2049L)\n+#define FLM_STA_DATA_PIS (2050L)\n+#define FLM_STA_DATA_RDS (2051L)\n+#define FLM_STA_DATA_RIS (2052L)\n+#define FLM_STA_DATA_UDS (2053L)\n+#define FLM_STA_DATA_UIS (2054L)\n+#define FLM_TIMEOUT (2055L)\n+#define FLM_TIMEOUT_T (2056L)\n+#define FLM_TRSWIN (2057L)\n+#define FLM_TRSWIN_S (2058L)\n+#define FLM_TRTWIN (2059L)\n+#define FLM_TRTWIN_T (2060L)\n+/* GFG */\n+#define GFG_BURSTSIZE0 (2061L)\n+#define GFG_BURSTSIZE0_VAL (2062L)\n+#define GFG_BURSTSIZE1 (2063L)\n+#define GFG_BURSTSIZE1_VAL (2064L)\n+#define GFG_BURSTSIZE2 (2065L)\n+#define GFG_BURSTSIZE2_VAL (2066L)\n+#define GFG_BURSTSIZE3 (2067L)\n+#define GFG_BURSTSIZE3_VAL (2068L)\n+#define GFG_BURSTSIZE4 (2069L)\n+#define GFG_BURSTSIZE4_VAL (2070L)\n+#define GFG_BURSTSIZE5 (2071L)\n+#define GFG_BURSTSIZE5_VAL (2072L)\n+#define GFG_BURSTSIZE6 (2073L)\n+#define GFG_BURSTSIZE6_VAL (2074L)\n+#define GFG_BURSTSIZE7 (2075L)\n+#define GFG_BURSTSIZE7_VAL (2076L)\n+#define GFG_CTRL0 (2077L)\n+#define GFG_CTRL0_ENABLE (2078L)\n+#define GFG_CTRL0_MODE (2079L)\n+#define GFG_CTRL0_PRBS_EN (2080L)\n+#define GFG_CTRL0_SIZE (2081L)\n+#define GFG_CTRL1 (2082L)\n+#define GFG_CTRL1_ENABLE (2083L)\n+#define GFG_CTRL1_MODE (2084L)\n+#define GFG_CTRL1_PRBS_EN (2085L)\n+#define GFG_CTRL1_SIZE (2086L)\n+#define GFG_CTRL2 (2087L)\n+#define GFG_CTRL2_ENABLE (2088L)\n+#define GFG_CTRL2_MODE (2089L)\n+#define GFG_CTRL2_PRBS_EN (2090L)\n+#define GFG_CTRL2_SIZE (2091L)\n+#define GFG_CTRL3 (2092L)\n+#define GFG_CTRL3_ENABLE (2093L)\n+#define GFG_CTRL3_MODE (2094L)\n+#define GFG_CTRL3_PRBS_EN (2095L)\n+#define GFG_CTRL3_SIZE (2096L)\n+#define GFG_CTRL4 (2097L)\n+#define GFG_CTRL4_ENABLE (2098L)\n+#define GFG_CTRL4_MODE (2099L)\n+#define GFG_CTRL4_PRBS_EN (2100L)\n+#define GFG_CTRL4_SIZE (2101L)\n+#define GFG_CTRL5 (2102L)\n+#define GFG_CTRL5_ENABLE (2103L)\n+#define GFG_CTRL5_MODE (2104L)\n+#define GFG_CTRL5_PRBS_EN (2105L)\n+#define GFG_CTRL5_SIZE (2106L)\n+#define GFG_CTRL6 (2107L)\n+#define GFG_CTRL6_ENABLE (2108L)\n+#define GFG_CTRL6_MODE (2109L)\n+#define GFG_CTRL6_PRBS_EN (2110L)\n+#define GFG_CTRL6_SIZE (2111L)\n+#define GFG_CTRL7 (2112L)\n+#define GFG_CTRL7_ENABLE (2113L)\n+#define GFG_CTRL7_MODE (2114L)\n+#define GFG_CTRL7_PRBS_EN (2115L)\n+#define GFG_CTRL7_SIZE (2116L)\n+#define GFG_RUN0 (2117L)\n+#define GFG_RUN0_RUN (2118L)\n+#define GFG_RUN1 (2119L)\n+#define GFG_RUN1_RUN (2120L)\n+#define GFG_RUN2 (2121L)\n+#define GFG_RUN2_RUN (2122L)\n+#define GFG_RUN3 (2123L)\n+#define GFG_RUN3_RUN (2124L)\n+#define GFG_RUN4 (2125L)\n+#define GFG_RUN4_RUN (2126L)\n+#define GFG_RUN5 (2127L)\n+#define GFG_RUN5_RUN (2128L)\n+#define GFG_RUN6 (2129L)\n+#define GFG_RUN6_RUN (2130L)\n+#define GFG_RUN7 (2131L)\n+#define GFG_RUN7_RUN (2132L)\n+#define GFG_SIZEMASK0 (2133L)\n+#define GFG_SIZEMASK0_VAL (2134L)\n+#define GFG_SIZEMASK1 (2135L)\n+#define GFG_SIZEMASK1_VAL (2136L)\n+#define GFG_SIZEMASK2 (2137L)\n+#define GFG_SIZEMASK2_VAL (2138L)\n+#define GFG_SIZEMASK3 (2139L)\n+#define GFG_SIZEMASK3_VAL (2140L)\n+#define GFG_SIZEMASK4 (2141L)\n+#define GFG_SIZEMASK4_VAL (2142L)\n+#define GFG_SIZEMASK5 (2143L)\n+#define GFG_SIZEMASK5_VAL (2144L)\n+#define GFG_SIZEMASK6 (2145L)\n+#define GFG_SIZEMASK6_VAL (2146L)\n+#define GFG_SIZEMASK7 (2147L)\n+#define GFG_SIZEMASK7_VAL (2148L)\n+#define GFG_STREAMID0 (2149L)\n+#define GFG_STREAMID0_VAL (2150L)\n+#define GFG_STREAMID1 (2151L)\n+#define GFG_STREAMID1_VAL (2152L)\n+#define GFG_STREAMID2 (2153L)\n+#define GFG_STREAMID2_VAL (2154L)\n+#define GFG_STREAMID3 (2155L)\n+#define GFG_STREAMID3_VAL (2156L)\n+#define GFG_STREAMID4 (2157L)\n+#define GFG_STREAMID4_VAL (2158L)\n+#define GFG_STREAMID5 (2159L)\n+#define GFG_STREAMID5_VAL (2160L)\n+#define GFG_STREAMID6 (2161L)\n+#define GFG_STREAMID6_VAL (2162L)\n+#define GFG_STREAMID7 (2163L)\n+#define GFG_STREAMID7_VAL (2164L)\n+/* GMF */\n+#define GMF_CTRL (2165L)\n+#define GMF_CTRL_ENABLE (2166L)\n+#define GMF_CTRL_FCS_ALWAYS (2167L)\n+#define GMF_CTRL_IFG_AUTO_ADJUST_ENABLE (2168L)\n+#define GMF_CTRL_IFG_ENABLE (2169L)\n+#define GMF_CTRL_IFG_TX_NOW_ALWAYS (2170L)\n+#define GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE (2171L)\n+#define GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK (2172L)\n+#define GMF_CTRL_IFG_TX_ON_TS_ALWAYS (2173L)\n+#define GMF_CTRL_TS_INJECT_ALWAYS (2174L)\n+#define GMF_CTRL_TS_INJECT_DUAL_STEP (2175L)\n+#define GMF_DEBUG_LANE_MARKER (2176L)\n+#define GMF_DEBUG_LANE_MARKER_COMPENSATION (2177L)\n+#define GMF_IFG_MAX_ADJUST_SLACK (2178L)\n+#define GMF_IFG_MAX_ADJUST_SLACK_SLACK (2179L)\n+#define GMF_IFG_SET_CLOCK_DELTA (2180L)\n+#define GMF_IFG_SET_CLOCK_DELTA_DELTA (2181L)\n+#define GMF_IFG_SET_CLOCK_DELTA_ADJUST (2182L)\n+#define GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA (2183L)\n+#define GMF_IFG_TX_NOW_ON_TS (2184L)\n+#define GMF_IFG_TX_NOW_ON_TS_TS (2185L)\n+#define GMF_SPEED (2186L)\n+#define GMF_SPEED_IFG_SPEED (2187L)\n+#define GMF_STAT (2188L)\n+#define GMF_STAT_CTRL_EMPTY (2189L)\n+#define GMF_STAT_DATA_CTRL_EMPTY (2190L)\n+#define GMF_STAT_SB_EMPTY (2191L)\n+#define GMF_STAT_CTRL (2192L)\n+#define GMF_STAT_CTRL_FILL_LEVEL (2193L)\n+#define GMF_STAT_DATA0 (2194L)\n+#define GMF_STAT_DATA0_EMPTY (2195L)\n+#define GMF_STAT_DATA1 (2196L)\n+#define GMF_STAT_DATA1_EMPTY (2197L)\n+#define GMF_STAT_DATA_BUFFER (2198L)\n+#define GMF_STAT_DATA_BUFFER_FREE (2199L)\n+#define GMF_STAT_DATA_BUFFER_USED (2200L)\n+#define GMF_STAT_MAX_DELAYED_PKT (2201L)\n+#define GMF_STAT_MAX_DELAYED_PKT_NS (2202L)\n+#define GMF_STAT_NEXT_PKT (2203L)\n+#define GMF_STAT_NEXT_PKT_NS (2204L)\n+#define GMF_STAT_STICKY (2205L)\n+#define GMF_STAT_STICKY_DATA_UNDERFLOWED (2206L)\n+#define GMF_STAT_STICKY_IFG_ADJUSTED (2207L)\n+#define GMF_TS_INJECT (2208L)\n+#define GMF_TS_INJECT_OFFSET (2209L)\n+#define GMF_TS_INJECT_POS (2210L)\n+/* GPIO_PHY */\n+#define GPIO_PHY_CFG (2211L)\n+#define GPIO_PHY_CFG_E_PORT0_RXLOS (2212L)\n+#define GPIO_PHY_CFG_E_PORT1_RXLOS (2213L)\n+#define GPIO_PHY_CFG_PORT0_INT_B (2214L)\n+#define GPIO_PHY_CFG_PORT0_LPMODE (2215L)\n+#define GPIO_PHY_CFG_PORT0_MODPRS_B (2216L)\n+#define GPIO_PHY_CFG_PORT0_PLL_INTR (2217L)\n+#define GPIO_PHY_CFG_PORT0_RESET_B (2218L)\n+#define GPIO_PHY_CFG_PORT1_INT_B (2219L)\n+#define GPIO_PHY_CFG_PORT1_LPMODE (2220L)\n+#define GPIO_PHY_CFG_PORT1_MODPRS_B (2221L)\n+#define GPIO_PHY_CFG_PORT1_PLL_INTR (2222L)\n+#define GPIO_PHY_CFG_PORT1_RESET_B (2223L)\n+#define GPIO_PHY_GPIO (2224L)\n+#define GPIO_PHY_GPIO_E_PORT0_RXLOS (2225L)\n+#define GPIO_PHY_GPIO_E_PORT1_RXLOS (2226L)\n+#define GPIO_PHY_GPIO_PORT0_INT_B (2227L)\n+#define GPIO_PHY_GPIO_PORT0_LPMODE (2228L)\n+#define GPIO_PHY_GPIO_PORT0_MODPRS_B (2229L)\n+#define GPIO_PHY_GPIO_PORT0_PLL_INTR (2230L)\n+#define GPIO_PHY_GPIO_PORT0_RESET_B (2231L)\n+#define GPIO_PHY_GPIO_PORT1_INT_B (2232L)\n+#define GPIO_PHY_GPIO_PORT1_LPMODE (2233L)\n+#define GPIO_PHY_GPIO_PORT1_MODPRS_B (2234L)\n+#define GPIO_PHY_GPIO_PORT1_PLL_INTR (2235L)\n+#define GPIO_PHY_GPIO_PORT1_RESET_B (2236L)\n+/* GPIO_PHY_PORTS */\n+#define GPIO_PHY_PORTS_CFG (2237L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT0_RXLOS (2238L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT0_TXDISABLE (2239L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT0_TXFAULT (2240L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT1_RXLOS (2241L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT1_TXDISABLE (2242L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT1_TXFAULT (2243L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT2_RXLOS (2244L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT2_TXDISABLE (2245L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT2_TXFAULT (2246L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT3_RXLOS (2247L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT3_TXDISABLE (2248L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT3_TXFAULT (2249L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT4_RXLOS (2250L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT4_TXDISABLE (2251L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT4_TXFAULT (2252L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT5_RXLOS (2253L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT5_TXDISABLE (2254L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT5_TXFAULT (2255L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT6_RXLOS (2256L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT6_TXDISABLE (2257L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT6_TXFAULT (2258L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT7_RXLOS (2259L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT7_TXDISABLE (2260L)\n+#define GPIO_PHY_PORTS_CFG_E_PORT7_TXFAULT (2261L)\n+#define GPIO_PHY_PORTS_GPIO (2262L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT0_RXLOS (2263L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXDISABLE (2264L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT0_TXFAULT (2265L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT1_RXLOS (2266L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXDISABLE (2267L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT1_TXFAULT (2268L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT2_RXLOS (2269L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXDISABLE (2270L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT2_TXFAULT (2271L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT3_RXLOS (2272L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXDISABLE (2273L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT3_TXFAULT (2274L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT4_RXLOS (2275L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXDISABLE (2276L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT4_TXFAULT (2277L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT5_RXLOS (2278L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXDISABLE (2279L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT5_TXFAULT (2280L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT6_RXLOS (2281L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXDISABLE (2282L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT6_TXFAULT (2283L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT7_RXLOS (2284L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXDISABLE (2285L)\n+#define GPIO_PHY_PORTS_GPIO_E_PORT7_TXFAULT (2286L)\n+/* GPIO_SFPP */\n+#define GPIO_SFPP_CFG (2287L)\n+#define GPIO_SFPP_CFG_ABS (2288L)\n+#define GPIO_SFPP_CFG_RS (2289L)\n+#define GPIO_SFPP_CFG_RXLOS (2290L)\n+#define GPIO_SFPP_CFG_TXDISABLE (2291L)\n+#define GPIO_SFPP_CFG_TXFAULT (2292L)\n+#define GPIO_SFPP_GPIO (2293L)\n+#define GPIO_SFPP_GPIO_ABS (2294L)\n+#define GPIO_SFPP_GPIO_RS (2295L)\n+#define GPIO_SFPP_GPIO_RXLOS (2296L)\n+#define GPIO_SFPP_GPIO_TXDISABLE (2297L)\n+#define GPIO_SFPP_GPIO_TXFAULT (2298L)\n+/* HFU */\n+#define HFU_RCP_CTRL (2381L)\n+#define HFU_RCP_CTRL_ADR (2382L)\n+#define HFU_RCP_CTRL_CNT (2383L)\n+#define HFU_RCP_DATA (2384L)\n+#define HFU_RCP_DATA_CSINF (2385L)\n+#define HFU_RCP_DATA_IL3OFS (2386L)\n+#define HFU_RCP_DATA_IL4OFS (2387L)\n+#define HFU_RCP_DATA_L3FRAG (2388L)\n+#define HFU_RCP_DATA_L3PRT (2389L)\n+#define HFU_RCP_DATA_L4PRT (2390L)\n+#define HFU_RCP_DATA_LEN_A_ADD_DYN (2391L)\n+#define HFU_RCP_DATA_LEN_A_ADD_OFS (2392L)\n+#define HFU_RCP_DATA_LEN_A_OL4LEN (2393L)\n+#define HFU_RCP_DATA_LEN_A_POS_DYN (2394L)\n+#define HFU_RCP_DATA_LEN_A_POS_OFS (2395L)\n+#define HFU_RCP_DATA_LEN_A_SUB_DYN (2396L)\n+#define HFU_RCP_DATA_LEN_A_WR (2397L)\n+#define HFU_RCP_DATA_LEN_B_ADD_DYN (2398L)\n+#define HFU_RCP_DATA_LEN_B_ADD_OFS (2399L)\n+#define HFU_RCP_DATA_LEN_B_POS_DYN (2400L)\n+#define HFU_RCP_DATA_LEN_B_POS_OFS (2401L)\n+#define HFU_RCP_DATA_LEN_B_SUB_DYN (2402L)\n+#define HFU_RCP_DATA_LEN_B_WR (2403L)\n+#define HFU_RCP_DATA_LEN_C_ADD_DYN (2404L)\n+#define HFU_RCP_DATA_LEN_C_ADD_OFS (2405L)\n+#define HFU_RCP_DATA_LEN_C_POS_DYN (2406L)\n+#define HFU_RCP_DATA_LEN_C_POS_OFS (2407L)\n+#define HFU_RCP_DATA_LEN_C_SUB_DYN (2408L)\n+#define HFU_RCP_DATA_LEN_C_WR (2409L)\n+#define HFU_RCP_DATA_OL3OFS (2410L)\n+#define HFU_RCP_DATA_OL4OFS (2411L)\n+#define HFU_RCP_DATA_TTL_POS_DYN (2412L)\n+#define HFU_RCP_DATA_TTL_POS_OFS (2413L)\n+#define HFU_RCP_DATA_TTL_WR (2414L)\n+#define HFU_RCP_DATA_TUNNEL (2415L)\n+/* HIF */\n+#define HIF_BUILD_TIME (2416L)\n+#define HIF_BUILD_TIME_TIME (2417L)\n+#define HIF_CONFIG (2418L)\n+#define HIF_CONFIG_EXT_TAG (2419L)\n+#define HIF_CONFIG_MAX_READ (2420L)\n+#define HIF_CONFIG_MAX_TLP (2421L)\n+#define HIF_CONTROL (2422L)\n+#define HIF_CONTROL_BLESSED (2423L)\n+#define HIF_CONTROL_WRAW (2424L)\n+#define HIF_PROD_ID_EX (2425L)\n+#define HIF_PROD_ID_EX_LAYOUT (2426L)\n+#define HIF_PROD_ID_EX_LAYOUT_VERSION (2427L)\n+#define HIF_PROD_ID_EX_RESERVED (2428L)\n+#define HIF_PROD_ID_EXT (2429L)\n+#define HIF_PROD_ID_EXT_LAYOUT (2430L)\n+#define HIF_PROD_ID_EXT_LAYOUT_VERSION (2431L)\n+#define HIF_PROD_ID_EXT_RESERVED (2432L)\n+#define HIF_PROD_ID_LSB (2433L)\n+#define HIF_PROD_ID_LSB_GROUP_ID (2434L)\n+#define HIF_PROD_ID_LSB_REV_ID (2435L)\n+#define HIF_PROD_ID_LSB_VER_ID (2436L)\n+#define HIF_PROD_ID_MSB (2437L)\n+#define HIF_PROD_ID_MSB_BUILD_NO (2438L)\n+#define HIF_PROD_ID_MSB_PATCH_NO (2439L)\n+#define HIF_PROD_ID_MSB_TYPE_ID (2440L)\n+#define HIF_SAMPLE_TIME (2441L)\n+#define HIF_SAMPLE_TIME_SAMPLE_TIME (2442L)\n+#define HIF_STATUS (2443L)\n+#define HIF_STATUS_RD_ERR (2444L)\n+#define HIF_STATUS_TAGS_IN_USE (2445L)\n+#define HIF_STATUS_WR_ERR (2446L)\n+#define HIF_STAT_CTRL (2447L)\n+#define HIF_STAT_CTRL_STAT_ENA (2448L)\n+#define HIF_STAT_CTRL_STAT_REQ (2449L)\n+#define HIF_STAT_REFCLK (2450L)\n+#define HIF_STAT_REFCLK_REFCLK250 (2451L)\n+#define HIF_STAT_RX (2452L)\n+#define HIF_STAT_RX_COUNTER (2453L)\n+#define HIF_STAT_TX (2454L)\n+#define HIF_STAT_TX_COUNTER (2455L)\n+#define HIF_TEST0 (2456L)\n+#define HIF_TEST0_DATA (2457L)\n+#define HIF_TEST1 (2458L)\n+#define HIF_TEST1_DATA (2459L)\n+#define HIF_TEST2 (2460L)\n+#define HIF_TEST2_DATA (2461L)\n+#define HIF_TEST3 (2462L)\n+#define HIF_TEST3_DATA (2463L)\n+#define HIF_UUID0 (2464L)\n+#define HIF_UUID0_UUID0 (2465L)\n+#define HIF_UUID1 (2466L)\n+#define HIF_UUID1_UUID1 (2467L)\n+#define HIF_UUID2 (2468L)\n+#define HIF_UUID2_UUID2 (2469L)\n+#define HIF_UUID3 (2470L)\n+#define HIF_UUID3_UUID3 (2471L)\n+/* HSH */\n+#define HSH_RCP_CTRL (2472L)\n+#define HSH_RCP_CTRL_ADR (2473L)\n+#define HSH_RCP_CTRL_CNT (2474L)\n+#define HSH_RCP_DATA (2475L)\n+#define HSH_RCP_DATA_AUTO_IPV4_MASK (2476L)\n+#define HSH_RCP_DATA_HSH_TYPE (2477L)\n+#define HSH_RCP_DATA_HSH_VALID (2478L)\n+#define HSH_RCP_DATA_K (2479L)\n+#define HSH_RCP_DATA_LOAD_DIST_TYPE (2480L)\n+#define HSH_RCP_DATA_MAC_PORT_MASK (2481L)\n+#define HSH_RCP_DATA_P_MASK (2482L)\n+#define HSH_RCP_DATA_QW0_OFS (2483L)\n+#define HSH_RCP_DATA_QW0_PE (2484L)\n+#define HSH_RCP_DATA_QW4_OFS (2485L)\n+#define HSH_RCP_DATA_QW4_PE (2486L)\n+#define HSH_RCP_DATA_SEED (2487L)\n+#define HSH_RCP_DATA_SORT (2488L)\n+#define HSH_RCP_DATA_TNL_P (2489L)\n+#define HSH_RCP_DATA_TOEPLITZ (2490L)\n+#define HSH_RCP_DATA_W8_OFS (2491L)\n+#define HSH_RCP_DATA_W8_PE (2492L)\n+#define HSH_RCP_DATA_W8_SORT (2493L)\n+#define HSH_RCP_DATA_W9_OFS (2494L)\n+#define HSH_RCP_DATA_W9_P (2495L)\n+#define HSH_RCP_DATA_W9_PE (2496L)\n+#define HSH_RCP_DATA_W9_SORT (2497L)\n+#define HSH_RCP_DATA_WORD_MASK (2498L)\n+/* HST */\n+#define HST_RCP_CTRL (2499L)\n+#define HST_RCP_CTRL_ADR (2500L)\n+#define HST_RCP_CTRL_CNT (2501L)\n+#define HST_RCP_DATA (2502L)\n+#define HST_RCP_DATA_END_DYN (2503L)\n+#define HST_RCP_DATA_END_OFS (2504L)\n+#define HST_RCP_DATA_MODIF0_CMD (2505L)\n+#define HST_RCP_DATA_MODIF0_DYN (2506L)\n+#define HST_RCP_DATA_MODIF0_OFS (2507L)\n+#define HST_RCP_DATA_MODIF0_VALUE (2508L)\n+#define HST_RCP_DATA_MODIF1_CMD (2509L)\n+#define HST_RCP_DATA_MODIF1_DYN (2510L)\n+#define HST_RCP_DATA_MODIF1_OFS (2511L)\n+#define HST_RCP_DATA_MODIF1_VALUE (2512L)\n+#define HST_RCP_DATA_MODIF2_CMD (2513L)\n+#define HST_RCP_DATA_MODIF2_DYN (2514L)\n+#define HST_RCP_DATA_MODIF2_OFS (2515L)\n+#define HST_RCP_DATA_MODIF2_VALUE (2516L)\n+#define HST_RCP_DATA_START_DYN (2517L)\n+#define HST_RCP_DATA_START_OFS (2518L)\n+#define HST_RCP_DATA_STRIP_MODE (2519L)\n+/* ICORE_10G */\n+#define ICORE_10G_INDIR_CTRL (2549L)\n+#define ICORE_10G_INDIR_CTRL_RD_ENABLE (2550L)\n+#define ICORE_10G_INDIR_CTRL_RD_READY (2551L)\n+#define ICORE_10G_INDIR_CTRL_SUB_ADDR (2552L)\n+#define ICORE_10G_INDIR_DATA (2553L)\n+#define ICORE_10G_INDIR_DATA_DATA (2554L)\n+#define ICORE_10G_MISC_CTRL (2555L)\n+#define ICORE_10G_MISC_CTRL_LINE_LOOP (2556L)\n+#define ICORE_10G_MISC_CTRL_LINK_LATENCY (2557L)\n+#define ICORE_10G_MISC_CTRL_RES_MAC_RX (2558L)\n+#define ICORE_10G_MISC_CTRL_RES_MAC_TX (2559L)\n+#define ICORE_10G_MISC_CTRL_SERIAL_LOOP (2560L)\n+#define ICORE_10G_MISC_CTRL_SET_LOCK2DATA (2561L)\n+#define ICORE_10G_MISC_CTRL_SET_LOCK2REF (2562L)\n+#define ICORE_10G_PHY_STATUS (2563L)\n+#define ICORE_10G_PHY_STATUS_BLOCK_LOCK (2564L)\n+#define ICORE_10G_PHY_STATUS_HI_BER (2565L)\n+#define ICORE_10G_PHY_STATUS_HI_BER_CHANGED (2566L)\n+#define ICORE_10G_PHY_STATUS_LINK_STATE (2567L)\n+#define ICORE_10G_PHY_STATUS_LINK_STATE_CHANGED (2568L)\n+#define ICORE_10G_PHY_STATUS_RXCLK_LOCKED (2569L)\n+#define ICORE_10G_PHY_STATUS_RXCLK_LOCKED2DATA (2570L)\n+#define ICORE_10G_PHY_STATUS_RX_CAL_BUSY (2571L)\n+#define ICORE_10G_PHY_STATUS_TXCLK_LOCKED (2572L)\n+#define ICORE_10G_PHY_STATUS_TX_CAL_BUSY (2573L)\n+#define ICORE_10G_TFG_ADDR (2574L)\n+#define ICORE_10G_TFG_ADDR_ADR (2575L)\n+#define ICORE_10G_TFG_ADDR_RDENA (2576L)\n+#define ICORE_10G_TFG_ADDR_RD_DONE (2577L)\n+#define ICORE_10G_TFG_CTRL (2578L)\n+#define ICORE_10G_TFG_CTRL_ID_ENA (2579L)\n+#define ICORE_10G_TFG_CTRL_ID_POS (2580L)\n+#define ICORE_10G_TFG_CTRL_RESTART (2581L)\n+#define ICORE_10G_TFG_CTRL_TG_ACT (2582L)\n+#define ICORE_10G_TFG_CTRL_TG_ENA (2583L)\n+#define ICORE_10G_TFG_CTRL_TIME_MODE (2584L)\n+#define ICORE_10G_TFG_CTRL_WRAP (2585L)\n+#define ICORE_10G_TFG_DATA (2586L)\n+#define ICORE_10G_TFG_DATA_ID (2587L)\n+#define ICORE_10G_TFG_DATA_LENGTH (2588L)\n+#define ICORE_10G_TFG_FRAME_HDR_0 (2589L)\n+#define ICORE_10G_TFG_FRAME_HDR_0_HDR (2590L)\n+#define ICORE_10G_TFG_FRAME_HDR_1 (2591L)\n+#define ICORE_10G_TFG_FRAME_HDR_1_HDR (2592L)\n+#define ICORE_10G_TFG_FRAME_HDR_2 (2593L)\n+#define ICORE_10G_TFG_FRAME_HDR_2_HDR (2594L)\n+#define ICORE_10G_TFG_FRAME_HDR_3 (2595L)\n+#define ICORE_10G_TFG_FRAME_HDR_3_HDR (2596L)\n+#define ICORE_10G_TFG_REPETITION (2597L)\n+#define ICORE_10G_TFG_REPETITION_CNT (2598L)\n+/* IFR */\n+#define IFR_RCP_CTRL (2642L)\n+#define IFR_RCP_CTRL_ADR (2643L)\n+#define IFR_RCP_CTRL_CNT (2644L)\n+#define IFR_RCP_DATA (2645L)\n+#define IFR_RCP_DATA_EN (2646L)\n+#define IFR_RCP_DATA_MTU (2647L)\n+/* IIC */\n+#define IIC_ADR (2648L)\n+#define IIC_ADR_SLV_ADR (2649L)\n+#define IIC_CR (2650L)\n+#define IIC_CR_EN (2651L)\n+#define IIC_CR_GC_EN (2652L)\n+#define IIC_CR_MSMS (2653L)\n+#define IIC_CR_RST (2654L)\n+#define IIC_CR_RSTA (2655L)\n+#define IIC_CR_TX (2656L)\n+#define IIC_CR_TXAK (2657L)\n+#define IIC_CR_TXFIFO_RESET (2658L)\n+#define IIC_DGIE (2659L)\n+#define IIC_DGIE_GIE (2660L)\n+#define IIC_GPO (2661L)\n+#define IIC_GPO_GPO_VAL (2662L)\n+#define IIC_IER (2663L)\n+#define IIC_IER_INT0 (2664L)\n+#define IIC_IER_INT1 (2665L)\n+#define IIC_IER_INT2 (2666L)\n+#define IIC_IER_INT3 (2667L)\n+#define IIC_IER_INT4 (2668L)\n+#define IIC_IER_INT5 (2669L)\n+#define IIC_IER_INT6 (2670L)\n+#define IIC_IER_INT7 (2671L)\n+#define IIC_ISR (2672L)\n+#define IIC_ISR_INT0 (2673L)\n+#define IIC_ISR_INT1 (2674L)\n+#define IIC_ISR_INT2 (2675L)\n+#define IIC_ISR_INT3 (2676L)\n+#define IIC_ISR_INT4 (2677L)\n+#define IIC_ISR_INT5 (2678L)\n+#define IIC_ISR_INT6 (2679L)\n+#define IIC_ISR_INT7 (2680L)\n+#define IIC_RX_FIFO (2681L)\n+#define IIC_RX_FIFO_RXDATA (2682L)\n+#define IIC_RX_FIFO_OCY (2683L)\n+#define IIC_RX_FIFO_OCY_OCY_VAL (2684L)\n+#define IIC_RX_FIFO_PIRQ (2685L)\n+#define IIC_RX_FIFO_PIRQ_CMP_VAL (2686L)\n+#define IIC_SOFTR (2687L)\n+#define IIC_SOFTR_RKEY (2688L)\n+#define IIC_SR (2689L)\n+#define IIC_SR_AAS (2690L)\n+#define IIC_SR_ABGC (2691L)\n+#define IIC_SR_BB (2692L)\n+#define IIC_SR_RXFIFO_EMPTY (2693L)\n+#define IIC_SR_RXFIFO_FULL (2694L)\n+#define IIC_SR_SRW (2695L)\n+#define IIC_SR_TXFIFO_EMPTY (2696L)\n+#define IIC_SR_TXFIFO_FULL (2697L)\n+#define IIC_TBUF (2698L)\n+#define IIC_TBUF_TBUF_VAL (2699L)\n+#define IIC_TEN_ADR (2700L)\n+#define IIC_TEN_ADR_MSB_SLV_ADR (2701L)\n+#define IIC_THDDAT (2702L)\n+#define IIC_THDDAT_THDDAT_VAL (2703L)\n+#define IIC_THDSTA (2704L)\n+#define IIC_THDSTA_THDSTA_VAL (2705L)\n+#define IIC_THIGH (2706L)\n+#define IIC_THIGH_THIGH_VAL (2707L)\n+#define IIC_TLOW (2708L)\n+#define IIC_TLOW_TLOW_VAL (2709L)\n+#define IIC_TSUDAT (2710L)\n+#define IIC_TSUDAT_TSUDAT_VAL (2711L)\n+#define IIC_TSUSTA (2712L)\n+#define IIC_TSUSTA_TSUSTA_VAL (2713L)\n+#define IIC_TSUSTO (2714L)\n+#define IIC_TSUSTO_TSUSTO_VAL (2715L)\n+#define IIC_TX_FIFO (2716L)\n+#define IIC_TX_FIFO_START (2717L)\n+#define IIC_TX_FIFO_STOP (2718L)\n+#define IIC_TX_FIFO_TXDATA (2719L)\n+#define IIC_TX_FIFO_OCY (2720L)\n+#define IIC_TX_FIFO_OCY_OCY_VAL (2721L)\n+/* INS */\n+#define INS_RCP_CTRL (2722L)\n+#define INS_RCP_CTRL_ADR (2723L)\n+#define INS_RCP_CTRL_CNT (2724L)\n+#define INS_RCP_DATA (2725L)\n+#define INS_RCP_DATA_DYN (2726L)\n+#define INS_RCP_DATA_LEN (2727L)\n+#define INS_RCP_DATA_OFS (2728L)\n+/* IOA */\n+#define IOA_RECIPE_CTRL (2778L)\n+#define IOA_RECIPE_CTRL_ADR (2779L)\n+#define IOA_RECIPE_CTRL_CNT (2780L)\n+#define IOA_RECIPE_DATA (2781L)\n+#define IOA_RECIPE_DATA_QUEUE_ID (2782L)\n+#define IOA_RECIPE_DATA_QUEUE_OVERRIDE_EN (2783L)\n+#define IOA_RECIPE_DATA_TUNNEL_POP (2784L)\n+#define IOA_RECIPE_DATA_VLAN_DEI (2785L)\n+#define IOA_RECIPE_DATA_VLAN_PCP (2786L)\n+#define IOA_RECIPE_DATA_VLAN_POP (2787L)\n+#define IOA_RECIPE_DATA_VLAN_PUSH (2788L)\n+#define IOA_RECIPE_DATA_VLAN_TPID_SEL (2789L)\n+#define IOA_RECIPE_DATA_VLAN_VID (2790L)\n+#define IOA_ROA_EPP_CTRL (2791L)\n+#define IOA_ROA_EPP_CTRL_ADR (2792L)\n+#define IOA_ROA_EPP_CTRL_CNT (2793L)\n+#define IOA_ROA_EPP_DATA (2794L)\n+#define IOA_ROA_EPP_DATA_PUSH_TUNNEL (2795L)\n+#define IOA_ROA_EPP_DATA_TX_PORT (2796L)\n+#define IOA_VLAN_TPID_SPECIAL (2797L)\n+#define IOA_VLAN_TPID_SPECIAL_CUSTTPID0 (2798L)\n+#define IOA_VLAN_TPID_SPECIAL_CUSTTPID1 (2799L)\n+/* IPF */\n+#define IPF_CTRL (2800L)\n+#define IPF_CTRL_ALL_UNM (2801L)\n+#define IPF_CTRL_ALL_UNM_INNER (2802L)\n+#define IPF_CTRL_DEL_UNM (2803L)\n+#define IPF_CTRL_ENABLE (2804L)\n+#define IPF_CTRL_FST_UNM (2805L)\n+#define IPF_CTRL_PASSIVE (2806L)\n+#define IPF_CTRL_PERSIST (2807L)\n+#define IPF_DEBUG (2808L)\n+#define IPF_DEBUG_FTF_N (2809L)\n+#define IPF_DEBUG_LIMIT_N (2810L)\n+#define IPF_EXPIRE (2811L)\n+#define IPF_EXPIRE_PERSIST (2812L)\n+#define IPF_EXPIRE_T (2813L)\n+#define IPF_FTF_DEBUG (2814L)\n+#define IPF_FTF_DEBUG_N (2815L)\n+#define IPF_RCP_CTRL (2816L)\n+#define IPF_RCP_CTRL_ADR (2817L)\n+#define IPF_RCP_CTRL_CNT (2818L)\n+#define IPF_RCP_DATA (2819L)\n+#define IPF_RCP_DATA_ALL_UNM (2820L)\n+#define IPF_RCP_DATA_COL_INH (2821L)\n+#define IPF_RCP_DATA_DEL_UNM (2822L)\n+#define IPF_RCP_DATA_DISC_INH (2823L)\n+#define IPF_RCP_DATA_DUP_INH (2824L)\n+#define IPF_RCP_DATA_ENABLE (2825L)\n+#define IPF_RCP_DATA_FST_UNM (2826L)\n+#define IPF_RCP_DATA_GROUP_ID (2827L)\n+#define IPF_RCP_DATA_HASH_CENC (2828L)\n+#define IPF_RCP_DATA_HSH_INH (2829L)\n+#define IPF_RCP_DATA_PORT_GROUP_ID (2830L)\n+#define IPF_RCP_DATA_QUEUE_INH (2831L)\n+#define IPF_RCP_DATA_UNMQ_HI (2832L)\n+#define IPF_RCP_DATA_UNMQ_LO (2833L)\n+#define IPF_RCP_DATA_UNM_FLAG_CENC (2834L)\n+#define IPF_SIZE_DEBUG (2835L)\n+#define IPF_SIZE_DEBUG_N (2836L)\n+#define IPF_STAT_MAX1 (2837L)\n+#define IPF_STAT_MAX1_N (2838L)\n+#define IPF_STAT_MAX2 (2839L)\n+#define IPF_STAT_MAX2_N (2840L)\n+#define IPF_STAT_MAX3 (2841L)\n+#define IPF_STAT_MAX3_N (2842L)\n+#define IPF_STAT_MAX4 (2843L)\n+#define IPF_STAT_MAX4_N (2844L)\n+#define IPF_TIMEOUT (2845L)\n+#define IPF_TIMEOUT_T (2846L)\n+#define IPF_UNMQ_CTRL (2847L)\n+#define IPF_UNMQ_CTRL_ADR (2848L)\n+#define IPF_UNMQ_CTRL_CNT (2849L)\n+#define IPF_UNMQ_DATA (2850L)\n+#define IPF_UNMQ_DATA_CENC (2851L)\n+#define IPF_UNMQ_DATA_EN (2852L)\n+#define IPF_UNMQ_DATA_ID (2853L)\n+#define IPF_UNM_FEED (2854L)\n+#define IPF_UNM_FEED_ADDR (2855L)\n+#define IPF_UNM_FEED_CNT (2856L)\n+#define IPF_UNM_FEED_FEED (2857L)\n+#define IPF_UNM_FEED_FEED_VALID (2858L)\n+#define IPF_UNM_FEED_RES1 (2859L)\n+#define IPF_UNM_FEED_RES2 (2860L)\n+#define IPF_UNM_FEED_RES3 (2861L)\n+/* KM */\n+#define KM_CAM_CTRL (2862L)\n+#define KM_CAM_CTRL_ADR (2863L)\n+#define KM_CAM_CTRL_CNT (2864L)\n+#define KM_CAM_DATA (2865L)\n+#define KM_CAM_DATA_FT0 (2866L)\n+#define KM_CAM_DATA_FT1 (2867L)\n+#define KM_CAM_DATA_FT2 (2868L)\n+#define KM_CAM_DATA_FT3 (2869L)\n+#define KM_CAM_DATA_FT4 (2870L)\n+#define KM_CAM_DATA_FT5 (2871L)\n+#define KM_CAM_DATA_W0 (2872L)\n+#define KM_CAM_DATA_W1 (2873L)\n+#define KM_CAM_DATA_W2 (2874L)\n+#define KM_CAM_DATA_W3 (2875L)\n+#define KM_CAM_DATA_W4 (2876L)\n+#define KM_CAM_DATA_W5 (2877L)\n+#define KM_RCP_CTRL (2878L)\n+#define KM_RCP_CTRL_ADR (2879L)\n+#define KM_RCP_CTRL_CNT (2880L)\n+#define KM_RCP_DATA (2881L)\n+#define KM_RCP_DATA_BANK_A (2882L)\n+#define KM_RCP_DATA_BANK_B (2883L)\n+#define KM_RCP_DATA_DUAL (2884L)\n+#define KM_RCP_DATA_DW0_B_DYN (2885L)\n+#define KM_RCP_DATA_DW0_B_OFS (2886L)\n+#define KM_RCP_DATA_DW10_DYN (2887L)\n+#define KM_RCP_DATA_DW10_OFS (2888L)\n+#define KM_RCP_DATA_DW10_SEL_A (2889L)\n+#define KM_RCP_DATA_DW10_SEL_B (2890L)\n+#define KM_RCP_DATA_DW2_B_DYN (2891L)\n+#define KM_RCP_DATA_DW2_B_OFS (2892L)\n+#define KM_RCP_DATA_DW8_B_DYN (2893L)\n+#define KM_RCP_DATA_DW8_B_OFS (2894L)\n+#define KM_RCP_DATA_DW8_DYN (2895L)\n+#define KM_RCP_DATA_DW8_OFS (2896L)\n+#define KM_RCP_DATA_DW8_SEL_A (2897L)\n+#define KM_RCP_DATA_DW8_SEL_B (2898L)\n+#define KM_RCP_DATA_EL_A (2899L)\n+#define KM_RCP_DATA_EL_B (2900L)\n+#define KM_RCP_DATA_FLOW_SET (2901L)\n+#define KM_RCP_DATA_FTM_A (2902L)\n+#define KM_RCP_DATA_FTM_B (2903L)\n+#define KM_RCP_DATA_INFO_A (2904L)\n+#define KM_RCP_DATA_INFO_B (2905L)\n+#define KM_RCP_DATA_KEYWAY_A (2906L)\n+#define KM_RCP_DATA_KEYWAY_B (2907L)\n+#define KM_RCP_DATA_KL_A (2908L)\n+#define KM_RCP_DATA_KL_B (2909L)\n+#define KM_RCP_DATA_MASK_A (2910L)\n+#define KM_RCP_DATA_MASK_B (2911L)\n+#define KM_RCP_DATA_PAIRED (2912L)\n+#define KM_RCP_DATA_QW0_B_DYN (2913L)\n+#define KM_RCP_DATA_QW0_B_OFS (2914L)\n+#define KM_RCP_DATA_QW0_DYN (2915L)\n+#define KM_RCP_DATA_QW0_OFS (2916L)\n+#define KM_RCP_DATA_QW0_SEL_A (2917L)\n+#define KM_RCP_DATA_QW0_SEL_B (2918L)\n+#define KM_RCP_DATA_QW4_B_DYN (2919L)\n+#define KM_RCP_DATA_QW4_B_OFS (2920L)\n+#define KM_RCP_DATA_QW4_DYN (2921L)\n+#define KM_RCP_DATA_QW4_OFS (2922L)\n+#define KM_RCP_DATA_QW4_SEL_A (2923L)\n+#define KM_RCP_DATA_QW4_SEL_B (2924L)\n+#define KM_RCP_DATA_SW4_B_DYN (2925L)\n+#define KM_RCP_DATA_SW4_B_OFS (2926L)\n+#define KM_RCP_DATA_SW5_B_DYN (2927L)\n+#define KM_RCP_DATA_SW5_B_OFS (2928L)\n+#define KM_RCP_DATA_SW8_B_DYN (2929L)\n+#define KM_RCP_DATA_SW8_B_OFS (2930L)\n+#define KM_RCP_DATA_SW8_DYN (2931L)\n+#define KM_RCP_DATA_SW8_OFS (2932L)\n+#define KM_RCP_DATA_SW8_SEL_A (2933L)\n+#define KM_RCP_DATA_SW8_SEL_B (2934L)\n+#define KM_RCP_DATA_SW9_B_DYN (2935L)\n+#define KM_RCP_DATA_SW9_B_OFS (2936L)\n+#define KM_RCP_DATA_SW9_DYN (2937L)\n+#define KM_RCP_DATA_SW9_OFS (2938L)\n+#define KM_RCP_DATA_SW9_SEL_A (2939L)\n+#define KM_RCP_DATA_SW9_SEL_B (2940L)\n+#define KM_RCP_DATA_SWX_CCH (2941L)\n+#define KM_RCP_DATA_SWX_OVS_SB (2942L)\n+#define KM_RCP_DATA_SWX_SEL_A (2943L)\n+#define KM_RCP_DATA_SWX_SEL_B (2944L)\n+#define KM_RCP_DATA_SYNERGY_MODE (2945L)\n+#define KM_STATUS (2946L)\n+#define KM_STATUS_TCQ_RDY (2947L)\n+#define KM_TCAM_CTRL (2948L)\n+#define KM_TCAM_CTRL_ADR (2949L)\n+#define KM_TCAM_CTRL_CNT (2950L)\n+#define KM_TCAM_DATA (2951L)\n+#define KM_TCAM_DATA_T (2952L)\n+#define KM_TCI_CTRL (2953L)\n+#define KM_TCI_CTRL_ADR (2954L)\n+#define KM_TCI_CTRL_CNT (2955L)\n+#define KM_TCI_DATA (2956L)\n+#define KM_TCI_DATA_COLOR (2957L)\n+#define KM_TCI_DATA_FT (2958L)\n+#define KM_TCQ_CTRL (2959L)\n+#define KM_TCQ_CTRL_ADR (2960L)\n+#define KM_TCQ_CTRL_CNT (2961L)\n+#define KM_TCQ_DATA (2962L)\n+#define KM_TCQ_DATA_BANK_MASK (2963L)\n+#define KM_TCQ_DATA_QUAL (2964L)\n+/* LAO */\n+/* MAC */\n+#define MAC_CONF_SERDES_BITFRAG (2965L)\n+#define MAC_CONF_SERDES_BITFRAG_BITFRAG (2966L)\n+#define MAC_CONF_SERDES_DELAY (2967L)\n+#define MAC_CONF_SERDES_DELAY_DELAY (2968L)\n+#define MAC_CONF_SERDES_REORDER (2969L)\n+#define MAC_CONF_SERDES_REORDER_REORDER (2970L)\n+#define MAC_FAULTY_BLK (2971L)\n+#define MAC_FAULTY_BLK_DATA (2972L)\n+#define MAC_HOST_STAT_BYTE_FILL (2973L)\n+#define MAC_HOST_STAT_BYTE_FILL_CNT (2974L)\n+#define MAC_INT (2975L)\n+#define MAC_INT_EN (2976L)\n+#define MAC_INT_MAX_PACE (2977L)\n+#define MAC_LINK_SUMMARY (2978L)\n+#define MAC_LINK_SUMMARY_ABS (2979L)\n+#define MAC_LINK_SUMMARY_GBOX_INTERR (2980L)\n+#define MAC_LINK_SUMMARY_GLB_ALARMN (2981L)\n+#define MAC_LINK_SUMMARY_LH_ABS (2982L)\n+#define MAC_LINK_SUMMARY_LH_GLB_ALARMN (2983L)\n+#define MAC_LINK_SUMMARY_LH_LOCAL_FAULT (2984L)\n+#define MAC_LINK_SUMMARY_LH_REMOTE_FAULT (2985L)\n+#define MAC_LINK_SUMMARY_LH_RX_LOS (2986L)\n+#define MAC_LINK_SUMMARY_LINK_DOWN_CNT (2987L)\n+#define MAC_LINK_SUMMARY_LL_PHY_LINK_STATE (2988L)\n+#define MAC_LINK_SUMMARY_LOCAL_FAULT (2989L)\n+#define MAC_LINK_SUMMARY_NT_PHY_LINK_STATE (2990L)\n+#define MAC_LINK_SUMMARY_REMOTE_FAULT (2991L)\n+#define MAC_LINK_SUMMARY_RX_LOS (2992L)\n+#define MAC_MAC_STAT_BYTE (2993L)\n+#define MAC_MAC_STAT_BYTE_CNT (2994L)\n+#define MAC_MAC_STAT_CRC (2995L)\n+#define MAC_MAC_STAT_CRC_CNT (2996L)\n+#define MAC_MAC_STAT_CV (2997L)\n+#define MAC_MAC_STAT_CV_CNT (2998L)\n+#define MAC_MAC_STAT_FRAME (2999L)\n+#define MAC_MAC_STAT_FRAME_CNT (3000L)\n+#define MAC_MAC_STAT_MICRO_DROP (3001L)\n+#define MAC_MAC_STAT_MICRO_DROP_CNT (3002L)\n+#define MAC_MAC_STAT_RATE_DROP (3003L)\n+#define MAC_MAC_STAT_RATE_DROP_CNT (3004L)\n+#define MAC_MAC_STAT_TRUNC (3005L)\n+#define MAC_MAC_STAT_TRUNC_CNT (3006L)\n+#define MAC_MDS_CEN_VAL (3007L)\n+#define MAC_MDS_CEN_VAL_VAL (3008L)\n+#define MAC_MDS_CONF (3009L)\n+#define MAC_MDS_CONF_CENTER_REC_ENA (3010L)\n+#define MAC_MDS_CONF_CLR_STAT (3011L)\n+#define MAC_MDS_CONF_ENA_TS_MOD (3012L)\n+#define MAC_MDS_CONF_REC_ENA (3013L)\n+#define MAC_MDS_CONF_TIME_MODE (3014L)\n+#define MAC_MDS_DATA (3015L)\n+#define MAC_MDS_DATA_DATA (3016L)\n+#define MAC_MDS_FRAMES (3017L)\n+#define MAC_MDS_FRAMES_CNT (3018L)\n+#define MAC_MDS_MAX (3019L)\n+#define MAC_MDS_MAX_MAX (3020L)\n+#define MAC_MDS_MIN (3021L)\n+#define MAC_MDS_MIN_MIN (3022L)\n+#define MAC_MDS_STAT (3023L)\n+#define MAC_MDS_STAT_CLR_BUSY (3024L)\n+#define MAC_MDS_STAT_HIT_MAX (3025L)\n+#define MAC_MDS_STAT_HIT_MIN (3026L)\n+#define MAC_MDS_VAL_REC (3027L)\n+#define MAC_MDS_VAL_REC_VALUE (3028L)\n+#define MAC_MDS_VAL_REC_FRAME (3029L)\n+#define MAC_MDS_VAL_REC_FRAME_VALUE (3030L)\n+#define MAC_NT_PORT_CTRL (3031L)\n+#define MAC_NT_PORT_CTRL_LED_MODE (3032L)\n+#define MAC_RAM_MDS_ADDR (3033L)\n+#define MAC_RAM_MDS_ADDR_ADR (3034L)\n+#define MAC_RAM_MDS_ADDR_CLR_RAM (3035L)\n+#define MAC_RAM_MDS_ADDR_RD_DONE (3036L)\n+#define MAC_RAM_MDS_ADDR_RD_ENA (3037L)\n+#define MAC_RAW_ADDR (3038L)\n+#define MAC_RAW_ADDR_ADR (3039L)\n+#define MAC_RAW_ADDR_RDENA (3040L)\n+#define MAC_RAW_ADDR_RD_DONE (3041L)\n+#define MAC_RAW_CTRL (3042L)\n+#define MAC_RAW_CTRL_OVERWR_LM (3043L)\n+#define MAC_RAW_CTRL_RESTART (3044L)\n+#define MAC_RAW_CTRL_TG_ACT (3045L)\n+#define MAC_RAW_CTRL_TG_ENA (3046L)\n+#define MAC_RAW_CTRL_WRAP (3047L)\n+#define MAC_RAW_DATA (3048L)\n+#define MAC_RAW_DATA_RAW_DATA (3049L)\n+#define MAC_RAW_REPETITION (3050L)\n+#define MAC_RAW_REPETITION_CNT (3051L)\n+#define MAC_RX_CONFIG (3052L)\n+#define MAC_RX_CONFIG_DESCRAMB (3053L)\n+#define MAC_RX_CONFIG_HOST_CLR_CNT (3054L)\n+#define MAC_RX_CONFIG_MAC_CLR_CNT (3055L)\n+#define MAC_RX_CONFIG_MIN_RX_FRAME (3056L)\n+#define MAC_RX_CONFIG_NT_DEBOUNCE_LATENCY (3057L)\n+#define MAC_RX_CONFIG_NT_FORCE_LINK_DOWN (3058L)\n+#define MAC_RX_CONFIG_NT_LINKUP_LATENCY (3059L)\n+#define MAC_RX_CONFIG_RST_BLK_ERR (3060L)\n+#define MAC_RX_CONFIG_RX_MAC_EN (3061L)\n+#define MAC_RX_CONFIG_TS_EOP (3062L)\n+#define MAC_RX_CONFIG_TXRX_LOOP (3063L)\n+#define MAC_RX_CONFIG2 (3064L)\n+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_INT (3065L)\n+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_LINK (3066L)\n+#define MAC_RX_CONFIG2_NT_MOD_ABS_MASK_RST (3067L)\n+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_INT (3068L)\n+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_LINK (3069L)\n+#define MAC_RX_CONFIG2_NT_RXLOS_MASK_RST (3070L)\n+#define MAC_RX_STATUS (3071L)\n+#define MAC_RX_STATUS_CORE_MODE (3072L)\n+#define MAC_RX_STATUS_LOCAL_FAULT (3073L)\n+#define MAC_RX_STATUS_REMOTE_FAULT (3074L)\n+#define MAC_RX_STATUS_RXTX_OVERFLOW (3075L)\n+#define MAC_RX_STATUS_VERSION (3076L)\n+#define MAC_TFG_ADDR (3077L)\n+#define MAC_TFG_ADDR_ADR (3078L)\n+#define MAC_TFG_ADDR_RDENA (3079L)\n+#define MAC_TFG_ADDR_RD_DONE (3080L)\n+#define MAC_TFG_CTRL (3081L)\n+#define MAC_TFG_CTRL_ID_ENA (3082L)\n+#define MAC_TFG_CTRL_ID_POS (3083L)\n+#define MAC_TFG_CTRL_RESTART (3084L)\n+#define MAC_TFG_CTRL_TG_ACT (3085L)\n+#define MAC_TFG_CTRL_TG_ENA (3086L)\n+#define MAC_TFG_CTRL_TIME_MODE (3087L)\n+#define MAC_TFG_CTRL_WRAP (3088L)\n+#define MAC_TFG_DATA (3089L)\n+#define MAC_TFG_DATA_GAP (3090L)\n+#define MAC_TFG_DATA_ID (3091L)\n+#define MAC_TFG_DATA_LENGTH (3092L)\n+#define MAC_TFG_FRAME_HDR (3093L)\n+#define MAC_TFG_FRAME_HDR_HDR (3094L)\n+#define MAC_TFG_REPETITION (3095L)\n+#define MAC_TFG_REPETITION_CNT (3096L)\n+#define MAC_TX_CONFIG (3097L)\n+#define MAC_TX_CONFIG_CLR_STICKY (3098L)\n+#define MAC_TX_CONFIG_CRC_ERR_INS (3099L)\n+#define MAC_TX_CONFIG_HOST_TX_ENA (3100L)\n+#define MAC_TX_CONFIG_MAC_LOOP (3101L)\n+#define MAC_TX_CONFIG_PCS_BIP_ERR (3102L)\n+#define MAC_TX_CONFIG_PCS_DIS_BIP_INS (3103L)\n+#define MAC_TX_CONFIG_PCS_IDLE (3104L)\n+#define MAC_TX_CONFIG_PCS_IDLE_DIS (3105L)\n+#define MAC_TX_CONFIG_PCS_LOCAL_FAULT (3106L)\n+#define MAC_TX_CONFIG_PCS_LOCAL_FAULT_DIS (3107L)\n+#define MAC_TX_CONFIG_PCS_REMOTE_FAULT (3108L)\n+#define MAC_TX_CONFIG_PCS_REMOTE_FAULT_DIS (3109L)\n+#define MAC_TX_CONFIG_PCS_SCRAMB_ENA (3110L)\n+#define MAC_TX_CONFIG_PCS_SCRAMB_ERR (3111L)\n+#define MAC_TX_CONFIG_TIME_OFFSET_TX (3112L)\n+#define MAC_TX_CONFIG_TS_EOP (3113L)\n+#define MAC_TX_STATUS (3114L)\n+#define MAC_TX_STATUS_PCS_ERR (3115L)\n+#define MAC_TX_STATUS_TX_MAC_ST (3116L)\n+#define MAC_TX_STATUS_UNDER_FLOW (3117L)\n+#define MAC_UPD_RX_COUNTERS (3118L)\n+#define MAC_UPD_RX_COUNTERS_TRIGGER (3119L)\n+/* MAC10 */\n+#define MAC10_CFG_0 (3135L)\n+#define MAC10_CFG_0_PAD_ENA (3136L)\n+#define MAC10_CFG_0_RX_ENA (3137L)\n+#define MAC10_CFG_0_RX_PAUSE_ENA (3138L)\n+#define MAC10_CFG_0_STR_ENA (3139L)\n+#define MAC10_CFG_0_TX_ENA (3140L)\n+#define MAC10_CFG_0_TX_PAUSE_ENA (3141L)\n+#define MAC10_MA (3142L)\n+#define MAC10_MA_MAC10_ADR_0 (3143L)\n+#define MAC10_MA_MAC_ADR_0 (3144L)\n+#define MAC10_MA_LO (3145L)\n+#define MAC10_MA_LO_MA_LO (3146L)\n+#define MAC10_MA_MAX_SIZE (3147L)\n+#define MAC10_MA_MAX_SIZE_MAC10_ADR_1 (3148L)\n+#define MAC10_MA_MAX_SIZE_MAC_ADR_1 (3149L)\n+#define MAC10_MA_MAX_SIZE_MTU (3150L)\n+#define MAC10_MA_UP (3151L)\n+#define MAC10_MA_UP_MA_UP (3152L)\n+#define MAC10_STICKY_XAUI (3153L)\n+#define MAC10_STICKY_XAUI_STICKY_XAUI (3154L)\n+/* MAC100 */\n+#define MAC100_CONF_SERDES_BITFRAG (3155L)\n+#define MAC100_CONF_SERDES_BITFRAG_BITFRAG (3156L)\n+#define MAC100_CONF_SERDES_DELAY (3157L)\n+#define MAC100_CONF_SERDES_DELAY_DELAY (3158L)\n+#define MAC100_CONF_SERDES_REORDER (3159L)\n+#define MAC100_CONF_SERDES_REORDER_REORDER (3160L)\n+#define MAC100_FAULTY_BLK (3161L)\n+#define MAC100_FAULTY_BLK_DATA (3162L)\n+#define MAC100_HOST_STAT_BYTE (3163L)\n+#define MAC100_HOST_STAT_BYTE_CNT (3164L)\n+#define MAC100_HOST_STAT_BYTE_FILL (3165L)\n+#define MAC100_HOST_STAT_BYTE_FILL_CNT (3166L)\n+#define MAC100_HOST_STAT_CRC (3167L)\n+#define MAC100_HOST_STAT_CRC_CNT (3168L)\n+#define MAC100_HOST_STAT_CV (3169L)\n+#define MAC100_HOST_STAT_CV_CNT (3170L)\n+#define MAC100_HOST_STAT_DROP (3171L)\n+#define MAC100_HOST_STAT_DROP_CNT (3172L)\n+#define MAC100_HOST_STAT_DROP_BYTE (3173L)\n+#define MAC100_HOST_STAT_DROP_BYTE_CNT (3174L)\n+#define MAC100_HOST_STAT_FRAME (3175L)\n+#define MAC100_HOST_STAT_FRAME_CNT (3176L)\n+#define MAC100_HOST_STAT_FRAME_FILL (3177L)\n+#define MAC100_HOST_STAT_FRAME_FILL_CNT (3178L)\n+#define MAC100_INT (3179L)\n+#define MAC100_INT_EN (3180L)\n+#define MAC100_INT_MAX_PACE (3181L)\n+#define MAC100_LINK_SUMMARY (3182L)\n+#define MAC100_LINK_SUMMARY_ABS (3183L)\n+#define MAC100_LINK_SUMMARY_GBOX_INTERR (3184L)\n+#define MAC100_LINK_SUMMARY_GLB_ALARMN (3185L)\n+#define MAC100_LINK_SUMMARY_LH_ABS (3186L)\n+#define MAC100_LINK_SUMMARY_LH_GLB_ALARMN (3187L)\n+#define MAC100_LINK_SUMMARY_LH_LOCAL_FAULT (3188L)\n+#define MAC100_LINK_SUMMARY_LH_REMOTE_FAULT (3189L)\n+#define MAC100_LINK_SUMMARY_LH_RX_LOS (3190L)\n+#define MAC100_LINK_SUMMARY_LINK_DOWN_CNT (3191L)\n+#define MAC100_LINK_SUMMARY_LL_PHY_LINK_STATE (3192L)\n+#define MAC100_LINK_SUMMARY_LOCAL_FAULT (3193L)\n+#define MAC100_LINK_SUMMARY_NT_PHY_LINK_STATE (3194L)\n+#define MAC100_LINK_SUMMARY_REMOTE_FAULT (3195L)\n+#define MAC100_LINK_SUMMARY_RX_LOS (3196L)\n+#define MAC100_MAC_STAT_BYTE (3197L)\n+#define MAC100_MAC_STAT_BYTE_CNT (3198L)\n+#define MAC100_MAC_STAT_CRC (3199L)\n+#define MAC100_MAC_STAT_CRC_CNT (3200L)\n+#define MAC100_MAC_STAT_CV (3201L)\n+#define MAC100_MAC_STAT_CV_CNT (3202L)\n+#define MAC100_MAC_STAT_FC (3203L)\n+#define MAC100_MAC_STAT_FC_CNT (3204L)\n+#define MAC100_MAC_STAT_FRAME (3205L)\n+#define MAC100_MAC_STAT_FRAME_CNT (3206L)\n+#define MAC100_MAC_STAT_MICRO_DROP (3207L)\n+#define MAC100_MAC_STAT_MICRO_DROP_CNT (3208L)\n+#define MAC100_MAC_STAT_PAUSE (3209L)\n+#define MAC100_MAC_STAT_PAUSE_CNT (3210L)\n+#define MAC100_MAC_STAT_RATE_DROP (3211L)\n+#define MAC100_MAC_STAT_RATE_DROP_CNT (3212L)\n+#define MAC100_MAC_STAT_TRUNC (3213L)\n+#define MAC100_MAC_STAT_TRUNC_CNT (3214L)\n+#define MAC100_MDS_CEN_VAL (3215L)\n+#define MAC100_MDS_CEN_VAL_VAL (3216L)\n+#define MAC100_MDS_CONF (3217L)\n+#define MAC100_MDS_CONF_CENTER_REC_ENA (3218L)\n+#define MAC100_MDS_CONF_CLR_STAT (3219L)\n+#define MAC100_MDS_CONF_ENA_TS_MOD (3220L)\n+#define MAC100_MDS_CONF_REC_ENA (3221L)\n+#define MAC100_MDS_CONF_TIME_MODE (3222L)\n+#define MAC100_MDS_DATA (3223L)\n+#define MAC100_MDS_DATA_DATA (3224L)\n+#define MAC100_MDS_FRAMES (3225L)\n+#define MAC100_MDS_FRAMES_CNT (3226L)\n+#define MAC100_MDS_MAX (3227L)\n+#define MAC100_MDS_MAX_MAX (3228L)\n+#define MAC100_MDS_MIN (3229L)\n+#define MAC100_MDS_MIN_MIN (3230L)\n+#define MAC100_MDS_STAT (3231L)\n+#define MAC100_MDS_STAT_CLR_BUSY (3232L)\n+#define MAC100_MDS_STAT_HIT_MAX (3233L)\n+#define MAC100_MDS_STAT_HIT_MIN (3234L)\n+#define MAC100_MDS_VAL_REC (3235L)\n+#define MAC100_MDS_VAL_REC_VALUE (3236L)\n+#define MAC100_MDS_VAL_REC_FRAME (3237L)\n+#define MAC100_MDS_VAL_REC_FRAME_VALUE (3238L)\n+#define MAC100_NT_PORT_CTRL (3239L)\n+#define MAC100_NT_PORT_CTRL_LED_MODE (3240L)\n+#define MAC100_RAM_MDS_ADDR (3241L)\n+#define MAC100_RAM_MDS_ADDR_ADR (3242L)\n+#define MAC100_RAM_MDS_ADDR_CLR_RAM (3243L)\n+#define MAC100_RAM_MDS_ADDR_RD_DONE (3244L)\n+#define MAC100_RAM_MDS_ADDR_RD_ENA (3245L)\n+#define MAC100_RAW_ADDR (3246L)\n+#define MAC100_RAW_ADDR_ADR (3247L)\n+#define MAC100_RAW_ADDR_RDENA (3248L)\n+#define MAC100_RAW_ADDR_RD_DONE (3249L)\n+#define MAC100_RAW_CTRL (3250L)\n+#define MAC100_RAW_CTRL_OVERWR_LM (3251L)\n+#define MAC100_RAW_CTRL_RESTART (3252L)\n+#define MAC100_RAW_CTRL_TG_ACT (3253L)\n+#define MAC100_RAW_CTRL_TG_ENA (3254L)\n+#define MAC100_RAW_CTRL_WRAP (3255L)\n+#define MAC100_RAW_DATA (3256L)\n+#define MAC100_RAW_DATA_RAW_DATA (3257L)\n+#define MAC100_RAW_REPETITION (3258L)\n+#define MAC100_RAW_REPETITION_CNT (3259L)\n+#define MAC100_RX_CONFIG (3260L)\n+#define MAC100_RX_CONFIG_DESCRAMB (3261L)\n+#define MAC100_RX_CONFIG_HADP_RUN_MODE (3262L)\n+#define MAC100_RX_CONFIG_HOST_CLR_CNT (3263L)\n+#define MAC100_RX_CONFIG_MAC_CLR_CNT (3264L)\n+#define MAC100_RX_CONFIG_MIN_RX_FRAME (3265L)\n+#define MAC100_RX_CONFIG_NT_DEBOUNCE_LATENCY (3266L)\n+#define MAC100_RX_CONFIG_NT_FORCE_LINK_DOWN (3267L)\n+#define MAC100_RX_CONFIG_NT_LINKUP_LATENCY (3268L)\n+#define MAC100_RX_CONFIG_RST_BLK_ERR (3269L)\n+#define MAC100_RX_CONFIG_RX_MAC_EN (3270L)\n+#define MAC100_RX_CONFIG_TS_EOP (3271L)\n+#define MAC100_RX_CONFIG_TXRX_LOOP (3272L)\n+#define MAC100_RX_CONFIG2 (3273L)\n+#define MAC100_RX_CONFIG2_NT_MOD_ABS_MASK_INT (3274L)\n+#define MAC100_RX_CONFIG2_NT_MOD_ABS_MASK_LINK (3275L)\n+#define MAC100_RX_CONFIG2_NT_MOD_ABS_MASK_RST (3276L)\n+#define MAC100_RX_CONFIG2_NT_RXLOS_MASK_INT (3277L)\n+#define MAC100_RX_CONFIG2_NT_RXLOS_MASK_LINK (3278L)\n+#define MAC100_RX_CONFIG2_NT_RXLOS_MASK_RST (3279L)\n+#define MAC100_RX_STATUS (3280L)\n+#define MAC100_RX_STATUS_CORE_MODE (3281L)\n+#define MAC100_RX_STATUS_LOCAL_FAULT (3282L)\n+#define MAC100_RX_STATUS_REMOTE_FAULT (3283L)\n+#define MAC100_RX_STATUS_RXTX_OVERFLOW (3284L)\n+#define MAC100_RX_STATUS_VERSION (3285L)\n+#define MAC100_TFG_ADDR (3286L)\n+#define MAC100_TFG_ADDR_ADR (3287L)\n+#define MAC100_TFG_ADDR_RDENA (3288L)\n+#define MAC100_TFG_ADDR_RD_DONE (3289L)\n+#define MAC100_TFG_CTRL (3290L)\n+#define MAC100_TFG_CTRL_ID_ENA (3291L)\n+#define MAC100_TFG_CTRL_ID_POS (3292L)\n+#define MAC100_TFG_CTRL_RESTART (3293L)\n+#define MAC100_TFG_CTRL_TG_ACT (3294L)\n+#define MAC100_TFG_CTRL_TG_ENA (3295L)\n+#define MAC100_TFG_CTRL_TIME_MODE (3296L)\n+#define MAC100_TFG_CTRL_WRAP (3297L)\n+#define MAC100_TFG_DATA (3298L)\n+#define MAC100_TFG_DATA_GAP (3299L)\n+#define MAC100_TFG_DATA_ID (3300L)\n+#define MAC100_TFG_DATA_LENGTH (3301L)\n+#define MAC100_TFG_FRAME_HDR (3302L)\n+#define MAC100_TFG_FRAME_HDR_HDR (3303L)\n+#define MAC100_TFG_REPETITION (3304L)\n+#define MAC100_TFG_REPETITION_CNT (3305L)\n+#define MAC100_TX_CONFIG (3306L)\n+#define MAC100_TX_CONFIG_CLR_STICKY (3307L)\n+#define MAC100_TX_CONFIG_CRC_ERR_INS (3308L)\n+#define MAC100_TX_CONFIG_HADP_LOOP (3309L)\n+#define MAC100_TX_CONFIG_HOST_TX_ENA (3310L)\n+#define MAC100_TX_CONFIG_MAC_LOOP (3311L)\n+#define MAC100_TX_CONFIG_PCS_BIP_ERR (3312L)\n+#define MAC100_TX_CONFIG_PCS_DIS_BIP_INS (3313L)\n+#define MAC100_TX_CONFIG_PCS_IDLE (3314L)\n+#define MAC100_TX_CONFIG_PCS_IDLE_DIS (3315L)\n+#define MAC100_TX_CONFIG_PCS_LOCAL_FAULT (3316L)\n+#define MAC100_TX_CONFIG_PCS_LOCAL_FAULT_DIS (3317L)\n+#define MAC100_TX_CONFIG_PCS_REMOTE_FAULT (3318L)\n+#define MAC100_TX_CONFIG_PCS_REMOTE_FAULT_DIS (3319L)\n+#define MAC100_TX_CONFIG_PCS_SCRAMB_ENA (3320L)\n+#define MAC100_TX_CONFIG_PCS_SCRAMB_ERR (3321L)\n+#define MAC100_TX_CONFIG_TIME_OFFSET_TX (3322L)\n+#define MAC100_TX_CONFIG_TS_EOP (3323L)\n+#define MAC100_TX_STATUS (3324L)\n+#define MAC100_TX_STATUS_PCS_ERR (3325L)\n+#define MAC100_TX_STATUS_TX_HADP_ST (3326L)\n+#define MAC100_TX_STATUS_TX_MAC_ST (3327L)\n+#define MAC100_TX_STATUS_UNDER_FLOW (3328L)\n+#define MAC100_UPD_RX_COUNTERS (3329L)\n+#define MAC100_UPD_RX_COUNTERS_TRIGGER (3330L)\n+/* MAC10G */\n+#define MAC10G_CFG (3331L)\n+#define MAC10G_CFG_MIN_RX_FRAME (3332L)\n+#define MAC10G_CFG_RX_ENA (3333L)\n+#define MAC10G_CFG_RX_EOP_TS (3334L)\n+#define MAC10G_CFG_RX_PAUSE_ENA (3335L)\n+#define MAC10G_CFG_STR_ENA (3336L)\n+#define MAC10G_CFG_TX_ENA (3337L)\n+#define MAC10G_CFG_TX_PAUSE_ENA (3338L)\n+#define MAC10G_MA_LO (3339L)\n+#define MAC10G_MA_LO_MA_LO (3340L)\n+#define MAC10G_MA_UP (3341L)\n+#define MAC10G_MA_UP_MA_UP (3342L)\n+/* MAC1G */\n+#define MAC1G_CFG (3343L)\n+#define MAC1G_CFG_MIN_RX_FRAME (3344L)\n+#define MAC1G_CFG_RX_ENA (3345L)\n+#define MAC1G_CFG_RX_EOP_TS (3346L)\n+#define MAC1G_CFG_RX_PAUSE_ENA (3347L)\n+#define MAC1G_CFG_SPEED (3348L)\n+#define MAC1G_CFG_STR_ENA (3349L)\n+#define MAC1G_CFG_TX_ENA (3350L)\n+#define MAC1G_CFG_TX_PAUSE_ENA (3351L)\n+#define MAC1G_MA_LO (3352L)\n+#define MAC1G_MA_LO_MA_LO (3353L)\n+#define MAC1G_MA_UP (3354L)\n+#define MAC1G_MA_UP_MA_UP (3355L)\n+/* MAC_PCS */\n+#define MAC_PCS_BAD_CODE (3366L)\n+#define MAC_PCS_BAD_CODE_CODE_ERR (3367L)\n+#define MAC_PCS_BIP_ERR (3368L)\n+#define MAC_PCS_BIP_ERR_BIP_ERR (3369L)\n+#define MAC_PCS_BLOCK_LOCK (3370L)\n+#define MAC_PCS_BLOCK_LOCK_LOCK (3371L)\n+#define MAC_PCS_BLOCK_LOCK_CHG (3372L)\n+#define MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG (3373L)\n+#define MAC_PCS_CLKRX_FRQ (3374L)\n+#define MAC_PCS_CLKRX_FRQ_RX_FREQ (3375L)\n+#define MAC_PCS_CLKTX_FRQ (3376L)\n+#define MAC_PCS_CLKTX_FRQ_TX_FREQ (3377L)\n+#define MAC_PCS_DEBOUNCE_CTRL (3378L)\n+#define MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY (3379L)\n+#define MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN (3380L)\n+#define MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY (3381L)\n+#define MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL (3382L)\n+#define MAC_PCS_DRP_CONFIG (3383L)\n+#define MAC_PCS_DRP_CONFIG_DRP_ADR (3384L)\n+#define MAC_PCS_DRP_CONFIG_DRP_DI (3385L)\n+#define MAC_PCS_DRP_CONFIG_DRP_EN (3386L)\n+#define MAC_PCS_DRP_CONFIG_DRP_MOD_ADR (3387L)\n+#define MAC_PCS_DRP_CONFIG_DRP_WREN (3388L)\n+#define MAC_PCS_DRP_CTRL (3389L)\n+#define MAC_PCS_DRP_CTRL_ADR (3390L)\n+#define MAC_PCS_DRP_CTRL_DATA (3391L)\n+#define MAC_PCS_DRP_CTRL_DBG_BUSY (3392L)\n+#define MAC_PCS_DRP_CTRL_DONE (3393L)\n+#define MAC_PCS_DRP_CTRL_MOD_ADR (3394L)\n+#define MAC_PCS_DRP_CTRL_WREN (3395L)\n+#define MAC_PCS_DRP_DATA (3396L)\n+#define MAC_PCS_DRP_DATA_DRP_DO (3397L)\n+#define MAC_PCS_DRP_DATA_DRP_RDY (3398L)\n+#define MAC_PCS_FEC_CTRL (3399L)\n+#define MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN (3400L)\n+#define MAC_PCS_FEC_CW_CNT (3401L)\n+#define MAC_PCS_FEC_CW_CNT_CW_CNT (3402L)\n+#define MAC_PCS_FEC_ERR_CNT_0 (3403L)\n+#define MAC_PCS_FEC_ERR_CNT_0_ERR_CNT (3404L)\n+#define MAC_PCS_FEC_ERR_CNT_1 (3405L)\n+#define MAC_PCS_FEC_ERR_CNT_1_ERR_CNT (3406L)\n+#define MAC_PCS_FEC_ERR_CNT_2 (3407L)\n+#define MAC_PCS_FEC_ERR_CNT_2_ERR_CNT (3408L)\n+#define MAC_PCS_FEC_ERR_CNT_3 (3409L)\n+#define MAC_PCS_FEC_ERR_CNT_3_ERR_CNT (3410L)\n+#define MAC_PCS_FEC_LANE_DLY_0 (3411L)\n+#define MAC_PCS_FEC_LANE_DLY_0_DLY (3412L)\n+#define MAC_PCS_FEC_LANE_DLY_1 (3413L)\n+#define MAC_PCS_FEC_LANE_DLY_1_DLY (3414L)\n+#define MAC_PCS_FEC_LANE_DLY_2 (3415L)\n+#define MAC_PCS_FEC_LANE_DLY_2_DLY (3416L)\n+#define MAC_PCS_FEC_LANE_DLY_3 (3417L)\n+#define MAC_PCS_FEC_LANE_DLY_3_DLY (3418L)\n+#define MAC_PCS_FEC_LANE_MAP (3419L)\n+#define MAC_PCS_FEC_LANE_MAP_MAPPING (3420L)\n+#define MAC_PCS_FEC_STAT (3421L)\n+#define MAC_PCS_FEC_STAT_AM_LOCK (3422L)\n+#define MAC_PCS_FEC_STAT_AM_LOCK_0 (3423L)\n+#define MAC_PCS_FEC_STAT_AM_LOCK_1 (3424L)\n+#define MAC_PCS_FEC_STAT_AM_LOCK_2 (3425L)\n+#define MAC_PCS_FEC_STAT_AM_LOCK_3 (3426L)\n+#define MAC_PCS_FEC_STAT_BLOCK_LOCK (3427L)\n+#define MAC_PCS_FEC_STAT_BYPASS (3428L)\n+#define MAC_PCS_FEC_STAT_FEC_LANE_ALGN (3429L)\n+#define MAC_PCS_FEC_STAT_HI_SER (3430L)\n+#define MAC_PCS_FEC_STAT_PCS_LANE_ALGN (3431L)\n+#define MAC_PCS_FEC_STAT_VALID (3432L)\n+#define MAC_PCS_FEC_UCW_CNT (3433L)\n+#define MAC_PCS_FEC_UCW_CNT_UCW_CNT (3434L)\n+#define MAC_PCS_FRAMING_ERR (3435L)\n+#define MAC_PCS_FRAMING_ERR_FRAMING_ERR (3436L)\n+#define MAC_PCS_GTY_CTL (3437L)\n+#define MAC_PCS_GTY_CTL_CDR_HOLD_0 (3438L)\n+#define MAC_PCS_GTY_CTL_CDR_HOLD_1 (3439L)\n+#define MAC_PCS_GTY_CTL_CDR_HOLD_2 (3440L)\n+#define MAC_PCS_GTY_CTL_CDR_HOLD_3 (3441L)\n+#define MAC_PCS_GTY_CTL_RX (3442L)\n+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_0 (3443L)\n+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_1 (3444L)\n+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_2 (3445L)\n+#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_3 (3446L)\n+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_0 (3447L)\n+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_1 (3448L)\n+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_2 (3449L)\n+#define MAC_PCS_GTY_CTL_RX_EQUA_RST_3 (3450L)\n+#define MAC_PCS_GTY_CTL_RX_LPM_EN_0 (3451L)\n+#define MAC_PCS_GTY_CTL_RX_LPM_EN_1 (3452L)\n+#define MAC_PCS_GTY_CTL_RX_LPM_EN_2 (3453L)\n+#define MAC_PCS_GTY_CTL_RX_LPM_EN_3 (3454L)\n+#define MAC_PCS_GTY_CTL_RX_POLARITY_0 (3455L)\n+#define MAC_PCS_GTY_CTL_RX_POLARITY_1 (3456L)\n+#define MAC_PCS_GTY_CTL_RX_POLARITY_2 (3457L)\n+#define MAC_PCS_GTY_CTL_RX_POLARITY_3 (3458L)\n+#define MAC_PCS_GTY_CTL_RX_RATE_0 (3459L)\n+#define MAC_PCS_GTY_CTL_RX_RATE_1 (3460L)\n+#define MAC_PCS_GTY_CTL_RX_RATE_2 (3461L)\n+#define MAC_PCS_GTY_CTL_RX_RATE_3 (3462L)\n+#define MAC_PCS_GTY_CTL_TX (3463L)\n+#define MAC_PCS_GTY_CTL_TX_INHIBIT_0 (3464L)\n+#define MAC_PCS_GTY_CTL_TX_INHIBIT_1 (3465L)\n+#define MAC_PCS_GTY_CTL_TX_INHIBIT_2 (3466L)\n+#define MAC_PCS_GTY_CTL_TX_INHIBIT_3 (3467L)\n+#define MAC_PCS_GTY_CTL_TX_POLARITY_0 (3468L)\n+#define MAC_PCS_GTY_CTL_TX_POLARITY_1 (3469L)\n+#define MAC_PCS_GTY_CTL_TX_POLARITY_2 (3470L)\n+#define MAC_PCS_GTY_CTL_TX_POLARITY_3 (3471L)\n+#define MAC_PCS_GTY_DIFF_CTL (3472L)\n+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0 (3473L)\n+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1 (3474L)\n+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2 (3475L)\n+#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3 (3476L)\n+#define MAC_PCS_GTY_LOOP (3477L)\n+#define MAC_PCS_GTY_LOOP_GT_LOOP_0 (3478L)\n+#define MAC_PCS_GTY_LOOP_GT_LOOP_1 (3479L)\n+#define MAC_PCS_GTY_LOOP_GT_LOOP_2 (3480L)\n+#define MAC_PCS_GTY_LOOP_GT_LOOP_3 (3481L)\n+#define MAC_PCS_GTY_POST_CURSOR (3482L)\n+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0 (3483L)\n+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1 (3484L)\n+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2 (3485L)\n+#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3 (3486L)\n+#define MAC_PCS_GTY_PRBS_SEL (3487L)\n+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0 (3488L)\n+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1 (3489L)\n+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2 (3490L)\n+#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3 (3491L)\n+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0 (3492L)\n+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1 (3493L)\n+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2 (3494L)\n+#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3 (3495L)\n+#define MAC_PCS_GTY_PRE_CURSOR (3496L)\n+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0 (3497L)\n+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1 (3498L)\n+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2 (3499L)\n+#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3 (3500L)\n+#define MAC_PCS_GTY_RX_BUF_STAT (3501L)\n+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0 (3502L)\n+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1 (3503L)\n+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2 (3504L)\n+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3 (3505L)\n+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0 (3506L)\n+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1 (3507L)\n+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2 (3508L)\n+#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3 (3509L)\n+#define MAC_PCS_GTY_SCAN_CTL (3510L)\n+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0 (3511L)\n+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1 (3512L)\n+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2 (3513L)\n+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3 (3514L)\n+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0 (3515L)\n+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1 (3516L)\n+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2 (3517L)\n+#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3 (3518L)\n+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0 (3519L)\n+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1 (3520L)\n+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2 (3521L)\n+#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3 (3522L)\n+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0 (3523L)\n+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1 (3524L)\n+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2 (3525L)\n+#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3 (3526L)\n+#define MAC_PCS_GTY_SCAN_STAT (3527L)\n+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0 (3528L)\n+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1 (3529L)\n+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2 (3530L)\n+#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3 (3531L)\n+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0 (3532L)\n+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1 (3533L)\n+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2 (3534L)\n+#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3 (3535L)\n+#define MAC_PCS_GTY_STAT (3536L)\n+#define MAC_PCS_GTY_STAT_RX_RST_DONE_0 (3537L)\n+#define MAC_PCS_GTY_STAT_RX_RST_DONE_1 (3538L)\n+#define MAC_PCS_GTY_STAT_RX_RST_DONE_2 (3539L)\n+#define MAC_PCS_GTY_STAT_RX_RST_DONE_3 (3540L)\n+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_0 (3541L)\n+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_1 (3542L)\n+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_2 (3543L)\n+#define MAC_PCS_GTY_STAT_TX_BUF_STAT_3 (3544L)\n+#define MAC_PCS_GTY_STAT_TX_RST_DONE_0 (3545L)\n+#define MAC_PCS_GTY_STAT_TX_RST_DONE_1 (3546L)\n+#define MAC_PCS_GTY_STAT_TX_RST_DONE_2 (3547L)\n+#define MAC_PCS_GTY_STAT_TX_RST_DONE_3 (3548L)\n+#define MAC_PCS_LANE_ALIGNER_FILL (3549L)\n+#define MAC_PCS_LANE_ALIGNER_FILL_FILL (3550L)\n+#define MAC_PCS_LINK_SUMMARY (3551L)\n+#define MAC_PCS_LINK_SUMMARY_ABS (3552L)\n+#define MAC_PCS_LINK_SUMMARY_LH_ABS (3553L)\n+#define MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT (3554L)\n+#define MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT (3555L)\n+#define MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT (3556L)\n+#define MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE (3557L)\n+#define MAC_PCS_LINK_SUMMARY_LOCAL_FAULT (3558L)\n+#define MAC_PCS_LINK_SUMMARY_NIM_INTERR (3559L)\n+#define MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE (3560L)\n+#define MAC_PCS_LINK_SUMMARY_REMOTE_FAULT (3561L)\n+#define MAC_PCS_LINK_SUMMARY_RESERVED (3562L)\n+#define MAC_PCS_MAC_PCS_CONFIG (3563L)\n+#define MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST (3564L)\n+#define MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE (3565L)\n+#define MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC (3566L)\n+#define MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST (3567L)\n+#define MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN (3568L)\n+#define MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST (3569L)\n+#define MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE (3570L)\n+#define MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE (3571L)\n+#define MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST (3572L)\n+#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE (3573L)\n+#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI (3574L)\n+#define MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN (3575L)\n+#define MAC_PCS_MAX_PKT_LEN (3576L)\n+#define MAC_PCS_MAX_PKT_LEN_MAX_LEN (3577L)\n+#define MAC_PCS_MF_ERR (3578L)\n+#define MAC_PCS_MF_ERR_MF_ERR (3579L)\n+#define MAC_PCS_MF_LEN_ERR (3580L)\n+#define MAC_PCS_MF_LEN_ERR_MF_LEN_ERR (3581L)\n+#define MAC_PCS_MF_REPEAT_ERR (3582L)\n+#define MAC_PCS_MF_REPEAT_ERR_MF_REPEAT_ERR (3583L)\n+#define MAC_PCS_PHYMAC_MISC (3584L)\n+#define MAC_PCS_PHYMAC_MISC_TS_EOP (3585L)\n+#define MAC_PCS_PHYMAC_MISC_TX_MUX_STATE (3586L)\n+#define MAC_PCS_PHYMAC_MISC_TX_SEL_HOST (3587L)\n+#define MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP (3588L)\n+#define MAC_PCS_PHYMAC_MISC_TX_SEL_TFG (3589L)\n+#define MAC_PCS_PHY_STAT (3590L)\n+#define MAC_PCS_PHY_STAT_ALARM (3591L)\n+#define MAC_PCS_PHY_STAT_MOD_PRS (3592L)\n+#define MAC_PCS_PHY_STAT_RX_LOS (3593L)\n+#define MAC_PCS_STAT_PCS_RX (3594L)\n+#define MAC_PCS_STAT_PCS_RX_ALIGNED (3595L)\n+#define MAC_PCS_STAT_PCS_RX_ALIGNED_ERR (3596L)\n+#define MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS (3597L)\n+#define MAC_PCS_STAT_PCS_RX_HI_BER (3598L)\n+#define MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT (3599L)\n+#define MAC_PCS_STAT_PCS_RX_LOCAL_FAULT (3600L)\n+#define MAC_PCS_STAT_PCS_RX_MISALIGNED (3601L)\n+#define MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT (3602L)\n+#define MAC_PCS_STAT_PCS_RX_REMOTE_FAULT (3603L)\n+#define MAC_PCS_STAT_PCS_RX_STATUS (3604L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH (3605L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED (3606L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR (3607L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS (3608L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_HI_BER (3609L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT (3610L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT (3611L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED (3612L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT (3613L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT (3614L)\n+#define MAC_PCS_STAT_PCS_RX_LATCH_STATUS (3615L)\n+#define MAC_PCS_STAT_PCS_TX (3616L)\n+#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT (3617L)\n+#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED (3618L)\n+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR (3619L)\n+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED (3620L)\n+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR (3621L)\n+#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED (3622L)\n+#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT (3623L)\n+#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED (3624L)\n+#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT (3625L)\n+#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED (3626L)\n+#define MAC_PCS_SYNCED (3627L)\n+#define MAC_PCS_SYNCED_SYNC (3628L)\n+#define MAC_PCS_SYNCED_ERR (3629L)\n+#define MAC_PCS_SYNCED_ERR_SYNC_ERROR (3630L)\n+#define MAC_PCS_TEST_ERR (3631L)\n+#define MAC_PCS_TEST_ERR_CODE_ERR (3632L)\n+#define MAC_PCS_TIMESTAMP_COMP (3633L)\n+#define MAC_PCS_TIMESTAMP_COMP_RX_DLY (3634L)\n+#define MAC_PCS_TIMESTAMP_COMP_TX_DLY (3635L)\n+#define MAC_PCS_VL_DEMUXED (3636L)\n+#define MAC_PCS_VL_DEMUXED_LOCK (3637L)\n+#define MAC_PCS_VL_DEMUXED_CHG (3638L)\n+#define MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG (3639L)\n+#define MAC_PCS_VL_NUMBER (3640L)\n+#define MAC_PCS_VL_NUMBER_VL_NUMBER (3641L)\n+/* MAC_PCS_XXV */\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0 (3642L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ASMDIR (3643L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_BYPASS (3644L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_ENABLE (3645L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_PAUSE (3646L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_0_RESTART (3647L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1 (3648L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ASMDIR (3649L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_BYPASS (3650L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_ENABLE (3651L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_PAUSE (3652L)\n+#define MAC_PCS_XXV_ANEG_1G_CONFIG_1_RESTART (3653L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_0 (3654L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_0_COMPLETE (3655L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ANEG_ABLE (3656L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_ASM (3657L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_PAUSE (3658L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_0_LP_RF (3659L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_1 (3660L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_1_COMPLETE (3661L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ANEG_ABLE (3662L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_ASM (3663L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_PAUSE (3664L)\n+#define MAC_PCS_XXV_ANEG_1G_STA_1_LP_RF (3665L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_0 (3666L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR (3667L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR1 (3668L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_0_25GBASE_CR_S (3669L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR (3670L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR1 (3671L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_0_BASE25G_CR_S (3672L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_1 (3673L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR (3674L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR1 (3675L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_1_BASE25G_CR_S (3676L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR (3677L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR1 (3678L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_1_25GBASE_CR_S (3679L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_2 (3680L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR (3681L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR1 (3682L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_2_BASE25G_CR_S (3683L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR (3684L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR1 (3685L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_2_25GBASE_CR_S (3686L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_3 (3687L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR (3688L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR1 (3689L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_3_BASE25G_CR_S (3690L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR (3691L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR1 (3692L)\n+#define MAC_PCS_XXV_ANEG_ABILITY_3_25GBASE_CR_S (3693L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0 (3694L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_ASMDIR (3695L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_BYPASS (3696L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_ENABLE (3697L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST (3698L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC74_REQUEST_10G (3699L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_ABILITY (3700L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_FEC91_REQUEST (3701L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_HIDE_FEC74 (3702L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_NONCE_SEED (3703L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_PAUSE (3704L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_PSEUDO (3705L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_REMOTE_FAULT (3706L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_RESTART (3707L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_RS_FEC_REQUEST (3708L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_FEC_OVERWRITE (3709L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_0_SW_SPEED_OVERWRITE (3710L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1 (3711L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_ASMDIR (3712L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_BYPASS (3713L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_ENABLE (3714L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST (3715L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC74_REQUEST_10G (3716L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_ABILITY (3717L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_FEC91_REQUEST (3718L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_HIDE_FEC74 (3719L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_NONCE_SEED (3720L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_PAUSE (3721L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_PSEUDO (3722L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_REMOTE_FAULT (3723L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_RESTART (3724L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_RS_FEC_REQUEST (3725L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_FEC_OVERWRITE (3726L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_1_SW_SPEED_OVERWRITE (3727L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2 (3728L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_ASMDIR (3729L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_BYPASS (3730L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_ENABLE (3731L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST (3732L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC74_REQUEST_10G (3733L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_ABILITY (3734L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_FEC91_REQUEST (3735L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_HIDE_FEC74 (3736L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_NONCE_SEED (3737L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_PAUSE (3738L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_PSEUDO (3739L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_REMOTE_FAULT (3740L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_RESTART (3741L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_RS_FEC_REQUEST (3742L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_FEC_OVERWRITE (3743L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_2_SW_SPEED_OVERWRITE (3744L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3 (3745L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_ASMDIR (3746L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_BYPASS (3747L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_ENABLE (3748L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST (3749L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC74_REQUEST_10G (3750L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_ABILITY (3751L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_FEC91_REQUEST (3752L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_HIDE_FEC74 (3753L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_NONCE_SEED (3754L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_PAUSE (3755L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_PSEUDO (3756L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_REMOTE_FAULT (3757L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_RESTART (3758L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_RS_FEC_REQUEST (3759L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_FEC_OVERWRITE (3760L)\n+#define MAC_PCS_XXV_ANEG_CONFIG_3_SW_SPEED_OVERWRITE (3761L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_0 (3762L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_END (3763L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_0_ANEG_STARTED (3764L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_0_CDR_HOLD (3765L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_END (3766L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_0_LT_STARTED (3767L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_1 (3768L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_END (3769L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_1_ANEG_STARTED (3770L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_1_CDR_HOLD (3771L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_END (3772L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_1_LT_STARTED (3773L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_2 (3774L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_END (3775L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_2_ANEG_STARTED (3776L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_2_CDR_HOLD (3777L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_END (3778L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_2_LT_STARTED (3779L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_3 (3780L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_END (3781L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_3_ANEG_STARTED (3782L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_3_CDR_HOLD (3783L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_END (3784L)\n+#define MAC_PCS_XXV_ANEG_DEBUG_3_LT_STARTED (3785L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_0 (3786L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR (3787L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR1 (3788L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_0_LINK_CR_S (3789L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_1 (3790L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR (3791L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR1 (3792L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_1_LINK_CR_S (3793L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_2 (3794L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR (3795L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR1 (3796L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_2_LINK_CR_S (3797L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_3 (3798L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR (3799L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR1 (3800L)\n+#define MAC_PCS_XXV_ANEG_LINK_STA_3_LINK_CR_S (3801L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0 (3802L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR (3803L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_0_LP_25GBASE_CR_S (3804L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1 (3805L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR (3806L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_1_LP_25GBASE_CR_S (3807L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2 (3808L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR (3809L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_2_LP_25GBASE_CR_S (3810L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3 (3811L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR (3812L)\n+#define MAC_PCS_XXV_ANEG_LP_ABILITIES_3_LP_25GBASE_CR_S (3813L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0 (3814L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_ABILITY (3815L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC74_REQUEST (3816L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_ABILITY (3817L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_C_FEC91_REQUEST (3818L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_25GBASE_CR1 (3819L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_0_LP_EX_ABILITY_VALID (3820L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1 (3821L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_ABILITY (3822L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC74_REQUEST (3823L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_ABILITY (3824L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_C_FEC91_REQUEST (3825L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_25GBASE_CR1 (3826L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_1_LP_EX_ABILITY_VALID (3827L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2 (3828L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_ABILITY (3829L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC74_REQUEST (3830L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_ABILITY (3831L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_C_FEC91_REQUEST (3832L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_25GBASE_CR1 (3833L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_2_LP_EX_ABILITY_VALID (3834L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3 (3835L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_ABILITY (3836L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC74_REQUEST (3837L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_ABILITY (3838L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_C_FEC91_REQUEST (3839L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_25GBASE_CR1 (3840L)\n+#define MAC_PCS_XXV_ANEG_LP_EX_ABILITIES_3_LP_EX_ABILITY_VALID (3841L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_0 (3842L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ABILITY_VALID (3843L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ANEG_ABLE (3844L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_ASM (3845L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_FEC74_REQ (3846L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_PAUSE (3847L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RF (3848L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_0_LP_RS_FEC_REQ (3849L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_1 (3850L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ABILITY_VALID (3851L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ANEG_ABLE (3852L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_ASM (3853L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_FEC74_REQ (3854L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_PAUSE (3855L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RF (3856L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_1_LP_RS_FEC_REQ (3857L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_2 (3858L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ABILITY_VALID (3859L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ANEG_ABLE (3860L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_ASM (3861L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_FEC74_REQ (3862L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_PAUSE (3863L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RF (3864L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_2_LP_RS_FEC_REQ (3865L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_3 (3866L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ABILITY_VALID (3867L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ANEG_ABLE (3868L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_ASM (3869L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_FEC74_REQ (3870L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_PAUSE (3871L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RF (3872L)\n+#define MAC_PCS_XXV_ANEG_LP_STA_3_LP_RS_FEC_REQ (3873L)\n+#define MAC_PCS_XXV_ANEG_STA_0 (3874L)\n+#define MAC_PCS_XXV_ANEG_STA_0_COMPLETE (3875L)\n+#define MAC_PCS_XXV_ANEG_STA_0_FEC74_EN (3876L)\n+#define MAC_PCS_XXV_ANEG_STA_0_PAR_D_FAULT (3877L)\n+#define MAC_PCS_XXV_ANEG_STA_0_RS_FEC_EN (3878L)\n+#define MAC_PCS_XXV_ANEG_STA_0_RX_PAUSE_EN (3879L)\n+#define MAC_PCS_XXV_ANEG_STA_0_TX_PAUSE_EN (3880L)\n+#define MAC_PCS_XXV_ANEG_STA_1 (3881L)\n+#define MAC_PCS_XXV_ANEG_STA_1_COMPLETE (3882L)\n+#define MAC_PCS_XXV_ANEG_STA_1_FEC74_EN (3883L)\n+#define MAC_PCS_XXV_ANEG_STA_1_PAR_D_FAULT (3884L)\n+#define MAC_PCS_XXV_ANEG_STA_1_RS_FEC_EN (3885L)\n+#define MAC_PCS_XXV_ANEG_STA_1_RX_PAUSE_EN (3886L)\n+#define MAC_PCS_XXV_ANEG_STA_1_TX_PAUSE_EN (3887L)\n+#define MAC_PCS_XXV_ANEG_STA_2 (3888L)\n+#define MAC_PCS_XXV_ANEG_STA_2_COMPLETE (3889L)\n+#define MAC_PCS_XXV_ANEG_STA_2_FEC74_EN (3890L)\n+#define MAC_PCS_XXV_ANEG_STA_2_PAR_D_FAULT (3891L)\n+#define MAC_PCS_XXV_ANEG_STA_2_RS_FEC_EN (3892L)\n+#define MAC_PCS_XXV_ANEG_STA_2_RX_PAUSE_EN (3893L)\n+#define MAC_PCS_XXV_ANEG_STA_2_TX_PAUSE_EN (3894L)\n+#define MAC_PCS_XXV_ANEG_STA_3 (3895L)\n+#define MAC_PCS_XXV_ANEG_STA_3_COMPLETE (3896L)\n+#define MAC_PCS_XXV_ANEG_STA_3_FEC74_EN (3897L)\n+#define MAC_PCS_XXV_ANEG_STA_3_PAR_D_FAULT (3898L)\n+#define MAC_PCS_XXV_ANEG_STA_3_RS_FEC_EN (3899L)\n+#define MAC_PCS_XXV_ANEG_STA_3_RX_PAUSE_EN (3900L)\n+#define MAC_PCS_XXV_ANEG_STA_3_TX_PAUSE_EN (3901L)\n+#define MAC_PCS_XXV_CLK_REF_ACTIVITY (3902L)\n+#define MAC_PCS_XXV_CLK_REF_ACTIVITY_COUNT (3903L)\n+#define MAC_PCS_XXV_CORE_CONF_0 (3904L)\n+#define MAC_PCS_XXV_CORE_CONF_0_ENHANCED_TS (3905L)\n+#define MAC_PCS_XXV_CORE_CONF_0_INLINE_MODE (3906L)\n+#define MAC_PCS_XXV_CORE_CONF_0_LINE_LOOPBACK (3907L)\n+#define MAC_PCS_XXV_CORE_CONF_0_RX_ENABLE (3908L)\n+#define MAC_PCS_XXV_CORE_CONF_0_RX_FORCE_RESYNC (3909L)\n+#define MAC_PCS_XXV_CORE_CONF_0_TS_AT_EOP (3910L)\n+#define MAC_PCS_XXV_CORE_CONF_0_TX_ENABLE (3911L)\n+#define MAC_PCS_XXV_CORE_CONF_0_TX_IGN_FCS (3912L)\n+#define MAC_PCS_XXV_CORE_CONF_0_TX_INS_FCS (3913L)\n+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_IDLE (3914L)\n+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_LFI (3915L)\n+#define MAC_PCS_XXV_CORE_CONF_0_TX_SEND_RFI (3916L)\n+#define MAC_PCS_XXV_CORE_CONF_1 (3917L)\n+#define MAC_PCS_XXV_CORE_CONF_1_ENHANCED_TS (3918L)\n+#define MAC_PCS_XXV_CORE_CONF_1_INLINE_MODE (3919L)\n+#define MAC_PCS_XXV_CORE_CONF_1_LINE_LOOPBACK (3920L)\n+#define MAC_PCS_XXV_CORE_CONF_1_RX_ENABLE (3921L)\n+#define MAC_PCS_XXV_CORE_CONF_1_RX_FORCE_RESYNC (3922L)\n+#define MAC_PCS_XXV_CORE_CONF_1_TS_AT_EOP (3923L)\n+#define MAC_PCS_XXV_CORE_CONF_1_TX_ENABLE (3924L)\n+#define MAC_PCS_XXV_CORE_CONF_1_TX_IGN_FCS (3925L)\n+#define MAC_PCS_XXV_CORE_CONF_1_TX_INS_FCS (3926L)\n+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_IDLE (3927L)\n+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_LFI (3928L)\n+#define MAC_PCS_XXV_CORE_CONF_1_TX_SEND_RFI (3929L)\n+#define MAC_PCS_XXV_CORE_CONF_2 (3930L)\n+#define MAC_PCS_XXV_CORE_CONF_2_ENHANCED_TS (3931L)\n+#define MAC_PCS_XXV_CORE_CONF_2_INLINE_MODE (3932L)\n+#define MAC_PCS_XXV_CORE_CONF_2_LINE_LOOPBACK (3933L)\n+#define MAC_PCS_XXV_CORE_CONF_2_RX_ENABLE (3934L)\n+#define MAC_PCS_XXV_CORE_CONF_2_RX_FORCE_RESYNC (3935L)\n+#define MAC_PCS_XXV_CORE_CONF_2_TS_AT_EOP (3936L)\n+#define MAC_PCS_XXV_CORE_CONF_2_TX_ENABLE (3937L)\n+#define MAC_PCS_XXV_CORE_CONF_2_TX_IGN_FCS (3938L)\n+#define MAC_PCS_XXV_CORE_CONF_2_TX_INS_FCS (3939L)\n+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_IDLE (3940L)\n+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_LFI (3941L)\n+#define MAC_PCS_XXV_CORE_CONF_2_TX_SEND_RFI (3942L)\n+#define MAC_PCS_XXV_CORE_CONF_3 (3943L)\n+#define MAC_PCS_XXV_CORE_CONF_3_ENHANCED_TS (3944L)\n+#define MAC_PCS_XXV_CORE_CONF_3_INLINE_MODE (3945L)\n+#define MAC_PCS_XXV_CORE_CONF_3_LINE_LOOPBACK (3946L)\n+#define MAC_PCS_XXV_CORE_CONF_3_RX_ENABLE (3947L)\n+#define MAC_PCS_XXV_CORE_CONF_3_RX_FORCE_RESYNC (3948L)\n+#define MAC_PCS_XXV_CORE_CONF_3_TS_AT_EOP (3949L)\n+#define MAC_PCS_XXV_CORE_CONF_3_TX_ENABLE (3950L)\n+#define MAC_PCS_XXV_CORE_CONF_3_TX_IGN_FCS (3951L)\n+#define MAC_PCS_XXV_CORE_CONF_3_TX_INS_FCS (3952L)\n+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_IDLE (3953L)\n+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_LFI (3954L)\n+#define MAC_PCS_XXV_CORE_CONF_3_TX_SEND_RFI (3955L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0 (3956L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_DEBOUNCE_LATENCY (3957L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_FORCE_LINK_DOWN (3958L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_LINKUP_LATENCY (3959L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_0_NT_PORT_CTRL (3960L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1 (3961L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_DEBOUNCE_LATENCY (3962L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_FORCE_LINK_DOWN (3963L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_LINKUP_LATENCY (3964L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_1_NT_PORT_CTRL (3965L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2 (3966L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_DEBOUNCE_LATENCY (3967L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_FORCE_LINK_DOWN (3968L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_LINKUP_LATENCY (3969L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_2_NT_PORT_CTRL (3970L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3 (3971L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_DEBOUNCE_LATENCY (3972L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_FORCE_LINK_DOWN (3973L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_LINKUP_LATENCY (3974L)\n+#define MAC_PCS_XXV_DEBOUNCE_CTRL_3_NT_PORT_CTRL (3975L)\n+#define MAC_PCS_XXV_FEC74_CCW_CNT_0 (3976L)\n+#define MAC_PCS_XXV_FEC74_CCW_CNT_0_FEC74_CCW_CNT (3977L)\n+#define MAC_PCS_XXV_FEC74_CCW_CNT_1 (3978L)\n+#define MAC_PCS_XXV_FEC74_CCW_CNT_1_FEC74_CCW_CNT (3979L)\n+#define MAC_PCS_XXV_FEC74_CCW_CNT_2 (3980L)\n+#define MAC_PCS_XXV_FEC74_CCW_CNT_2_FEC74_CCW_CNT (3981L)\n+#define MAC_PCS_XXV_FEC74_CCW_CNT_3 (3982L)\n+#define MAC_PCS_XXV_FEC74_CCW_CNT_3_FEC74_CCW_CNT (3983L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_0 (3984L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_0_FEC74_ERRORS_TO_PCS (3985L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_0_RX_FEC74_ENABLE (3986L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_0_TX_FEC74_ENABLE (3987L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_1 (3988L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_1_FEC74_ERRORS_TO_PCS (3989L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_1_RX_FEC74_ENABLE (3990L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_1_TX_FEC74_ENABLE (3991L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_2 (3992L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_2_FEC74_ERRORS_TO_PCS (3993L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_2_RX_FEC74_ENABLE (3994L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_2_TX_FEC74_ENABLE (3995L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_3 (3996L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_3_FEC74_ERRORS_TO_PCS (3997L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_3_RX_FEC74_ENABLE (3998L)\n+#define MAC_PCS_XXV_FEC74_CONFIG_3_TX_FEC74_ENABLE (3999L)\n+#define MAC_PCS_XXV_FEC74_UCW_CNT_0 (4000L)\n+#define MAC_PCS_XXV_FEC74_UCW_CNT_0_FEC74_UCW_CNT (4001L)\n+#define MAC_PCS_XXV_FEC74_UCW_CNT_1 (4002L)\n+#define MAC_PCS_XXV_FEC74_UCW_CNT_1_FEC74_UCW_CNT (4003L)\n+#define MAC_PCS_XXV_FEC74_UCW_CNT_2 (4004L)\n+#define MAC_PCS_XXV_FEC74_UCW_CNT_2_FEC74_UCW_CNT (4005L)\n+#define MAC_PCS_XXV_FEC74_UCW_CNT_3 (4006L)\n+#define MAC_PCS_XXV_FEC74_UCW_CNT_3_FEC74_UCW_CNT (4007L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_0 (4008L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_0_CDR_HOLD (4009L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_0_EQUA_RST (4010L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_0_LPM_EN (4011L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_0_POLARITY (4012L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_0_RATE (4013L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_1 (4014L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_1_CDR_HOLD (4015L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_1_EQUA_RST (4016L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_1_LPM_EN (4017L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_1_POLARITY (4018L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_1_RATE (4019L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_2 (4020L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_2_CDR_HOLD (4021L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_2_EQUA_RST (4022L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_2_LPM_EN (4023L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_2_POLARITY (4024L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_2_RATE (4025L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_3 (4026L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_3_CDR_HOLD (4027L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_3_EQUA_RST (4028L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_3_LPM_EN (4029L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_3_POLARITY (4030L)\n+#define MAC_PCS_XXV_GTY_CTL_RX_3_RATE (4031L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_0 (4032L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_0_INHIBIT (4033L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_0_POLARITY (4034L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_1 (4035L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_1_INHIBIT (4036L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_1_POLARITY (4037L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_2 (4038L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_2_INHIBIT (4039L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_2_POLARITY (4040L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_3 (4041L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_3_INHIBIT (4042L)\n+#define MAC_PCS_XXV_GTY_CTL_TX_3_POLARITY (4043L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_0 (4044L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL (4045L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_0_TX_DIFF_CTL_ADJUSTED (4046L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_1 (4047L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL (4048L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_1_TX_DIFF_CTL_ADJUSTED (4049L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_2 (4050L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL (4051L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_2_TX_DIFF_CTL_ADJUSTED (4052L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_3 (4053L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL (4054L)\n+#define MAC_PCS_XXV_GTY_DIFF_CTL_3_TX_DIFF_CTL_ADJUSTED (4055L)\n+#define MAC_PCS_XXV_GTY_LOOP_0 (4056L)\n+#define MAC_PCS_XXV_GTY_LOOP_0_GT_LOOP (4057L)\n+#define MAC_PCS_XXV_GTY_LOOP_1 (4058L)\n+#define MAC_PCS_XXV_GTY_LOOP_1_GT_LOOP (4059L)\n+#define MAC_PCS_XXV_GTY_LOOP_2 (4060L)\n+#define MAC_PCS_XXV_GTY_LOOP_2_GT_LOOP (4061L)\n+#define MAC_PCS_XXV_GTY_LOOP_3 (4062L)\n+#define MAC_PCS_XXV_GTY_LOOP_3_GT_LOOP (4063L)\n+#define MAC_PCS_XXV_GTY_MAIN_CTL_0 (4064L)\n+#define MAC_PCS_XXV_GTY_MAIN_CTL_0_TX_MAIN_CTL (4065L)\n+#define MAC_PCS_XXV_GTY_MAIN_CTL_1 (4066L)\n+#define MAC_PCS_XXV_GTY_MAIN_CTL_1_TX_MAIN_CTL (4067L)\n+#define MAC_PCS_XXV_GTY_MAIN_CTL_2 (4068L)\n+#define MAC_PCS_XXV_GTY_MAIN_CTL_2_TX_MAIN_CTL (4069L)\n+#define MAC_PCS_XXV_GTY_MAIN_CTL_3 (4070L)\n+#define MAC_PCS_XXV_GTY_MAIN_CTL_3_TX_MAIN_CTL (4071L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_0 (4072L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR (4073L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_0_TX_POST_CSR_ADJUSTED (4074L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_1 (4075L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR (4076L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_1_TX_POST_CSR_ADJUSTED (4077L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_2 (4078L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR (4079L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_2_TX_POST_CSR_ADJUSTED (4080L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_3 (4081L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR (4082L)\n+#define MAC_PCS_XXV_GTY_POST_CURSOR_3_TX_POST_CSR_ADJUSTED (4083L)\n+#define MAC_PCS_XXV_GTY_PRBS_0 (4084L)\n+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR (4085L)\n+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_ERR_INS (4086L)\n+#define MAC_PCS_XXV_GTY_PRBS_0_PRBS_RST (4087L)\n+#define MAC_PCS_XXV_GTY_PRBS_0_RX_PRBS_SEL (4088L)\n+#define MAC_PCS_XXV_GTY_PRBS_0_TX_PRBS_SEL (4089L)\n+#define MAC_PCS_XXV_GTY_PRBS_1 (4090L)\n+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR (4091L)\n+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_ERR_INS (4092L)\n+#define MAC_PCS_XXV_GTY_PRBS_1_PRBS_RST (4093L)\n+#define MAC_PCS_XXV_GTY_PRBS_1_RX_PRBS_SEL (4094L)\n+#define MAC_PCS_XXV_GTY_PRBS_1_TX_PRBS_SEL (4095L)\n+#define MAC_PCS_XXV_GTY_PRBS_2 (4096L)\n+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR (4097L)\n+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_ERR_INS (4098L)\n+#define MAC_PCS_XXV_GTY_PRBS_2_PRBS_RST (4099L)\n+#define MAC_PCS_XXV_GTY_PRBS_2_RX_PRBS_SEL (4100L)\n+#define MAC_PCS_XXV_GTY_PRBS_2_TX_PRBS_SEL (4101L)\n+#define MAC_PCS_XXV_GTY_PRBS_3 (4102L)\n+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR (4103L)\n+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_ERR_INS (4104L)\n+#define MAC_PCS_XXV_GTY_PRBS_3_PRBS_RST (4105L)\n+#define MAC_PCS_XXV_GTY_PRBS_3_RX_PRBS_SEL (4106L)\n+#define MAC_PCS_XXV_GTY_PRBS_3_TX_PRBS_SEL (4107L)\n+#define MAC_PCS_XXV_GTY_PRBS_CNT_0 (4108L)\n+#define MAC_PCS_XXV_GTY_PRBS_CNT_0_COUNT (4109L)\n+#define MAC_PCS_XXV_GTY_PRBS_CNT_1 (4110L)\n+#define MAC_PCS_XXV_GTY_PRBS_CNT_1_COUNT (4111L)\n+#define MAC_PCS_XXV_GTY_PRBS_CNT_2 (4112L)\n+#define MAC_PCS_XXV_GTY_PRBS_CNT_2_COUNT (4113L)\n+#define MAC_PCS_XXV_GTY_PRBS_CNT_3 (4114L)\n+#define MAC_PCS_XXV_GTY_PRBS_CNT_3_COUNT (4115L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0 (4116L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR (4117L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_0_TX_PRE_CSR_ADJUSTED (4118L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1 (4119L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR (4120L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_1_TX_PRE_CSR_ADJUSTED (4121L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2 (4122L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR (4123L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_2_TX_PRE_CSR_ADJUSTED (4124L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3 (4125L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR (4126L)\n+#define MAC_PCS_XXV_GTY_PRE_CURSOR_3_TX_PRE_CSR_ADJUSTED (4127L)\n+#define MAC_PCS_XXV_GTY_STATUS_0 (4128L)\n+#define MAC_PCS_XXV_GTY_STATUS_0_GT_POWERGOOD (4129L)\n+#define MAC_PCS_XXV_GTY_STATUS_0_GT_RXBUFSTATUS (4130L)\n+#define MAC_PCS_XXV_GTY_STATUS_0_GT_STARTOFSEQ (4131L)\n+#define MAC_PCS_XXV_GTY_STATUS_0_GT_TXBUFSTATUS (4132L)\n+#define MAC_PCS_XXV_GTY_STATUS_1 (4133L)\n+#define MAC_PCS_XXV_GTY_STATUS_1_GT_POWERGOOD (4134L)\n+#define MAC_PCS_XXV_GTY_STATUS_1_GT_RXBUFSTATUS (4135L)\n+#define MAC_PCS_XXV_GTY_STATUS_1_GT_STARTOFSEQ (4136L)\n+#define MAC_PCS_XXV_GTY_STATUS_1_GT_TXBUFSTATUS (4137L)\n+#define MAC_PCS_XXV_GTY_STATUS_2 (4138L)\n+#define MAC_PCS_XXV_GTY_STATUS_2_GT_POWERGOOD (4139L)\n+#define MAC_PCS_XXV_GTY_STATUS_2_GT_RXBUFSTATUS (4140L)\n+#define MAC_PCS_XXV_GTY_STATUS_2_GT_STARTOFSEQ (4141L)\n+#define MAC_PCS_XXV_GTY_STATUS_2_GT_TXBUFSTATUS (4142L)\n+#define MAC_PCS_XXV_GTY_STATUS_3 (4143L)\n+#define MAC_PCS_XXV_GTY_STATUS_3_GT_POWERGOOD (4144L)\n+#define MAC_PCS_XXV_GTY_STATUS_3_GT_RXBUFSTATUS (4145L)\n+#define MAC_PCS_XXV_GTY_STATUS_3_GT_STARTOFSEQ (4146L)\n+#define MAC_PCS_XXV_GTY_STATUS_3_GT_TXBUFSTATUS (4147L)\n+#define MAC_PCS_XXV_LATENCY_0 (4148L)\n+#define MAC_PCS_XXV_LATENCY_0_RX_LATENCY_MEAS (4149L)\n+#define MAC_PCS_XXV_LATENCY_1 (4150L)\n+#define MAC_PCS_XXV_LATENCY_1_RX_LATENCY_MEAS (4151L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0 (4152L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_MAIN (4153L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_POST (4154L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_DEC_PRE (4155L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_MAIN (4156L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_POST (4157L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INC_PRE (4158L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_INIT (4159L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_0_PRESET (4160L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1 (4161L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_MAIN (4162L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_POST (4163L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_DEC_PRE (4164L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_MAIN (4165L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_POST (4166L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INC_PRE (4167L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_INIT (4168L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_1_PRESET (4169L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2 (4170L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_MAIN (4171L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_POST (4172L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_DEC_PRE (4173L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_MAIN (4174L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_POST (4175L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INC_PRE (4176L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_INIT (4177L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_2_PRESET (4178L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3 (4179L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_MAIN (4180L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_POST (4181L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_DEC_PRE (4182L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_MAIN (4183L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_POST (4184L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INC_PRE (4185L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_INIT (4186L)\n+#define MAC_PCS_XXV_LE_LT_COEF_RECEIVED_3_PRESET (4187L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_0 (4188L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_MAIN_STA (4189L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_POST_STA (4190L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_0_PRE_STA (4191L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_1 (4192L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_MAIN_STA (4193L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_POST_STA (4194L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_1_PRE_STA (4195L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_2 (4196L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_MAIN_STA (4197L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_POST_STA (4198L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_2_PRE_STA (4199L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_3 (4200L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_MAIN_STA (4201L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_POST_STA (4202L)\n+#define MAC_PCS_XXV_LE_LT_STA_SEND_3_PRE_STA (4203L)\n+#define MAC_PCS_XXV_LINK_SPEED_0 (4204L)\n+#define MAC_PCS_XXV_LINK_SPEED_0_10G (4205L)\n+#define MAC_PCS_XXV_LINK_SPEED_0_SPEED (4206L)\n+#define MAC_PCS_XXV_LINK_SPEED_0_TOGGLE (4207L)\n+#define MAC_PCS_XXV_LINK_SPEED_1 (4208L)\n+#define MAC_PCS_XXV_LINK_SPEED_1_10G (4209L)\n+#define MAC_PCS_XXV_LINK_SPEED_1_SPEED (4210L)\n+#define MAC_PCS_XXV_LINK_SPEED_1_TOGGLE (4211L)\n+#define MAC_PCS_XXV_LINK_SPEED_2 (4212L)\n+#define MAC_PCS_XXV_LINK_SPEED_2_10G (4213L)\n+#define MAC_PCS_XXV_LINK_SPEED_2_SPEED (4214L)\n+#define MAC_PCS_XXV_LINK_SPEED_2_TOGGLE (4215L)\n+#define MAC_PCS_XXV_LINK_SPEED_3 (4216L)\n+#define MAC_PCS_XXV_LINK_SPEED_3_10G (4217L)\n+#define MAC_PCS_XXV_LINK_SPEED_3_SPEED (4218L)\n+#define MAC_PCS_XXV_LINK_SPEED_3_TOGGLE (4219L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0 (4220L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_ABS (4221L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_COMPLETE (4222L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_ANEG_CONSORTIUM_MISMATCH (4223L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_INTERNAL_LOCAL_FAULT (4224L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_ABS (4225L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_INTERNAL_LOCAL_FAULT (4226L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_LOCAL_FAULT (4227L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RECEIVED_LOCAL_FAULT (4228L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_REMOTE_FAULT (4229L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_FEC74_LOCK_ERROR (4230L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_HIGH_BIT_ERROR_RATE (4231L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_PCS_VALID_CTRL_CODE (4232L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_RX_RSFEC_HI_SER (4233L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_LOCAL_FAULT (4234L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LH_TX_UNDERRUN (4235L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LINK_DOWN_CNT (4236L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_PHY_LINK_STATE (4237L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_BLOCK_LOCK (4238L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_FEC74_LOCK (4239L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_RX_RSFEC_LANE_ALIGNMENT (4240L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LL_TX_RSFEC_LANE_ALIGNMENT (4241L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_LT_DONE (4242L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_NIM_INTERR (4243L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_0_NT_PHY_LINK_STATE (4244L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1 (4245L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_ABS (4246L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_COMPLETE (4247L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_ANEG_CONSORTIUM_MISMATCH (4248L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_INTERNAL_LOCAL_FAULT (4249L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_ABS (4250L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_INTERNAL_LOCAL_FAULT (4251L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_LOCAL_FAULT (4252L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RECEIVED_LOCAL_FAULT (4253L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_REMOTE_FAULT (4254L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_FEC74_LOCK_ERROR (4255L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_HIGH_BIT_ERROR_RATE (4256L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_PCS_VALID_CTRL_CODE (4257L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_RX_RSFEC_HI_SER (4258L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_LOCAL_FAULT (4259L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LH_TX_UNDERRUN (4260L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LINK_DOWN_CNT (4261L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_PHY_LINK_STATE (4262L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_BLOCK_LOCK (4263L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_FEC74_LOCK (4264L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_RX_RSFEC_LANE_ALIGNMENT (4265L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LL_TX_RSFEC_LANE_ALIGNMENT (4266L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_LT_DONE (4267L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_NIM_INTERR (4268L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_1_NT_PHY_LINK_STATE (4269L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2 (4270L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_ABS (4271L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_COMPLETE (4272L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_ANEG_CONSORTIUM_MISMATCH (4273L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_INTERNAL_LOCAL_FAULT (4274L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_ABS (4275L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_INTERNAL_LOCAL_FAULT (4276L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_LOCAL_FAULT (4277L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RECEIVED_LOCAL_FAULT (4278L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_REMOTE_FAULT (4279L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_FEC74_LOCK_ERROR (4280L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_HIGH_BIT_ERROR_RATE (4281L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_PCS_VALID_CTRL_CODE (4282L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_RX_RSFEC_HI_SER (4283L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_LOCAL_FAULT (4284L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LH_TX_UNDERRUN (4285L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LINK_DOWN_CNT (4286L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_PHY_LINK_STATE (4287L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_BLOCK_LOCK (4288L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_FEC74_LOCK (4289L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_RX_RSFEC_LANE_ALIGNMENT (4290L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LL_TX_RSFEC_LANE_ALIGNMENT (4291L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_LT_DONE (4292L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_NIM_INTERR (4293L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_2_NT_PHY_LINK_STATE (4294L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3 (4295L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_ABS (4296L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_COMPLETE (4297L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_ANEG_CONSORTIUM_MISMATCH (4298L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_INTERNAL_LOCAL_FAULT (4299L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_ABS (4300L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_INTERNAL_LOCAL_FAULT (4301L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_LOCAL_FAULT (4302L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RECEIVED_LOCAL_FAULT (4303L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_REMOTE_FAULT (4304L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_FEC74_LOCK_ERROR (4305L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_HIGH_BIT_ERROR_RATE (4306L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_PCS_VALID_CTRL_CODE (4307L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_RX_RSFEC_HI_SER (4308L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_LOCAL_FAULT (4309L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LH_TX_UNDERRUN (4310L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LINK_DOWN_CNT (4311L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_PHY_LINK_STATE (4312L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_BLOCK_LOCK (4313L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_FEC74_LOCK (4314L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_RX_RSFEC_LANE_ALIGNMENT (4315L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LL_TX_RSFEC_LANE_ALIGNMENT (4316L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_LT_DONE (4317L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_NIM_INTERR (4318L)\n+#define MAC_PCS_XXV_LINK_SUMMARY_3_NT_PHY_LINK_STATE (4319L)\n+#define MAC_PCS_XXV_LT_CONF_0 (4320L)\n+#define MAC_PCS_XXV_LT_CONF_0_ENABLE (4321L)\n+#define MAC_PCS_XXV_LT_CONF_0_RESTART (4322L)\n+#define MAC_PCS_XXV_LT_CONF_0_SEED (4323L)\n+#define MAC_PCS_XXV_LT_CONF_1 (4324L)\n+#define MAC_PCS_XXV_LT_CONF_1_ENABLE (4325L)\n+#define MAC_PCS_XXV_LT_CONF_1_RESTART (4326L)\n+#define MAC_PCS_XXV_LT_CONF_1_SEED (4327L)\n+#define MAC_PCS_XXV_LT_CONF_2 (4328L)\n+#define MAC_PCS_XXV_LT_CONF_2_ENABLE (4329L)\n+#define MAC_PCS_XXV_LT_CONF_2_RESTART (4330L)\n+#define MAC_PCS_XXV_LT_CONF_2_SEED (4331L)\n+#define MAC_PCS_XXV_LT_CONF_3 (4332L)\n+#define MAC_PCS_XXV_LT_CONF_3_ENABLE (4333L)\n+#define MAC_PCS_XXV_LT_CONF_3_RESTART (4334L)\n+#define MAC_PCS_XXV_LT_CONF_3_SEED (4335L)\n+#define MAC_PCS_XXV_LT_STA_0 (4336L)\n+#define MAC_PCS_XXV_LT_STA_0_DONE (4337L)\n+#define MAC_PCS_XXV_LT_STA_0_FAIL (4338L)\n+#define MAC_PCS_XXV_LT_STA_0_LOCK (4339L)\n+#define MAC_PCS_XXV_LT_STA_0_TRAIN (4340L)\n+#define MAC_PCS_XXV_LT_STA_1 (4341L)\n+#define MAC_PCS_XXV_LT_STA_1_DONE (4342L)\n+#define MAC_PCS_XXV_LT_STA_1_FAIL (4343L)\n+#define MAC_PCS_XXV_LT_STA_1_LOCK (4344L)\n+#define MAC_PCS_XXV_LT_STA_1_TRAIN (4345L)\n+#define MAC_PCS_XXV_LT_STA_2 (4346L)\n+#define MAC_PCS_XXV_LT_STA_2_DONE (4347L)\n+#define MAC_PCS_XXV_LT_STA_2_FAIL (4348L)\n+#define MAC_PCS_XXV_LT_STA_2_LOCK (4349L)\n+#define MAC_PCS_XXV_LT_STA_2_TRAIN (4350L)\n+#define MAC_PCS_XXV_LT_STA_3 (4351L)\n+#define MAC_PCS_XXV_LT_STA_3_DONE (4352L)\n+#define MAC_PCS_XXV_LT_STA_3_FAIL (4353L)\n+#define MAC_PCS_XXV_LT_STA_3_LOCK (4354L)\n+#define MAC_PCS_XXV_LT_STA_3_TRAIN (4355L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_0 (4356L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_ATTRIB (4357L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_NEXT (4358L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_0_PREV (4359L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_1 (4360L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_ATTRIB (4361L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_NEXT (4362L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_1_PREV (4363L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_2 (4364L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_ATTRIB (4365L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_NEXT (4366L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_2_PREV (4367L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_3 (4368L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_ATTRIB (4369L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_NEXT (4370L)\n+#define MAC_PCS_XXV_LT_TABLE_READBACK_3_PREV (4371L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0 (4372L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_ATTRIB (4373L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_NEXT (4374L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_PREV (4375L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_SEL (4376L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_TABLE_ADDR (4377L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_0_UPDATE (4378L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1 (4379L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_ATTRIB (4380L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_NEXT (4381L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_PREV (4382L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_SEL (4383L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_TABLE_ADDR (4384L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_1_UPDATE (4385L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2 (4386L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_ATTRIB (4387L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_NEXT (4388L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_PREV (4389L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_SEL (4390L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_TABLE_ADDR (4391L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_2_UPDATE (4392L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3 (4393L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_ATTRIB (4394L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_NEXT (4395L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_PREV (4396L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_SEL (4397L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_TABLE_ADDR (4398L)\n+#define MAC_PCS_XXV_LT_UPDATE_COEF_TABLE_3_UPDATE (4399L)\n+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0 (4400L)\n+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_0_RX_MAX_LENGTH (4401L)\n+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1 (4402L)\n+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_1_RX_MAX_LENGTH (4403L)\n+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2 (4404L)\n+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_2_RX_MAX_LENGTH (4405L)\n+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3 (4406L)\n+#define MAC_PCS_XXV_MAC_RX_MAX_LENGTH_3_RX_MAX_LENGTH (4407L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0 (4408L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_MIN_RX_FRAME (4409L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_0_RX_MIN_LENGTH (4410L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1 (4411L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_MIN_RX_FRAME (4412L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_1_RX_MIN_LENGTH (4413L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2 (4414L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_MIN_RX_FRAME (4415L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_2_RX_MIN_LENGTH (4416L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3 (4417L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_MIN_RX_FRAME (4418L)\n+#define MAC_PCS_XXV_MAC_RX_MIN_LENGTH_3_RX_MIN_LENGTH (4419L)\n+#define MAC_PCS_XXV_MAX_PKT_LEN_0 (4420L)\n+#define MAC_PCS_XXV_MAX_PKT_LEN_0_MAX_LEN (4421L)\n+#define MAC_PCS_XXV_MAX_PKT_LEN_1 (4422L)\n+#define MAC_PCS_XXV_MAX_PKT_LEN_1_MAX_LEN (4423L)\n+#define MAC_PCS_XXV_MAX_PKT_LEN_2 (4424L)\n+#define MAC_PCS_XXV_MAX_PKT_LEN_2_MAX_LEN (4425L)\n+#define MAC_PCS_XXV_MAX_PKT_LEN_3 (4426L)\n+#define MAC_PCS_XXV_MAX_PKT_LEN_3_MAX_LEN (4427L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0 (4428L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_MAIN (4429L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_POST (4430L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ADJ_PRE (4431L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_ENABLE (4432L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_INIT (4433L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_PRESET (4434L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_0_RX_READY (4435L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1 (4436L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_MAIN (4437L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_POST (4438L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ADJ_PRE (4439L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_ENABLE (4440L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_INIT (4441L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_PRESET (4442L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_1_RX_READY (4443L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2 (4444L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_MAIN (4445L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_POST (4446L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ADJ_PRE (4447L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_ENABLE (4448L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_INIT (4449L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_PRESET (4450L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_2_RX_READY (4451L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3 (4452L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_MAIN (4453L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_POST (4454L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ADJ_PRE (4455L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_ENABLE (4456L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_INIT (4457L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_PRESET (4458L)\n+#define MAC_PCS_XXV_RE_LT_COEF_TO_TX_3_RX_READY (4459L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0 (4460L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_MAIN_STA (4461L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_POST_STA (4462L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_0_PRE_STA (4463L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1 (4464L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_MAIN_STA (4465L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_POST_STA (4466L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_1_PRE_STA (4467L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2 (4468L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_MAIN_STA (4469L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_POST_STA (4470L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_2_PRE_STA (4471L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3 (4472L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_MAIN_STA (4473L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_POST_STA (4474L)\n+#define MAC_PCS_XXV_RE_LT_STA_RECEIVED_3_PRE_STA (4475L)\n+#define MAC_PCS_XXV_RST_0 (4476L)\n+#define MAC_PCS_XXV_RST_0_MAC_PCS (4477L)\n+#define MAC_PCS_XXV_RST_1 (4478L)\n+#define MAC_PCS_XXV_RST_1_MAC_PCS (4479L)\n+#define MAC_PCS_XXV_RST_2 (4480L)\n+#define MAC_PCS_XXV_RST_2_MAC_PCS (4481L)\n+#define MAC_PCS_XXV_RST_3 (4482L)\n+#define MAC_PCS_XXV_RST_3_MAC_PCS (4483L)\n+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0 (4484L)\n+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_0_RS_FEC_CCW_CNT (4485L)\n+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1 (4486L)\n+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_1_RS_FEC_CCW_CNT (4487L)\n+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2 (4488L)\n+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_2_RS_FEC_CCW_CNT (4489L)\n+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3 (4490L)\n+#define MAC_PCS_XXV_RS_FEC_CCW_CNT_3_RS_FEC_CCW_CNT (4491L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_0 (4492L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_0_CONSORTIUM (4493L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_CORRECTION (4494L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_ENABLE (4495L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_IEEE_ERROR_INDICATION (4496L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_0_RS_FEC_INDICATION (4497L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_1 (4498L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_1_CONSORTIUM (4499L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_CORRECTION (4500L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_ENABLE (4501L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_IEEE_ERROR_INDICATION (4502L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_1_RS_FEC_INDICATION (4503L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_2 (4504L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_2_CONSORTIUM (4505L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_CORRECTION (4506L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_ENABLE (4507L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_IEEE_ERROR_INDICATION (4508L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_2_RS_FEC_INDICATION (4509L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_3 (4510L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_3_CONSORTIUM (4511L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_CORRECTION (4512L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_ENABLE (4513L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_IEEE_ERROR_INDICATION (4514L)\n+#define MAC_PCS_XXV_RS_FEC_CONF_3_RS_FEC_INDICATION (4515L)\n+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0 (4516L)\n+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_0_RS_FEC_ERR_CNT (4517L)\n+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1 (4518L)\n+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_1_RS_FEC_ERR_CNT (4519L)\n+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2 (4520L)\n+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_2_RS_FEC_ERR_CNT (4521L)\n+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3 (4522L)\n+#define MAC_PCS_XXV_RS_FEC_ERR_CNT_3_RS_FEC_ERR_CNT (4523L)\n+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0 (4524L)\n+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_0_RS_FEC_UCW_CNT (4525L)\n+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1 (4526L)\n+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_1_RS_FEC_UCW_CNT (4527L)\n+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2 (4528L)\n+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_2_RS_FEC_UCW_CNT (4529L)\n+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3 (4530L)\n+#define MAC_PCS_XXV_RS_FEC_UCW_CNT_3_RS_FEC_UCW_CNT (4531L)\n+#define MAC_PCS_XXV_RX_BAD_FCS_0 (4532L)\n+#define MAC_PCS_XXV_RX_BAD_FCS_0_COUNT (4533L)\n+#define MAC_PCS_XXV_RX_BAD_FCS_1 (4534L)\n+#define MAC_PCS_XXV_RX_BAD_FCS_1_COUNT (4535L)\n+#define MAC_PCS_XXV_RX_BAD_FCS_2 (4536L)\n+#define MAC_PCS_XXV_RX_BAD_FCS_2_COUNT (4537L)\n+#define MAC_PCS_XXV_RX_BAD_FCS_3 (4538L)\n+#define MAC_PCS_XXV_RX_BAD_FCS_3_COUNT (4539L)\n+#define MAC_PCS_XXV_RX_FRAMING_ERROR_0 (4540L)\n+#define MAC_PCS_XXV_RX_FRAMING_ERROR_0_COUNT (4541L)\n+#define MAC_PCS_XXV_RX_FRAMING_ERROR_1 (4542L)\n+#define MAC_PCS_XXV_RX_FRAMING_ERROR_1_COUNT (4543L)\n+#define MAC_PCS_XXV_RX_FRAMING_ERROR_2 (4544L)\n+#define MAC_PCS_XXV_RX_FRAMING_ERROR_2_COUNT (4545L)\n+#define MAC_PCS_XXV_RX_FRAMING_ERROR_3 (4546L)\n+#define MAC_PCS_XXV_RX_FRAMING_ERROR_3_COUNT (4547L)\n+#define MAC_PCS_XXV_RX_GOOD_BYTES_0 (4548L)\n+#define MAC_PCS_XXV_RX_GOOD_BYTES_0_COUNT (4549L)\n+#define MAC_PCS_XXV_RX_GOOD_BYTES_1 (4550L)\n+#define MAC_PCS_XXV_RX_GOOD_BYTES_1_COUNT (4551L)\n+#define MAC_PCS_XXV_RX_GOOD_BYTES_2 (4552L)\n+#define MAC_PCS_XXV_RX_GOOD_BYTES_2_COUNT (4553L)\n+#define MAC_PCS_XXV_RX_GOOD_BYTES_3 (4554L)\n+#define MAC_PCS_XXV_RX_GOOD_BYTES_3_COUNT (4555L)\n+#define MAC_PCS_XXV_RX_GOOD_PACKETS_0 (4556L)\n+#define MAC_PCS_XXV_RX_GOOD_PACKETS_0_COUNT (4557L)\n+#define MAC_PCS_XXV_RX_GOOD_PACKETS_1 (4558L)\n+#define MAC_PCS_XXV_RX_GOOD_PACKETS_1_COUNT (4559L)\n+#define MAC_PCS_XXV_RX_GOOD_PACKETS_2 (4560L)\n+#define MAC_PCS_XXV_RX_GOOD_PACKETS_2_COUNT (4561L)\n+#define MAC_PCS_XXV_RX_GOOD_PACKETS_3 (4562L)\n+#define MAC_PCS_XXV_RX_GOOD_PACKETS_3_COUNT (4563L)\n+#define MAC_PCS_XXV_RX_LATENCY_0 (4564L)\n+#define MAC_PCS_XXV_RX_LATENCY_0_LATENCY (4565L)\n+#define MAC_PCS_XXV_RX_LATENCY_1 (4566L)\n+#define MAC_PCS_XXV_RX_LATENCY_1_LATENCY (4567L)\n+#define MAC_PCS_XXV_RX_TOTAL_BYTES_0 (4568L)\n+#define MAC_PCS_XXV_RX_TOTAL_BYTES_0_COUNT (4569L)\n+#define MAC_PCS_XXV_RX_TOTAL_BYTES_1 (4570L)\n+#define MAC_PCS_XXV_RX_TOTAL_BYTES_1_COUNT (4571L)\n+#define MAC_PCS_XXV_RX_TOTAL_BYTES_2 (4572L)\n+#define MAC_PCS_XXV_RX_TOTAL_BYTES_2_COUNT (4573L)\n+#define MAC_PCS_XXV_RX_TOTAL_BYTES_3 (4574L)\n+#define MAC_PCS_XXV_RX_TOTAL_BYTES_3_COUNT (4575L)\n+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0 (4576L)\n+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_0_COUNT (4577L)\n+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1 (4578L)\n+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_1_COUNT (4579L)\n+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2 (4580L)\n+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_2_COUNT (4581L)\n+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3 (4582L)\n+#define MAC_PCS_XXV_RX_TOTAL_PACKETS_3_COUNT (4583L)\n+#define MAC_PCS_XXV_SUB_RST_0 (4584L)\n+#define MAC_PCS_XXV_SUB_RST_0_AN_LT (4585L)\n+#define MAC_PCS_XXV_SUB_RST_0_QPLL (4586L)\n+#define MAC_PCS_XXV_SUB_RST_0_RX_BUF (4587L)\n+#define MAC_PCS_XXV_SUB_RST_0_RX_GT_DATA (4588L)\n+#define MAC_PCS_XXV_SUB_RST_0_RX_MAC_PCS (4589L)\n+#define MAC_PCS_XXV_SUB_RST_0_RX_PCS (4590L)\n+#define MAC_PCS_XXV_SUB_RST_0_RX_PMA (4591L)\n+#define MAC_PCS_XXV_SUB_RST_0_SPEED_CTRL (4592L)\n+#define MAC_PCS_XXV_SUB_RST_0_TX_GT_DATA (4593L)\n+#define MAC_PCS_XXV_SUB_RST_0_TX_MAC_PCS (4594L)\n+#define MAC_PCS_XXV_SUB_RST_0_TX_PCS (4595L)\n+#define MAC_PCS_XXV_SUB_RST_0_TX_PMA (4596L)\n+#define MAC_PCS_XXV_SUB_RST_1 (4597L)\n+#define MAC_PCS_XXV_SUB_RST_1_AN_LT (4598L)\n+#define MAC_PCS_XXV_SUB_RST_1_QPLL (4599L)\n+#define MAC_PCS_XXV_SUB_RST_1_RX_BUF (4600L)\n+#define MAC_PCS_XXV_SUB_RST_1_RX_GT_DATA (4601L)\n+#define MAC_PCS_XXV_SUB_RST_1_RX_MAC_PCS (4602L)\n+#define MAC_PCS_XXV_SUB_RST_1_RX_PCS (4603L)\n+#define MAC_PCS_XXV_SUB_RST_1_RX_PMA (4604L)\n+#define MAC_PCS_XXV_SUB_RST_1_SPEED_CTRL (4605L)\n+#define MAC_PCS_XXV_SUB_RST_1_TX_GT_DATA (4606L)\n+#define MAC_PCS_XXV_SUB_RST_1_TX_MAC_PCS (4607L)\n+#define MAC_PCS_XXV_SUB_RST_1_TX_PCS (4608L)\n+#define MAC_PCS_XXV_SUB_RST_1_TX_PMA (4609L)\n+#define MAC_PCS_XXV_SUB_RST_2 (4610L)\n+#define MAC_PCS_XXV_SUB_RST_2_AN_LT (4611L)\n+#define MAC_PCS_XXV_SUB_RST_2_QPLL (4612L)\n+#define MAC_PCS_XXV_SUB_RST_2_RX_BUF (4613L)\n+#define MAC_PCS_XXV_SUB_RST_2_RX_GT_DATA (4614L)\n+#define MAC_PCS_XXV_SUB_RST_2_RX_MAC_PCS (4615L)\n+#define MAC_PCS_XXV_SUB_RST_2_RX_PCS (4616L)\n+#define MAC_PCS_XXV_SUB_RST_2_RX_PMA (4617L)\n+#define MAC_PCS_XXV_SUB_RST_2_SPEED_CTRL (4618L)\n+#define MAC_PCS_XXV_SUB_RST_2_TX_GT_DATA (4619L)\n+#define MAC_PCS_XXV_SUB_RST_2_TX_MAC_PCS (4620L)\n+#define MAC_PCS_XXV_SUB_RST_2_TX_PCS (4621L)\n+#define MAC_PCS_XXV_SUB_RST_2_TX_PMA (4622L)\n+#define MAC_PCS_XXV_SUB_RST_3 (4623L)\n+#define MAC_PCS_XXV_SUB_RST_3_AN_LT (4624L)\n+#define MAC_PCS_XXV_SUB_RST_3_QPLL (4625L)\n+#define MAC_PCS_XXV_SUB_RST_3_RX_BUF (4626L)\n+#define MAC_PCS_XXV_SUB_RST_3_RX_GT_DATA (4627L)\n+#define MAC_PCS_XXV_SUB_RST_3_RX_MAC_PCS (4628L)\n+#define MAC_PCS_XXV_SUB_RST_3_RX_PCS (4629L)\n+#define MAC_PCS_XXV_SUB_RST_3_RX_PMA (4630L)\n+#define MAC_PCS_XXV_SUB_RST_3_SPEED_CTRL (4631L)\n+#define MAC_PCS_XXV_SUB_RST_3_TX_GT_DATA (4632L)\n+#define MAC_PCS_XXV_SUB_RST_3_TX_MAC_PCS (4633L)\n+#define MAC_PCS_XXV_SUB_RST_3_TX_PCS (4634L)\n+#define MAC_PCS_XXV_SUB_RST_3_TX_PMA (4635L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_0 (4636L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_0_QPLL_LOCK (4637L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_RX_RST (4638L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_0_USER_TX_RST (4639L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_1 (4640L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_1_QPLL_LOCK (4641L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_RX_RST (4642L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_1_USER_TX_RST (4643L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_2 (4644L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_2_QPLL_LOCK (4645L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_RX_RST (4646L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_2_USER_TX_RST (4647L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_3 (4648L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_3_QPLL_LOCK (4649L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_RX_RST (4650L)\n+#define MAC_PCS_XXV_SUB_RST_STATUS_3_USER_TX_RST (4651L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_0 (4652L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_0_RX_DLY (4653L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_0_TX_DLY (4654L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_1 (4655L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_1_RX_DLY (4656L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_1_TX_DLY (4657L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_2 (4658L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_2_RX_DLY (4659L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_2_TX_DLY (4660L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_3 (4661L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_3_RX_DLY (4662L)\n+#define MAC_PCS_XXV_TIMESTAMP_COMP_3_TX_DLY (4663L)\n+#define MAC_PCS_XXV_TX_BAD_FCS_0 (4664L)\n+#define MAC_PCS_XXV_TX_BAD_FCS_0_COUNT (4665L)\n+#define MAC_PCS_XXV_TX_BAD_FCS_1 (4666L)\n+#define MAC_PCS_XXV_TX_BAD_FCS_1_COUNT (4667L)\n+#define MAC_PCS_XXV_TX_BAD_FCS_2 (4668L)\n+#define MAC_PCS_XXV_TX_BAD_FCS_2_COUNT (4669L)\n+#define MAC_PCS_XXV_TX_BAD_FCS_3 (4670L)\n+#define MAC_PCS_XXV_TX_BAD_FCS_3_COUNT (4671L)\n+#define MAC_PCS_XXV_TX_FRAME_ERROR_0 (4672L)\n+#define MAC_PCS_XXV_TX_FRAME_ERROR_0_COUNT (4673L)\n+#define MAC_PCS_XXV_TX_FRAME_ERROR_1 (4674L)\n+#define MAC_PCS_XXV_TX_FRAME_ERROR_1_COUNT (4675L)\n+#define MAC_PCS_XXV_TX_FRAME_ERROR_2 (4676L)\n+#define MAC_PCS_XXV_TX_FRAME_ERROR_2_COUNT (4677L)\n+#define MAC_PCS_XXV_TX_FRAME_ERROR_3 (4678L)\n+#define MAC_PCS_XXV_TX_FRAME_ERROR_3_COUNT (4679L)\n+#define MAC_PCS_XXV_TX_GOOD_BYTES_0 (4680L)\n+#define MAC_PCS_XXV_TX_GOOD_BYTES_0_COUNT (4681L)\n+#define MAC_PCS_XXV_TX_GOOD_BYTES_1 (4682L)\n+#define MAC_PCS_XXV_TX_GOOD_BYTES_1_COUNT (4683L)\n+#define MAC_PCS_XXV_TX_GOOD_BYTES_2 (4684L)\n+#define MAC_PCS_XXV_TX_GOOD_BYTES_2_COUNT (4685L)\n+#define MAC_PCS_XXV_TX_GOOD_BYTES_3 (4686L)\n+#define MAC_PCS_XXV_TX_GOOD_BYTES_3_COUNT (4687L)\n+#define MAC_PCS_XXV_TX_GOOD_PACKETS_0 (4688L)\n+#define MAC_PCS_XXV_TX_GOOD_PACKETS_0_COUNT (4689L)\n+#define MAC_PCS_XXV_TX_GOOD_PACKETS_1 (4690L)\n+#define MAC_PCS_XXV_TX_GOOD_PACKETS_1_COUNT (4691L)\n+#define MAC_PCS_XXV_TX_GOOD_PACKETS_2 (4692L)\n+#define MAC_PCS_XXV_TX_GOOD_PACKETS_2_COUNT (4693L)\n+#define MAC_PCS_XXV_TX_GOOD_PACKETS_3 (4694L)\n+#define MAC_PCS_XXV_TX_GOOD_PACKETS_3_COUNT (4695L)\n+#define MAC_PCS_XXV_TX_TOTAL_BYTES_0 (4696L)\n+#define MAC_PCS_XXV_TX_TOTAL_BYTES_0_COUNT (4697L)\n+#define MAC_PCS_XXV_TX_TOTAL_BYTES_1 (4698L)\n+#define MAC_PCS_XXV_TX_TOTAL_BYTES_1_COUNT (4699L)\n+#define MAC_PCS_XXV_TX_TOTAL_BYTES_2 (4700L)\n+#define MAC_PCS_XXV_TX_TOTAL_BYTES_2_COUNT (4701L)\n+#define MAC_PCS_XXV_TX_TOTAL_BYTES_3 (4702L)\n+#define MAC_PCS_XXV_TX_TOTAL_BYTES_3_COUNT (4703L)\n+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0 (4704L)\n+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_0_COUNT (4705L)\n+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1 (4706L)\n+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_1_COUNT (4707L)\n+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2 (4708L)\n+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_2_COUNT (4709L)\n+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3 (4710L)\n+#define MAC_PCS_XXV_TX_TOTAL_PACKETS_3_COUNT (4711L)\n+/* MAC_RX */\n+#define MAC_RX_BAD_FCS (4712L)\n+#define MAC_RX_BAD_FCS_COUNT (4713L)\n+#define MAC_RX_BAD_PREAMBLE (4714L)\n+#define MAC_RX_BAD_PREAMBLE_COUNT (4715L)\n+#define MAC_RX_BAD_SFD (4716L)\n+#define MAC_RX_BAD_SFD_COUNT (4717L)\n+#define MAC_RX_BROADCAST (4718L)\n+#define MAC_RX_BROADCAST_COUNT (4719L)\n+#define MAC_RX_FRAGMENT (4720L)\n+#define MAC_RX_FRAGMENT_COUNT (4721L)\n+#define MAC_RX_INRANGEERR (4722L)\n+#define MAC_RX_INRANGEERR_COUNT (4723L)\n+#define MAC_RX_JABBER (4724L)\n+#define MAC_RX_JABBER_COUNT (4725L)\n+#define MAC_RX_MULTICAST (4726L)\n+#define MAC_RX_MULTICAST_COUNT (4727L)\n+#define MAC_RX_OVERSIZE (4728L)\n+#define MAC_RX_OVERSIZE_COUNT (4729L)\n+#define MAC_RX_PACKET_1024_1518_BYTES (4730L)\n+#define MAC_RX_PACKET_1024_1518_BYTES_COUNT (4731L)\n+#define MAC_RX_PACKET_128_255_BYTES (4732L)\n+#define MAC_RX_PACKET_128_255_BYTES_COUNT (4733L)\n+#define MAC_RX_PACKET_1519_1522_BYTES (4734L)\n+#define MAC_RX_PACKET_1519_1522_BYTES_COUNT (4735L)\n+#define MAC_RX_PACKET_1523_1548_BYTES (4736L)\n+#define MAC_RX_PACKET_1523_1548_BYTES_COUNT (4737L)\n+#define MAC_RX_PACKET_1549_2047_BYTES (4738L)\n+#define MAC_RX_PACKET_1549_2047_BYTES_COUNT (4739L)\n+#define MAC_RX_PACKET_2048_4095_BYTES (4740L)\n+#define MAC_RX_PACKET_2048_4095_BYTES_COUNT (4741L)\n+#define MAC_RX_PACKET_256_511_BYTES (4742L)\n+#define MAC_RX_PACKET_256_511_BYTES_COUNT (4743L)\n+#define MAC_RX_PACKET_4096_8191_BYTES (4744L)\n+#define MAC_RX_PACKET_4096_8191_BYTES_COUNT (4745L)\n+#define MAC_RX_PACKET_512_1023_BYTES (4746L)\n+#define MAC_RX_PACKET_512_1023_BYTES_COUNT (4747L)\n+#define MAC_RX_PACKET_64_BYTES (4748L)\n+#define MAC_RX_PACKET_64_BYTES_COUNT (4749L)\n+#define MAC_RX_PACKET_65_127_BYTES (4750L)\n+#define MAC_RX_PACKET_65_127_BYTES_COUNT (4751L)\n+#define MAC_RX_PACKET_8192_9215_BYTES (4752L)\n+#define MAC_RX_PACKET_8192_9215_BYTES_COUNT (4753L)\n+#define MAC_RX_PACKET_BAD_FCS (4754L)\n+#define MAC_RX_PACKET_BAD_FCS_COUNT (4755L)\n+#define MAC_RX_PACKET_LARGE (4756L)\n+#define MAC_RX_PACKET_LARGE_COUNT (4757L)\n+#define MAC_RX_PACKET_SMALL (4758L)\n+#define MAC_RX_PACKET_SMALL_COUNT (4759L)\n+#define MAC_RX_STOMPED_FCS (4760L)\n+#define MAC_RX_STOMPED_FCS_COUNT (4761L)\n+#define MAC_RX_TOOLONG (4762L)\n+#define MAC_RX_TOOLONG_COUNT (4763L)\n+#define MAC_RX_TOTAL_BYTES (4764L)\n+#define MAC_RX_TOTAL_BYTES_COUNT (4765L)\n+#define MAC_RX_TOTAL_GOOD_BYTES (4766L)\n+#define MAC_RX_TOTAL_GOOD_BYTES_COUNT (4767L)\n+#define MAC_RX_TOTAL_GOOD_PACKETS (4768L)\n+#define MAC_RX_TOTAL_GOOD_PACKETS_COUNT (4769L)\n+#define MAC_RX_TOTAL_PACKETS (4770L)\n+#define MAC_RX_TOTAL_PACKETS_COUNT (4771L)\n+#define MAC_RX_TRUNCATED (4772L)\n+#define MAC_RX_TRUNCATED_COUNT (4773L)\n+#define MAC_RX_UNDERSIZE (4774L)\n+#define MAC_RX_UNDERSIZE_COUNT (4775L)\n+#define MAC_RX_UNICAST (4776L)\n+#define MAC_RX_UNICAST_COUNT (4777L)\n+#define MAC_RX_VLAN (4778L)\n+#define MAC_RX_VLAN_COUNT (4779L)\n+/* MAC_TFG */\n+#define MAC_TFG_TFG_ADDR (4780L)\n+#define MAC_TFG_TFG_ADDR_ADR (4781L)\n+#define MAC_TFG_TFG_ADDR_RDENA (4782L)\n+#define MAC_TFG_TFG_ADDR_RD_DONE (4783L)\n+#define MAC_TFG_TFG_CTRL (4784L)\n+#define MAC_TFG_TFG_CTRL_ID_ENA (4785L)\n+#define MAC_TFG_TFG_CTRL_ID_POS (4786L)\n+#define MAC_TFG_TFG_CTRL_RESTART (4787L)\n+#define MAC_TFG_TFG_CTRL_TG_ACT (4788L)\n+#define MAC_TFG_TFG_CTRL_TG_ENA (4789L)\n+#define MAC_TFG_TFG_CTRL_TIME_MODE (4790L)\n+#define MAC_TFG_TFG_CTRL_WRAP (4791L)\n+#define MAC_TFG_TFG_DATA (4792L)\n+#define MAC_TFG_TFG_DATA_GAP (4793L)\n+#define MAC_TFG_TFG_DATA_ID (4794L)\n+#define MAC_TFG_TFG_DATA_LENGTH (4795L)\n+#define MAC_TFG_TFG_FRAME_HDR (4796L)\n+#define MAC_TFG_TFG_FRAME_HDR_HDR (4797L)\n+#define MAC_TFG_TFG_REPETITION (4798L)\n+#define MAC_TFG_TFG_REPETITION_CNT (4799L)\n+/* MAC_TX */\n+#define MAC_TX_BAD_FCS (4800L)\n+#define MAC_TX_BAD_FCS_COUNT (4801L)\n+#define MAC_TX_BROADCAST (4802L)\n+#define MAC_TX_BROADCAST_COUNT (4803L)\n+#define MAC_TX_FRAME_ERRORS (4804L)\n+#define MAC_TX_FRAME_ERRORS_COUNT (4805L)\n+#define MAC_TX_MULTICAST (4806L)\n+#define MAC_TX_MULTICAST_COUNT (4807L)\n+#define MAC_TX_PACKET_1024_1518_BYTES (4808L)\n+#define MAC_TX_PACKET_1024_1518_BYTES_COUNT (4809L)\n+#define MAC_TX_PACKET_128_255_BYTES (4810L)\n+#define MAC_TX_PACKET_128_255_BYTES_COUNT (4811L)\n+#define MAC_TX_PACKET_1519_1522_BYTES (4812L)\n+#define MAC_TX_PACKET_1519_1522_BYTES_COUNT (4813L)\n+#define MAC_TX_PACKET_1523_1548_BYTES (4814L)\n+#define MAC_TX_PACKET_1523_1548_BYTES_COUNT (4815L)\n+#define MAC_TX_PACKET_1549_2047_BYTES (4816L)\n+#define MAC_TX_PACKET_1549_2047_BYTES_COUNT (4817L)\n+#define MAC_TX_PACKET_2048_4095_BYTES (4818L)\n+#define MAC_TX_PACKET_2048_4095_BYTES_COUNT (4819L)\n+#define MAC_TX_PACKET_256_511_BYTES (4820L)\n+#define MAC_TX_PACKET_256_511_BYTES_COUNT (4821L)\n+#define MAC_TX_PACKET_4096_8191_BYTES (4822L)\n+#define MAC_TX_PACKET_4096_8191_BYTES_COUNT (4823L)\n+#define MAC_TX_PACKET_512_1023_BYTES (4824L)\n+#define MAC_TX_PACKET_512_1023_BYTES_COUNT (4825L)\n+#define MAC_TX_PACKET_64_BYTES (4826L)\n+#define MAC_TX_PACKET_64_BYTES_COUNT (4827L)\n+#define MAC_TX_PACKET_65_127_BYTES (4828L)\n+#define MAC_TX_PACKET_65_127_BYTES_COUNT (4829L)\n+#define MAC_TX_PACKET_8192_9215_BYTES (4830L)\n+#define MAC_TX_PACKET_8192_9215_BYTES_COUNT (4831L)\n+#define MAC_TX_PACKET_LARGE (4832L)\n+#define MAC_TX_PACKET_LARGE_COUNT (4833L)\n+#define MAC_TX_PACKET_SMALL (4834L)\n+#define MAC_TX_PACKET_SMALL_COUNT (4835L)\n+#define MAC_TX_TOTAL_BYTES (4836L)\n+#define MAC_TX_TOTAL_BYTES_COUNT (4837L)\n+#define MAC_TX_TOTAL_GOOD_BYTES (4838L)\n+#define MAC_TX_TOTAL_GOOD_BYTES_COUNT (4839L)\n+#define MAC_TX_TOTAL_GOOD_PACKETS (4840L)\n+#define MAC_TX_TOTAL_GOOD_PACKETS_COUNT (4841L)\n+#define MAC_TX_TOTAL_PACKETS (4842L)\n+#define MAC_TX_TOTAL_PACKETS_COUNT (4843L)\n+#define MAC_TX_UNICAST (4844L)\n+#define MAC_TX_UNICAST_COUNT (4845L)\n+#define MAC_TX_VLAN (4846L)\n+#define MAC_TX_VLAN_COUNT (4847L)\n+/* MCU */\n+#define MCU_CSR (4848L)\n+#define MCU_CSR_HALT (4849L)\n+#define MCU_CSR_PAUSE (4850L)\n+#define MCU_CSR_RESET (4851L)\n+#define MCU_CSR_RESET_MCU (4852L)\n+#define MCU_DRAM_CTRL (4853L)\n+#define MCU_DRAM_CTRL_ADR (4854L)\n+#define MCU_DRAM_CTRL_CNT (4855L)\n+#define MCU_DRAM_RD_DATA (4856L)\n+#define MCU_DRAM_RD_DATA_DATA (4857L)\n+#define MCU_DRAM_WR_DATA (4858L)\n+#define MCU_DRAM_WR_DATA_DATA (4859L)\n+#define MCU_IRAM_CTRL (4860L)\n+#define MCU_IRAM_CTRL_ADR (4861L)\n+#define MCU_IRAM_CTRL_CNT (4862L)\n+#define MCU_IRAM_DATA (4863L)\n+#define MCU_IRAM_DATA_DATA (4864L)\n+/* MDG */\n+#define MDG_BSO_CTRL (4865L)\n+#define MDG_BSO_CTRL_ADR (4866L)\n+#define MDG_BSO_CTRL_CNT (4867L)\n+#define MDG_BSO_DATA (4868L)\n+#define MDG_BSO_DATA_OFFSET (4869L)\n+#define MDG_CONTROL (4870L)\n+#define MDG_CONTROL_AE (4871L)\n+#define MDG_CONTROL_AS (4872L)\n+#define MDG_CONTROL_CE (4873L)\n+#define MDG_CONTROL_EN (4874L)\n+#define MDG_DBG_EGS_FC0 (4875L)\n+#define MDG_DBG_EGS_FC0_BLOCKED (4876L)\n+#define MDG_DBG_EGS_FC1 (4877L)\n+#define MDG_DBG_EGS_FC1_BLOCKED (4878L)\n+#define MDG_DBG_EGS_FC2 (4879L)\n+#define MDG_DBG_EGS_FC2_BLOCKED (4880L)\n+#define MDG_DBG_EGS_FC3 (4881L)\n+#define MDG_DBG_EGS_FC3_BLOCKED (4882L)\n+#define MDG_DBG_HBM (4883L)\n+#define MDG_DBG_HBM_ADR (4884L)\n+#define MDG_DBG_HBM_MAIN (4885L)\n+#define MDG_DBG_HBM_MAP (4886L)\n+#define MDG_DBG_HBM_META (4887L)\n+#define MDG_DBG_HBM_VALID (4888L)\n+#define MDG_DBG_IGS_FC0 (4889L)\n+#define MDG_DBG_IGS_FC0_BLOCKED (4890L)\n+#define MDG_DBG_IGS_FC1 (4891L)\n+#define MDG_DBG_IGS_FC1_BLOCKED (4892L)\n+#define MDG_DBG_IGS_FC2 (4893L)\n+#define MDG_DBG_IGS_FC2_BLOCKED (4894L)\n+#define MDG_DBG_IGS_FC3 (4895L)\n+#define MDG_DBG_IGS_FC3_BLOCKED (4896L)\n+#define MDG_HBM_CTRL (4897L)\n+#define MDG_HBM_CTRL_ADR (4898L)\n+#define MDG_HBM_CTRL_CNT (4899L)\n+#define MDG_HBM_DATA (4900L)\n+#define MDG_HBM_DATA_MAIN (4901L)\n+#define MDG_HBM_DATA_MAP (4902L)\n+#define MDG_HBM_DATA_META (4903L)\n+#define MDG_HBS_CTRL (4904L)\n+#define MDG_HBS_CTRL_ADR (4905L)\n+#define MDG_HBS_CTRL_CNT (4906L)\n+#define MDG_HBS_DATA (4907L)\n+#define MDG_HBS_DATA_SIZE (4908L)\n+#define MDG_MAX_BYTES (4909L)\n+#define MDG_MAX_BYTES_MAX (4910L)\n+#define MDG_MAX_PACKETS (4911L)\n+#define MDG_MAX_PACKETS_MAX (4912L)\n+#define MDG_TIMEOUT (4913L)\n+#define MDG_TIMEOUT_T (4914L)\n+/* MSK */\n+#define MSK_RCP_CTRL (4980L)\n+#define MSK_RCP_CTRL_ADR (4981L)\n+#define MSK_RCP_CTRL_CNT (4982L)\n+#define MSK_RCP_DATA (4983L)\n+#define MSK_RCP_DATA_MASK_DYN0 (4984L)\n+#define MSK_RCP_DATA_MASK_DYN1 (4985L)\n+#define MSK_RCP_DATA_MASK_DYN2 (4986L)\n+#define MSK_RCP_DATA_MASK_DYN3 (4987L)\n+#define MSK_RCP_DATA_MASK_EN0 (4988L)\n+#define MSK_RCP_DATA_MASK_EN1 (4989L)\n+#define MSK_RCP_DATA_MASK_EN2 (4990L)\n+#define MSK_RCP_DATA_MASK_EN3 (4991L)\n+#define MSK_RCP_DATA_MASK_LEN0 (4992L)\n+#define MSK_RCP_DATA_MASK_LEN1 (4993L)\n+#define MSK_RCP_DATA_MASK_LEN2 (4994L)\n+#define MSK_RCP_DATA_MASK_LEN3 (4995L)\n+#define MSK_RCP_DATA_MASK_OFS0 (4996L)\n+#define MSK_RCP_DATA_MASK_OFS1 (4997L)\n+#define MSK_RCP_DATA_MASK_OFS2 (4998L)\n+#define MSK_RCP_DATA_MASK_OFS3 (4999L)\n+/* PCIE3 */\n+#define PCIE3_BUILD_SEED (5228L)\n+#define PCIE3_BUILD_SEED_BUILD_SEED (5229L)\n+#define PCIE3_BUILD_TIME (5230L)\n+#define PCIE3_BUILD_TIME_TIME (5231L)\n+#define PCIE3_CONFIG (5232L)\n+#define PCIE3_CONFIG_EXT_TAG (5233L)\n+#define PCIE3_CONFIG_MAX_READ (5234L)\n+#define PCIE3_CONFIG_MAX_TLP (5235L)\n+#define PCIE3_CONTROL (5236L)\n+#define PCIE3_CONTROL_RD_ATTR (5237L)\n+#define PCIE3_CONTROL_WRAW (5238L)\n+#define PCIE3_CONTROL_WR_ATTR (5239L)\n+#define PCIE3_CORESPEED (5240L)\n+#define PCIE3_CORESPEED_CORESPEED (5241L)\n+#define PCIE3_CORESPEED_DDR3SPEED (5242L)\n+#define PCIE3_DRP_COMMON (5243L)\n+#define PCIE3_DRP_COMMON_DRP_ADDR (5244L)\n+#define PCIE3_DRP_COMMON_DRP_RDY (5245L)\n+#define PCIE3_DRP_COMMON_GTH_SEL (5246L)\n+#define PCIE3_DRP_COMMON_WR (5247L)\n+#define PCIE3_DRP_DATE (5248L)\n+#define PCIE3_DRP_DATE_DRP_DATA (5249L)\n+#define PCIE3_EP_TO_RP_ERR (5250L)\n+#define PCIE3_EP_TO_RP_ERR_ERR_COR (5251L)\n+#define PCIE3_EP_TO_RP_ERR_ERR_FATAL (5252L)\n+#define PCIE3_EP_TO_RP_ERR_ERR_NONFATAL (5253L)\n+#define PCIE3_INT_CLR (5254L)\n+#define PCIE3_INT_CLR_AVR (5255L)\n+#define PCIE3_INT_CLR_FHM (5256L)\n+#define PCIE3_INT_CLR_INT_0 (5257L)\n+#define PCIE3_INT_CLR_INT_1 (5258L)\n+#define PCIE3_INT_CLR_INT_10 (5259L)\n+#define PCIE3_INT_CLR_INT_11 (5260L)\n+#define PCIE3_INT_CLR_INT_12 (5261L)\n+#define PCIE3_INT_CLR_INT_13 (5262L)\n+#define PCIE3_INT_CLR_INT_14 (5263L)\n+#define PCIE3_INT_CLR_INT_15 (5264L)\n+#define PCIE3_INT_CLR_INT_16 (5265L)\n+#define PCIE3_INT_CLR_INT_17 (5266L)\n+#define PCIE3_INT_CLR_INT_18 (5267L)\n+#define PCIE3_INT_CLR_INT_19 (5268L)\n+#define PCIE3_INT_CLR_INT_2 (5269L)\n+#define PCIE3_INT_CLR_INT_20 (5270L)\n+#define PCIE3_INT_CLR_INT_21 (5271L)\n+#define PCIE3_INT_CLR_INT_22 (5272L)\n+#define PCIE3_INT_CLR_INT_23 (5273L)\n+#define PCIE3_INT_CLR_INT_24 (5274L)\n+#define PCIE3_INT_CLR_INT_25 (5275L)\n+#define PCIE3_INT_CLR_INT_26 (5276L)\n+#define PCIE3_INT_CLR_INT_27 (5277L)\n+#define PCIE3_INT_CLR_INT_28 (5278L)\n+#define PCIE3_INT_CLR_INT_29 (5279L)\n+#define PCIE3_INT_CLR_INT_3 (5280L)\n+#define PCIE3_INT_CLR_INT_30 (5281L)\n+#define PCIE3_INT_CLR_INT_31 (5282L)\n+#define PCIE3_INT_CLR_INT_4 (5283L)\n+#define PCIE3_INT_CLR_INT_5 (5284L)\n+#define PCIE3_INT_CLR_INT_6 (5285L)\n+#define PCIE3_INT_CLR_INT_7 (5286L)\n+#define PCIE3_INT_CLR_INT_8 (5287L)\n+#define PCIE3_INT_CLR_INT_9 (5288L)\n+#define PCIE3_INT_CLR_PORT (5289L)\n+#define PCIE3_INT_CLR_PPS (5290L)\n+#define PCIE3_INT_CLR_QSPI (5291L)\n+#define PCIE3_INT_CLR_SPIM (5292L)\n+#define PCIE3_INT_CLR_SPIS (5293L)\n+#define PCIE3_INT_CLR_STA (5294L)\n+#define PCIE3_INT_CLR_TIMER (5295L)\n+#define PCIE3_INT_FORC (5296L)\n+#define PCIE3_INT_FORC_AVR (5297L)\n+#define PCIE3_INT_FORC_FHM (5298L)\n+#define PCIE3_INT_FORC_INT_0 (5299L)\n+#define PCIE3_INT_FORC_INT_1 (5300L)\n+#define PCIE3_INT_FORC_INT_10 (5301L)\n+#define PCIE3_INT_FORC_INT_11 (5302L)\n+#define PCIE3_INT_FORC_INT_12 (5303L)\n+#define PCIE3_INT_FORC_INT_13 (5304L)\n+#define PCIE3_INT_FORC_INT_14 (5305L)\n+#define PCIE3_INT_FORC_INT_15 (5306L)\n+#define PCIE3_INT_FORC_INT_16 (5307L)\n+#define PCIE3_INT_FORC_INT_17 (5308L)\n+#define PCIE3_INT_FORC_INT_18 (5309L)\n+#define PCIE3_INT_FORC_INT_19 (5310L)\n+#define PCIE3_INT_FORC_INT_2 (5311L)\n+#define PCIE3_INT_FORC_INT_20 (5312L)\n+#define PCIE3_INT_FORC_INT_21 (5313L)\n+#define PCIE3_INT_FORC_INT_22 (5314L)\n+#define PCIE3_INT_FORC_INT_23 (5315L)\n+#define PCIE3_INT_FORC_INT_24 (5316L)\n+#define PCIE3_INT_FORC_INT_25 (5317L)\n+#define PCIE3_INT_FORC_INT_26 (5318L)\n+#define PCIE3_INT_FORC_INT_27 (5319L)\n+#define PCIE3_INT_FORC_INT_28 (5320L)\n+#define PCIE3_INT_FORC_INT_29 (5321L)\n+#define PCIE3_INT_FORC_INT_3 (5322L)\n+#define PCIE3_INT_FORC_INT_30 (5323L)\n+#define PCIE3_INT_FORC_INT_31 (5324L)\n+#define PCIE3_INT_FORC_INT_4 (5325L)\n+#define PCIE3_INT_FORC_INT_5 (5326L)\n+#define PCIE3_INT_FORC_INT_6 (5327L)\n+#define PCIE3_INT_FORC_INT_7 (5328L)\n+#define PCIE3_INT_FORC_INT_8 (5329L)\n+#define PCIE3_INT_FORC_INT_9 (5330L)\n+#define PCIE3_INT_FORC_PORT (5331L)\n+#define PCIE3_INT_FORC_PPS (5332L)\n+#define PCIE3_INT_FORC_QSPI (5333L)\n+#define PCIE3_INT_FORC_SPIM (5334L)\n+#define PCIE3_INT_FORC_SPIS (5335L)\n+#define PCIE3_INT_FORC_STA (5336L)\n+#define PCIE3_INT_FORC_TIMER (5337L)\n+#define PCIE3_INT_MASK (5338L)\n+#define PCIE3_INT_MASK_AVR (5339L)\n+#define PCIE3_INT_MASK_FHM (5340L)\n+#define PCIE3_INT_MASK_IIC0 (5341L)\n+#define PCIE3_INT_MASK_IIC1 (5342L)\n+#define PCIE3_INT_MASK_IIC2 (5343L)\n+#define PCIE3_INT_MASK_IIC3 (5344L)\n+#define PCIE3_INT_MASK_IIC4 (5345L)\n+#define PCIE3_INT_MASK_IIC5 (5346L)\n+#define PCIE3_INT_MASK_INT_0 (5347L)\n+#define PCIE3_INT_MASK_INT_1 (5348L)\n+#define PCIE3_INT_MASK_INT_10 (5349L)\n+#define PCIE3_INT_MASK_INT_11 (5350L)\n+#define PCIE3_INT_MASK_INT_12 (5351L)\n+#define PCIE3_INT_MASK_INT_13 (5352L)\n+#define PCIE3_INT_MASK_INT_14 (5353L)\n+#define PCIE3_INT_MASK_INT_15 (5354L)\n+#define PCIE3_INT_MASK_INT_16 (5355L)\n+#define PCIE3_INT_MASK_INT_17 (5356L)\n+#define PCIE3_INT_MASK_INT_18 (5357L)\n+#define PCIE3_INT_MASK_INT_19 (5358L)\n+#define PCIE3_INT_MASK_INT_2 (5359L)\n+#define PCIE3_INT_MASK_INT_20 (5360L)\n+#define PCIE3_INT_MASK_INT_21 (5361L)\n+#define PCIE3_INT_MASK_INT_22 (5362L)\n+#define PCIE3_INT_MASK_INT_23 (5363L)\n+#define PCIE3_INT_MASK_INT_24 (5364L)\n+#define PCIE3_INT_MASK_INT_25 (5365L)\n+#define PCIE3_INT_MASK_INT_26 (5366L)\n+#define PCIE3_INT_MASK_INT_27 (5367L)\n+#define PCIE3_INT_MASK_INT_28 (5368L)\n+#define PCIE3_INT_MASK_INT_29 (5369L)\n+#define PCIE3_INT_MASK_INT_3 (5370L)\n+#define PCIE3_INT_MASK_INT_30 (5371L)\n+#define PCIE3_INT_MASK_INT_31 (5372L)\n+#define PCIE3_INT_MASK_INT_4 (5373L)\n+#define PCIE3_INT_MASK_INT_5 (5374L)\n+#define PCIE3_INT_MASK_INT_6 (5375L)\n+#define PCIE3_INT_MASK_INT_7 (5376L)\n+#define PCIE3_INT_MASK_INT_8 (5377L)\n+#define PCIE3_INT_MASK_INT_9 (5378L)\n+#define PCIE3_INT_MASK_PORT (5379L)\n+#define PCIE3_INT_MASK_PPS (5380L)\n+#define PCIE3_INT_MASK_QSPI (5381L)\n+#define PCIE3_INT_MASK_SPIM (5382L)\n+#define PCIE3_INT_MASK_SPIS (5383L)\n+#define PCIE3_INT_MASK_STA (5384L)\n+#define PCIE3_INT_MASK_TIMER (5385L)\n+#define PCIE3_LAT_CTRL (5386L)\n+#define PCIE3_LAT_CTRL_CLEAR_RAM (5387L)\n+#define PCIE3_LAT_CTRL_ENABLE (5388L)\n+#define PCIE3_LAT_CTRL_PRESCAL (5389L)\n+#define PCIE3_LAT_CTRL_RAM_VLD (5390L)\n+#define PCIE3_LAT_CTRL_READ_RAM (5391L)\n+#define PCIE3_LAT_CTRL_STATUS (5392L)\n+#define PCIE3_LAT_MAX (5393L)\n+#define PCIE3_LAT_MAX_MAX (5394L)\n+#define PCIE3_LAT_RAMADR (5395L)\n+#define PCIE3_LAT_RAMADR_ADR (5396L)\n+#define PCIE3_LAT_RAMDATA (5397L)\n+#define PCIE3_LAT_RAMDATA_DATA (5398L)\n+#define PCIE3_LINK_STATUS (5399L)\n+#define PCIE3_LINK_STATUS_CLEAR (5400L)\n+#define PCIE3_LINK_STATUS_RETRAIN_CNT (5401L)\n+#define PCIE3_MARKADR_LSB (5402L)\n+#define PCIE3_MARKADR_LSB_ADR (5403L)\n+#define PCIE3_MARKADR_MSB (5404L)\n+#define PCIE3_MARKADR_MSB_ADR (5405L)\n+#define PCIE3_PB_INTERVAL (5406L)\n+#define PCIE3_PB_INTERVAL_INTERVAL (5407L)\n+#define PCIE3_PB_MAX_RD (5408L)\n+#define PCIE3_PB_MAX_RD_PB (5409L)\n+#define PCIE3_PB_MAX_WR (5410L)\n+#define PCIE3_PB_MAX_WR_PB (5411L)\n+#define PCIE3_PCIE_CTRL (5412L)\n+#define PCIE3_PCIE_CTRL_EXT_TAG_ENA (5413L)\n+#define PCIE3_PCI_ENDPOINT (5414L)\n+#define PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK (5415L)\n+#define PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK (5416L)\n+#define PCIE3_PCI_ENDPOINT_GET_MSG (5417L)\n+#define PCIE3_PCI_ENDPOINT_IF_ID (5418L)\n+#define PCIE3_PCI_ENDPOINT_SEND_MSG (5419L)\n+#define PCIE3_PCI_TEST0 (5420L)\n+#define PCIE3_PCI_TEST0_DATA (5421L)\n+#define PCIE3_PCI_TEST1 (5422L)\n+#define PCIE3_PCI_TEST1_DATA (5423L)\n+#define PCIE3_PCI_TEST2 (5424L)\n+#define PCIE3_PCI_TEST2_DATA (5425L)\n+#define PCIE3_PCI_TEST3 (5426L)\n+#define PCIE3_PCI_TEST3_DATA (5427L)\n+#define PCIE3_PROD_ID_EX (5428L)\n+#define PCIE3_PROD_ID_EX_LAYOUT (5429L)\n+#define PCIE3_PROD_ID_EX_LAYOUT_VERSION (5430L)\n+#define PCIE3_PROD_ID_EX_RESERVED (5431L)\n+#define PCIE3_PROD_ID_LSB (5432L)\n+#define PCIE3_PROD_ID_LSB_GROUP_ID (5433L)\n+#define PCIE3_PROD_ID_LSB_REV_ID (5434L)\n+#define PCIE3_PROD_ID_LSB_VER_ID (5435L)\n+#define PCIE3_PROD_ID_MSB (5436L)\n+#define PCIE3_PROD_ID_MSB_BUILD_NO (5437L)\n+#define PCIE3_PROD_ID_MSB_PATCH_NO (5438L)\n+#define PCIE3_PROD_ID_MSB_TYPE_ID (5439L)\n+#define PCIE3_RESET_CTRL (5440L)\n+#define PCIE3_RESET_CTRL_MASK (5441L)\n+#define PCIE3_RP_TO_EP_ERR (5442L)\n+#define PCIE3_RP_TO_EP_ERR_ERR_COR (5443L)\n+#define PCIE3_RP_TO_EP_ERR_ERR_FATAL (5444L)\n+#define PCIE3_RP_TO_EP_ERR_ERR_NONFATAL (5445L)\n+#define PCIE3_SAMPLE_TIME (5446L)\n+#define PCIE3_SAMPLE_TIME_SAMPLE_TIME (5447L)\n+#define PCIE3_STATUS (5448L)\n+#define PCIE3_STATUS_RD_ERR (5449L)\n+#define PCIE3_STATUS_TAGS_IN_USE (5450L)\n+#define PCIE3_STATUS_WR_ERR (5451L)\n+#define PCIE3_STATUS0 (5452L)\n+#define PCIE3_STATUS0_TAGS_IN_USE (5453L)\n+#define PCIE3_STATUS0_UR_ADDR (5454L)\n+#define PCIE3_STATUS0_UR_DWORD (5455L)\n+#define PCIE3_STATUS0_UR_FBE (5456L)\n+#define PCIE3_STATUS0_UR_FMT (5457L)\n+#define PCIE3_STATUS0_UR_LBE (5458L)\n+#define PCIE3_STATUS0_UR_REG (5459L)\n+#define PCIE3_STAT_CTRL (5460L)\n+#define PCIE3_STAT_CTRL_STAT_ENA (5461L)\n+#define PCIE3_STAT_CTRL_STAT_REQ (5462L)\n+#define PCIE3_STAT_REFCLK (5463L)\n+#define PCIE3_STAT_REFCLK_REFCLK250 (5464L)\n+#define PCIE3_STAT_RQ_RDY (5465L)\n+#define PCIE3_STAT_RQ_RDY_COUNTER (5466L)\n+#define PCIE3_STAT_RQ_VLD (5467L)\n+#define PCIE3_STAT_RQ_VLD_COUNTER (5468L)\n+#define PCIE3_STAT_RX (5469L)\n+#define PCIE3_STAT_RX_COUNTER (5470L)\n+#define PCIE3_STAT_TX (5471L)\n+#define PCIE3_STAT_TX_COUNTER (5472L)\n+#define PCIE3_TEST0 (5473L)\n+#define PCIE3_TEST0_DATA (5474L)\n+#define PCIE3_TEST1 (5475L)\n+#define PCIE3_TEST1_DATA (5476L)\n+#define PCIE3_TEST2_DATA (5477L)\n+#define PCIE3_TEST3_DATA (5478L)\n+#define PCIE3_UUID0 (5479L)\n+#define PCIE3_UUID0_UUID0 (5480L)\n+#define PCIE3_UUID1 (5481L)\n+#define PCIE3_UUID1_UUID1 (5482L)\n+#define PCIE3_UUID2 (5483L)\n+#define PCIE3_UUID2_UUID2 (5484L)\n+#define PCIE3_UUID3 (5485L)\n+#define PCIE3_UUID3_UUID3 (5486L)\n+/* PCI_RD_TG */\n+#define PCI_RD_TG_TG_CTRL (5487L)\n+#define PCI_RD_TG_TG_CTRL_TG_RD_RDY (5488L)\n+#define PCI_RD_TG_TG_RDADDR (5489L)\n+#define PCI_RD_TG_TG_RDADDR_RAM_ADDR (5490L)\n+#define PCI_RD_TG_TG_RDDATA0 (5491L)\n+#define PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW (5492L)\n+#define PCI_RD_TG_TG_RDDATA1 (5493L)\n+#define PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH (5494L)\n+#define PCI_RD_TG_TG_RDDATA2 (5495L)\n+#define PCI_RD_TG_TG_RDDATA2_REQ_HID (5496L)\n+#define PCI_RD_TG_TG_RDDATA2_REQ_SIZE (5497L)\n+#define PCI_RD_TG_TG_RDDATA2_WAIT (5498L)\n+#define PCI_RD_TG_TG_RDDATA2_WRAP (5499L)\n+#define PCI_RD_TG_TG_RD_RUN (5500L)\n+#define PCI_RD_TG_TG_RD_RUN_RD_ITERATION (5501L)\n+/* PCI_TA */\n+#define PCI_TA_CONTROL (5502L)\n+#define PCI_TA_CONTROL_ENABLE (5503L)\n+#define PCI_TA_LENGTH_ERROR (5504L)\n+#define PCI_TA_LENGTH_ERROR_AMOUNT (5505L)\n+#define PCI_TA_PACKET_BAD (5506L)\n+#define PCI_TA_PACKET_BAD_AMOUNT (5507L)\n+#define PCI_TA_PACKET_GOOD (5508L)\n+#define PCI_TA_PACKET_GOOD_AMOUNT (5509L)\n+#define PCI_TA_PAYLOAD_ERROR (5510L)\n+#define PCI_TA_PAYLOAD_ERROR_AMOUNT (5511L)\n+/* PCI_WR_TG */\n+#define PCI_WR_TG_TG_CTRL (5512L)\n+#define PCI_WR_TG_TG_CTRL_TG_WR_RDY (5513L)\n+#define PCI_WR_TG_TG_SEQ (5514L)\n+#define PCI_WR_TG_TG_SEQ_SEQUENCE (5515L)\n+#define PCI_WR_TG_TG_WRADDR (5516L)\n+#define PCI_WR_TG_TG_WRADDR_RAM_ADDR (5517L)\n+#define PCI_WR_TG_TG_WRDATA0 (5518L)\n+#define PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW (5519L)\n+#define PCI_WR_TG_TG_WRDATA1 (5520L)\n+#define PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH (5521L)\n+#define PCI_WR_TG_TG_WRDATA2 (5522L)\n+#define PCI_WR_TG_TG_WRDATA2_INC_MODE (5523L)\n+#define PCI_WR_TG_TG_WRDATA2_REQ_HID (5524L)\n+#define PCI_WR_TG_TG_WRDATA2_REQ_SIZE (5525L)\n+#define PCI_WR_TG_TG_WRDATA2_WAIT (5526L)\n+#define PCI_WR_TG_TG_WRDATA2_WRAP (5527L)\n+#define PCI_WR_TG_TG_WR_RUN (5528L)\n+#define PCI_WR_TG_TG_WR_RUN_WR_ITERATION (5529L)\n+/* PCM_NT100A01_01 */\n+#define PCM_NT100A01_01_CTRL (5530L)\n+#define PCM_NT100A01_01_CTRL_PTP_CLKSEL (5531L)\n+#define PCM_NT100A01_01_CTRL_REC_MMCM_RST (5532L)\n+#define PCM_NT100A01_01_CTRL_TS_CLKSEL (5533L)\n+#define PCM_NT100A01_01_CTRL_TS_MMCM_RST (5534L)\n+#define PCM_NT100A01_01_GPIO_I (5535L)\n+#define PCM_NT100A01_01_GPIO_I_SI5328_C2B (5536L)\n+#define PCM_NT100A01_01_GPIO_I_SI5328_CS_CA (5537L)\n+#define PCM_NT100A01_01_GPIO_I_SI5328_INT_C1B (5538L)\n+#define PCM_NT100A01_01_GPIO_I_SI5328_LOL (5539L)\n+#define PCM_NT100A01_01_GPIO_O (5540L)\n+#define PCM_NT100A01_01_GPIO_O_SI5328_CS_CA (5541L)\n+#define PCM_NT100A01_01_GPIO_O_SI5328_RST_B (5542L)\n+#define PCM_NT100A01_01_GPIO_T (5543L)\n+#define PCM_NT100A01_01_GPIO_T_SI5328_CS_CA (5544L)\n+#define PCM_NT100A01_01_LATCH (5545L)\n+#define PCM_NT100A01_01_LATCH_REC_MMCM_LOCKED (5546L)\n+#define PCM_NT100A01_01_LATCH_TCXO_MMCM_LOCKED (5547L)\n+#define PCM_NT100A01_01_LATCH_TS_MMCM_LOCKED (5548L)\n+#define PCM_NT100A01_01_STAT (5549L)\n+#define PCM_NT100A01_01_STAT_REC_MMCM_LOCKED (5550L)\n+#define PCM_NT100A01_01_STAT_TCXO_MMCM_LOCKED (5551L)\n+#define PCM_NT100A01_01_STAT_TS_MMCM_LOCKED (5552L)\n+/* PCM_NT50B01_01 */\n+#define PCM_NT50B01_01_CTRL (5553L)\n+#define PCM_NT50B01_01_CTRL_TS_CLKSEL (5554L)\n+#define PCM_NT50B01_01_CTRL_TS_MMCM_RST (5555L)\n+#define PCM_NT50B01_01_LATCH (5556L)\n+#define PCM_NT50B01_01_LATCH_TS_MMCM_LOCKED (5557L)\n+#define PCM_NT50B01_01_STAT (5558L)\n+#define PCM_NT50B01_01_STAT_TS_MMCM_LOCKED (5559L)\n+/* PCS */\n+#define PCS_BER_COUNT (5560L)\n+#define PCS_BER_COUNT_CNT (5561L)\n+#define PCS_BIP_COUNT (5562L)\n+#define PCS_BIP_COUNT_CNT (5563L)\n+#define PCS_BLOCK_LOCK (5564L)\n+#define PCS_BLOCK_LOCK_LOCK (5565L)\n+#define PCS_BLOCK_LOCK_LATCH (5566L)\n+#define PCS_BLOCK_LOCK_LATCH_LATCH_LOCK (5567L)\n+#define PCS_BLOCK_LOCK_ST (5568L)\n+#define PCS_BLOCK_LOCK_ST_LATCH_STATE (5569L)\n+#define PCS_DDR3_STATUS (5570L)\n+#define PCS_DDR3_STATUS_CALIB_DONE (5571L)\n+#define PCS_DRP_CONFIG (5572L)\n+#define PCS_DRP_CONFIG_DRP_ADR (5573L)\n+#define PCS_DRP_CONFIG_DRP_DI (5574L)\n+#define PCS_DRP_CONFIG_DRP_EN (5575L)\n+#define PCS_DRP_CONFIG_DRP_WREN (5576L)\n+#define PCS_DRP_DATA (5577L)\n+#define PCS_DRP_DATA_DRP_DO (5578L)\n+#define PCS_DRP_DATA_DRP_RDY (5579L)\n+#define PCS_FSM_DONE (5580L)\n+#define PCS_FSM_DONE_RX_RST_DONE (5581L)\n+#define PCS_FSM_DONE_TX_RST_DONE (5582L)\n+#define PCS_GTH_CONFIG (5583L)\n+#define PCS_GTH_CONFIG_EYE_SCAN_RST (5584L)\n+#define PCS_GTH_CONFIG_EYE_SCAN_TRIG (5585L)\n+#define PCS_GTH_CONFIG_GT_LOOP (5586L)\n+#define PCS_GTH_CONFIG_GT_LPM_EN (5587L)\n+#define PCS_GTH_CONFIG_GT_MRST (5588L)\n+#define PCS_GTH_CONFIG_GT_RX_RST (5589L)\n+#define PCS_GTH_CONFIG_GT_SOFT_RST (5590L)\n+#define PCS_GTH_CONFIG_GT_TX_RST (5591L)\n+#define PCS_GTH_CONFIG_RX_MONITOR_SEL (5592L)\n+#define PCS_GTH_CONFIG_RX_PCS_RST (5593L)\n+#define PCS_GTH_CONFIG_RX_USER_RDY (5594L)\n+#define PCS_GTH_CONFIG_TX_PCS_RST (5595L)\n+#define PCS_GTH_CONFIG_TX_USER_RDYU (5596L)\n+#define PCS_GTH_CONTROL (5597L)\n+#define PCS_GTH_CONTROL_CPLL_LOCK (5598L)\n+#define PCS_GTH_CONTROL_CPLL_REFCLK_LOST (5599L)\n+#define PCS_GTH_CONTROL_RX_BUF_RST (5600L)\n+#define PCS_GTH_TX_TUNING (5601L)\n+#define PCS_GTH_TX_TUNING_DIFF_CTRL (5602L)\n+#define PCS_GTH_TX_TUNING_POST_CURSOR (5603L)\n+#define PCS_GTH_TX_TUNING_PRE_CURSOR (5604L)\n+#define PCS_LANE_LOCK (5605L)\n+#define PCS_LANE_LOCK_LOCK (5606L)\n+#define PCS_LANE_LOCK_LATCH (5607L)\n+#define PCS_LANE_LOCK_LATCH_LATCH_LOCK (5608L)\n+#define PCS_LANE_LOCK_ST (5609L)\n+#define PCS_LANE_LOCK_ST_LATCH_STATE (5610L)\n+#define PCS_LANE_MAPPING (5611L)\n+#define PCS_LANE_MAPPING_LANE (5612L)\n+#define PCS_LANE_OFFSET (5613L)\n+#define PCS_LANE_OFFSET_DIFF (5614L)\n+#define PCS_PCS_CONFIG (5615L)\n+#define PCS_PCS_CONFIG_BER_RST (5616L)\n+#define PCS_PCS_CONFIG_BIP_RST (5617L)\n+#define PCS_PCS_CONFIG_LANE_ADDR (5618L)\n+#define PCS_PCS_CONFIG_LANE_BLOCK_CLR (5619L)\n+#define PCS_PCS_CONFIG_TIME_OFFSET_RX (5620L)\n+#define PCS_PCS_CONFIG_TXRX_LOOP (5621L)\n+#define PCS_PCS_STATUS (5622L)\n+#define PCS_PCS_STATUS_ALIGN (5623L)\n+#define PCS_PCS_STATUS_DELAY_ERR (5624L)\n+#define PCS_PCS_STATUS_FIFO_DELAY (5625L)\n+#define PCS_PCS_STATUS_HI_BER (5626L)\n+#define PCS_POLARITY (5627L)\n+#define PCS_POLARITY_RX_POL (5628L)\n+#define PCS_POLARITY_TX_POL (5629L)\n+/* PCS100 */\n+#define PCS100_BER_COUNT (5630L)\n+#define PCS100_BER_COUNT_CNT (5631L)\n+#define PCS100_BIP_COUNT (5632L)\n+#define PCS100_BIP_COUNT_CNT (5633L)\n+#define PCS100_BLOCK_LOCK (5634L)\n+#define PCS100_BLOCK_LOCK_LOCK (5635L)\n+#define PCS100_BLOCK_LOCK_LATCH (5636L)\n+#define PCS100_BLOCK_LOCK_LATCH_LATCH_LOCK (5637L)\n+#define PCS100_BLOCK_LOCK_ST (5638L)\n+#define PCS100_BLOCK_LOCK_ST_LATCH_STATE (5639L)\n+#define PCS100_DDR3_STATUS (5640L)\n+#define PCS100_DDR3_STATUS_CALIB_DONE (5641L)\n+#define PCS100_DRP_CONFIG (5642L)\n+#define PCS100_DRP_CONFIG_DRP_ADR (5643L)\n+#define PCS100_DRP_CONFIG_DRP_DI (5644L)\n+#define PCS100_DRP_CONFIG_DRP_EN (5645L)\n+#define PCS100_DRP_CONFIG_DRP_WREN (5646L)\n+#define PCS100_DRP_DATA (5647L)\n+#define PCS100_DRP_DATA_DRP_DO (5648L)\n+#define PCS100_DRP_DATA_DRP_RDY (5649L)\n+#define PCS100_FSM_DONE (5650L)\n+#define PCS100_FSM_DONE_RX_RST_DONE (5651L)\n+#define PCS100_FSM_DONE_TX_RST_DONE (5652L)\n+#define PCS100_GTH_CONFIG (5653L)\n+#define PCS100_GTH_CONFIG_EYE_SCAN_RST (5654L)\n+#define PCS100_GTH_CONFIG_EYE_SCAN_TRIG (5655L)\n+#define PCS100_GTH_CONFIG_GT_LOOP (5656L)\n+#define PCS100_GTH_CONFIG_GT_MRST (5657L)\n+#define PCS100_GTH_CONFIG_GT_RX_RST (5658L)\n+#define PCS100_GTH_CONFIG_GT_SOFT_RST (5659L)\n+#define PCS100_GTH_CONFIG_GT_TX_RST (5660L)\n+#define PCS100_GTH_CONFIG_RX_MONITOR_SEL (5661L)\n+#define PCS100_GTH_CONFIG_RX_PCS_RST (5662L)\n+#define PCS100_GTH_CONFIG_RX_USER_RDY (5663L)\n+#define PCS100_GTH_CONFIG_TX_PCS_RST (5664L)\n+#define PCS100_GTH_CONFIG_TX_USER_RDYU (5665L)\n+#define PCS100_GTH_CONTROL (5666L)\n+#define PCS100_GTH_CONTROL_CPLL_LOCK (5667L)\n+#define PCS100_GTH_CONTROL_CPLL_REFCLK_LOST (5668L)\n+#define PCS100_GTH_CONTROL_QPLL_LOCK (5669L)\n+#define PCS100_GTH_CONTROL_QPLL_REFCLK_LOST (5670L)\n+#define PCS100_GTH_CONTROL_RX_BUF_RST (5671L)\n+#define PCS100_GTH_TX_TUNING (5672L)\n+#define PCS100_GTH_TX_TUNING_DIFF_CTRL (5673L)\n+#define PCS100_GTH_TX_TUNING_POST_CURSOR (5674L)\n+#define PCS100_GTH_TX_TUNING_PRE_CURSOR (5675L)\n+#define PCS100_LANE_LOCK (5676L)\n+#define PCS100_LANE_LOCK_LOCK (5677L)\n+#define PCS100_LANE_LOCK_LATCH (5678L)\n+#define PCS100_LANE_LOCK_LATCH_LATCH_LOCK (5679L)\n+#define PCS100_LANE_LOCK_ST (5680L)\n+#define PCS100_LANE_LOCK_ST_LATCH_STATE (5681L)\n+#define PCS100_LANE_MAPPING (5682L)\n+#define PCS100_LANE_MAPPING_LANE (5683L)\n+#define PCS100_LANE_OFFSET (5684L)\n+#define PCS100_LANE_OFFSET_DIFF (5685L)\n+#define PCS100_PCS_CONFIG (5686L)\n+#define PCS100_PCS_CONFIG_BER_RST (5687L)\n+#define PCS100_PCS_CONFIG_BIP_RST (5688L)\n+#define PCS100_PCS_CONFIG_LANE_ADDR (5689L)\n+#define PCS100_PCS_CONFIG_LANE_BLOCK_CLR (5690L)\n+#define PCS100_PCS_CONFIG_TIME_OFFSET_RX (5691L)\n+#define PCS100_PCS_CONFIG_TXRX_LOOP (5692L)\n+#define PCS100_PCS_STATUS (5693L)\n+#define PCS100_PCS_STATUS_ALIGN (5694L)\n+#define PCS100_PCS_STATUS_DELAY_ERR (5695L)\n+#define PCS100_PCS_STATUS_FIFO_DELAY (5696L)\n+#define PCS100_PCS_STATUS_HI_BER (5697L)\n+/* PDB */\n+#define PDB_CONFIG (5698L)\n+#define PDB_CONFIG_PORT_OFS (5699L)\n+#define PDB_CONFIG_TS_FORMAT (5700L)\n+#define PDB_RCP_CTRL (5701L)\n+#define PDB_RCP_CTRL_ADR (5702L)\n+#define PDB_RCP_CTRL_CNT (5703L)\n+#define PDB_RCP_DATA (5704L)\n+#define PDB_RCP_DATA_ALIGN (5705L)\n+#define PDB_RCP_DATA_CRC_OVERWRITE (5706L)\n+#define PDB_RCP_DATA_DESCRIPTOR (5707L)\n+#define PDB_RCP_DATA_DESC_LEN (5708L)\n+#define PDB_RCP_DATA_DUPLICATE_BIT (5709L)\n+#define PDB_RCP_DATA_DUPLICATE_EN (5710L)\n+#define PDB_RCP_DATA_IP_PROT_TNL (5711L)\n+#define PDB_RCP_DATA_OFS0_DYN (5712L)\n+#define PDB_RCP_DATA_OFS0_REL (5713L)\n+#define PDB_RCP_DATA_OFS1_DYN (5714L)\n+#define PDB_RCP_DATA_OFS1_REL (5715L)\n+#define PDB_RCP_DATA_OFS2_DYN (5716L)\n+#define PDB_RCP_DATA_OFS2_REL (5717L)\n+#define PDB_RCP_DATA_PCAP_KEEP_FCS (5718L)\n+#define PDB_RCP_DATA_PPC_HSH (5719L)\n+#define PDB_RCP_DATA_TX_IGNORE (5720L)\n+#define PDB_RCP_DATA_TX_NOW (5721L)\n+#define PDB_RCP_DATA_TX_PORT (5722L)\n+/* PDI */\n+#define PDI_CR (5723L)\n+#define PDI_CR_EN (5724L)\n+#define PDI_CR_PARITY (5725L)\n+#define PDI_CR_RST (5726L)\n+#define PDI_CR_RXRST (5727L)\n+#define PDI_CR_STOP (5728L)\n+#define PDI_CR_TXRST (5729L)\n+#define PDI_DRR (5730L)\n+#define PDI_DRR_DRR (5731L)\n+#define PDI_DTR (5732L)\n+#define PDI_DTR_DTR (5733L)\n+#define PDI_PRE (5734L)\n+#define PDI_PRE_PRE (5735L)\n+#define PDI_SR (5736L)\n+#define PDI_SR_DISABLE_BUSY (5737L)\n+#define PDI_SR_DONE (5738L)\n+#define PDI_SR_ENABLE_BUSY (5739L)\n+#define PDI_SR_FRAME_ERR (5740L)\n+#define PDI_SR_OVERRUN_ERR (5741L)\n+#define PDI_SR_PARITY_ERR (5742L)\n+#define PDI_SR_RXLVL (5743L)\n+#define PDI_SR_RX_BUSY (5744L)\n+#define PDI_SR_TXLVL (5745L)\n+#define PDI_SR_TX_BUSY (5746L)\n+#define PDI_SRR (5747L)\n+#define PDI_SRR_RST (5748L)\n+/* PHY10G */\n+#define PHY10G_CORE_CONF (5749L)\n+#define PHY10G_CORE_CONF_CLEAR_PCS_LINK_FAULTS (5750L)\n+#define PHY10G_CORE_CONF_CLEAR_PCS_STATUS2 (5751L)\n+#define PHY10G_CORE_CONF_CLEAR_PMA_PMD_LINK_FAULTS (5752L)\n+#define PHY10G_CORE_CONF_CLEAR_TEST_PATT_ERR_COUNT (5753L)\n+#define PHY10G_CORE_CONF_DATA_PATT_SEL (5754L)\n+#define PHY10G_CORE_CONF_GLOBAL_TX_DISABLE (5755L)\n+#define PHY10G_CORE_CONF_NT_FORCE_LINK_DOWN (5756L)\n+#define PHY10G_CORE_CONF_NT_LINKUP_LATENCY (5757L)\n+#define PHY10G_CORE_CONF_PCS_LOOPBACK (5758L)\n+#define PHY10G_CORE_CONF_PCS_RESET (5759L)\n+#define PHY10G_CORE_CONF_PMA_LOOPBACK (5760L)\n+#define PHY10G_CORE_CONF_PMA_RESET (5761L)\n+#define PHY10G_CORE_CONF_PMD_TX_DISABLE (5762L)\n+#define PHY10G_CORE_CONF_PRBS31_RX_EN (5763L)\n+#define PHY10G_CORE_CONF_PRBS31_TX_EN (5764L)\n+#define PHY10G_CORE_CONF_RX_TEST_PATT_EN (5765L)\n+#define PHY10G_CORE_CONF_SET_PCS_LINK_STATUS (5766L)\n+#define PHY10G_CORE_CONF_SET_PMA_LINK_STATUS (5767L)\n+#define PHY10G_CORE_CONF_TEST_PATT_SEL (5768L)\n+#define PHY10G_CORE_CONF_TX_TEST_PATT_EN (5769L)\n+#define PHY10G_CORE_STAT (5770L)\n+#define PHY10G_CORE_STAT_NT_LINK_STATE (5771L)\n+#define PHY10G_CORE_STAT_PCS_BER_COUNT (5772L)\n+#define PHY10G_CORE_STAT_PCS_BLOCK_LOCK (5773L)\n+#define PHY10G_CORE_STAT_PCS_ERR_BLOCK_COUNT (5774L)\n+#define PHY10G_CORE_STAT_PCS_HIBER (5775L)\n+#define PHY10G_CORE_STAT_PCS_RESET (5776L)\n+#define PHY10G_CORE_STAT_PCS_RX_FAULT (5777L)\n+#define PHY10G_CORE_STAT_PCS_RX_HIBER_LH (5778L)\n+#define PHY10G_CORE_STAT_PCS_RX_LINK_STATUS (5779L)\n+#define PHY10G_CORE_STAT_PCS_RX_LOCKED (5780L)\n+#define PHY10G_CORE_STAT_PCS_RX_LOCKED_LL (5781L)\n+#define PHY10G_CORE_STAT_PCS_TEST_PATT_ERR_COUNT (5782L)\n+#define PHY10G_CORE_STAT_PCS_TX_FAULT (5783L)\n+#define PHY10G_CORE_STAT_PMA_PMD_LINK_STAT (5784L)\n+#define PHY10G_CORE_STAT_PMA_PMD_RX_FAULT (5785L)\n+#define PHY10G_CORE_STAT_PMA_PMD_TX_FAULT (5786L)\n+#define PHY10G_CORE_STAT_PMA_RESET (5787L)\n+#define PHY10G_CORE_STAT_RX_SIG_DET (5788L)\n+#define PHY10G_CORE_STAT_TENG_PCS_RX_LINK_STATUS (5789L)\n+#define PHY10G_CTRL (5790L)\n+#define PHY10G_CTRL_FORCE_LINK_DOWN (5791L)\n+#define PHY10G_CTRL_HOST_LOOPBACK (5792L)\n+#define PHY10G_CTRL_LINE_LOOPBACK (5793L)\n+#define PHY10G_CTRL_LINKUP_LATENCY (5794L)\n+#define PHY10G_CTRL_SOFT_RESET (5795L)\n+#define PHY10G_GPIO (5796L)\n+#define PHY10G_GPIO_ABS (5797L)\n+#define PHY10G_GPIO_LED_MODE (5798L)\n+#define PHY10G_GPIO_LED_MODE_NIM (5799L)\n+#define PHY10G_GPIO_LED_MODE_PHY (5800L)\n+#define PHY10G_GPIO_PWR_EN (5801L)\n+#define PHY10G_GPIO_RX_LOS (5802L)\n+#define PHY10G_GPIO_TX_FAULT (5803L)\n+#define PHY10G_GT_CTRL (5804L)\n+#define PHY10G_GT_CTRL_EYESCANRESET (5805L)\n+#define PHY10G_GT_CTRL_EYESCANTRIGGER (5806L)\n+#define PHY10G_GT_CTRL_RXCDRHOLD (5807L)\n+#define PHY10G_GT_CTRL_RXDFELPMRESET (5808L)\n+#define PHY10G_GT_CTRL_RXLPMEN (5809L)\n+#define PHY10G_GT_CTRL_RXPMARESET (5810L)\n+#define PHY10G_GT_CTRL_RXPRBSENABLE (5811L)\n+#define PHY10G_GT_CTRL_RXRATE (5812L)\n+#define PHY10G_GT_CTRL_TXDIFFCTRL (5813L)\n+#define PHY10G_GT_CTRL_TXPCSRESET (5814L)\n+#define PHY10G_GT_CTRL_TXPMARESET (5815L)\n+#define PHY10G_GT_CTRL_TXPOSTCURSOR (5816L)\n+#define PHY10G_GT_CTRL_TXPRBSENABLE (5817L)\n+#define PHY10G_GT_CTRL_TXPRBSFORCEERR (5818L)\n+#define PHY10G_GT_CTRL_TXPRECURSOR (5819L)\n+#define PHY10G_GT_STAT (5820L)\n+#define PHY10G_GT_STAT_DMONITOROUT (5821L)\n+#define PHY10G_GT_STAT_EYESCANDATAERROR (5822L)\n+#define PHY10G_GT_STAT_RXBUFSTATUS (5823L)\n+#define PHY10G_GT_STAT_RXPMARESETDONE (5824L)\n+#define PHY10G_GT_STAT_RXPRBSERR (5825L)\n+#define PHY10G_GT_STAT_RXPRBSLOCKED (5826L)\n+#define PHY10G_GT_STAT_RXRESETDONE (5827L)\n+#define PHY10G_GT_STAT_TXBUFSTATUS (5828L)\n+#define PHY10G_GT_STAT_TXRESETDONE (5829L)\n+#define PHY10G_GT_STAT2 (5830L)\n+#define PHY10G_GT_STAT2_DMONITOR (5831L)\n+#define PHY10G_GT_STAT2_RXPRBSCNT (5832L)\n+#define PHY10G_INT (5833L)\n+#define PHY10G_INT_EN (5834L)\n+#define PHY10G_INT_MAX_PACE (5835L)\n+#define PHY10G_LINK_SUMMARY (5836L)\n+#define PHY10G_LINK_SUMMARY_ABS (5837L)\n+#define PHY10G_LINK_SUMMARY_CORE_STATUS (5838L)\n+#define PHY10G_LINK_SUMMARY_LINK_DOWN_CNT (5839L)\n+#define PHY10G_LINK_SUMMARY_NT_LINK_STATE (5840L)\n+#define PHY10G_LINK_SUMMARY_RES (5841L)\n+#define PHY10G_TS_COMP (5842L)\n+#define PHY10G_TS_COMP_RX (5843L)\n+/* PHY3S10G */\n+#define PHY3S10G_ANEG_ADV_3S (5844L)\n+#define PHY3S10G_ANEG_ADV_3S_DUPLEX (5845L)\n+#define PHY3S10G_ANEG_ADV_3S_PAUSE (5846L)\n+#define PHY3S10G_ANEG_ADV_3S_REMOTE_FAULT (5847L)\n+#define PHY3S10G_CORE_CONF_10G (5848L)\n+#define PHY3S10G_CORE_CONF_10G_CLEAR_PCS_LINK_FAULTS (5849L)\n+#define PHY3S10G_CORE_CONF_10G_CLEAR_PCS_STATUS2 (5850L)\n+#define PHY3S10G_CORE_CONF_10G_CLEAR_PMA_PMD_LINK_FAULTS (5851L)\n+#define PHY3S10G_CORE_CONF_10G_PCS_LOOPBACK (5852L)\n+#define PHY3S10G_CORE_CONF_10G_PCS_RESET (5853L)\n+#define PHY3S10G_CORE_CONF_10G_PMA_LOOPBACK (5854L)\n+#define PHY3S10G_CORE_CONF_10G_PMA_RESET (5855L)\n+#define PHY3S10G_CORE_CONF_10G_SET_PCS_LINK_STATUS (5856L)\n+#define PHY3S10G_CORE_CONF_10G_SET_PMA_LINK_STATUS (5857L)\n+#define PHY3S10G_CORE_CONF_3S (5858L)\n+#define PHY3S10G_CORE_CONF_3S_ANEG_BYPASS_EN (5859L)\n+#define PHY3S10G_CORE_CONF_3S_ANEG_EN (5860L)\n+#define PHY3S10G_CORE_CONF_3S_ANEG_RESTART (5861L)\n+#define PHY3S10G_CORE_CONF_3S_BASEX_OR_SGMII (5862L)\n+#define PHY3S10G_CORE_CONF_3S_LINK_TIMER_BASEX (5863L)\n+#define PHY3S10G_CORE_CONF_3S_LOOPBACK_CTRL (5864L)\n+#define PHY3S10G_CORE_CONF_3S_POWER_DOWN (5865L)\n+#define PHY3S10G_CORE_CONF_3S_SPEED (5866L)\n+#define PHY3S10G_CORE_CONF_3S_UNIDIRECT_EN (5867L)\n+#define PHY3S10G_CORE_STAT_10G (5868L)\n+#define PHY3S10G_CORE_STAT_10G_NT_LINK_STATE (5869L)\n+#define PHY3S10G_CORE_STAT_10G_PCS_BER_COUNT (5870L)\n+#define PHY3S10G_CORE_STAT_10G_PCS_BLOCK_LOCK (5871L)\n+#define PHY3S10G_CORE_STAT_10G_PCS_ERR_BLOCK_COUNT (5872L)\n+#define PHY3S10G_CORE_STAT_10G_PCS_HIBER (5873L)\n+#define PHY3S10G_CORE_STAT_10G_PCS_RX_HIBER_LH (5874L)\n+#define PHY3S10G_CORE_STAT_10G_PCS_RX_LINK_STATUS (5875L)\n+#define PHY3S10G_CORE_STAT_10G_PCS_RX_LOCKED (5876L)\n+#define PHY3S10G_CORE_STAT_10G_PCS_RX_LOCKED_LL (5877L)\n+#define PHY3S10G_CORE_STAT_10G_PMA_PMD_LINK_STAT (5878L)\n+#define PHY3S10G_CORE_STAT_10G_RX_SIG_DET (5879L)\n+#define PHY3S10G_CORE_STAT_10G_TENG_PCS_RX_LINK_STATUS (5880L)\n+#define PHY3S10G_CORE_STAT_3S (5881L)\n+#define PHY3S10G_CORE_STAT_3S_ANEG_COMPLETE (5882L)\n+#define PHY3S10G_CORE_STAT_3S_DUPLEX_MODE (5883L)\n+#define PHY3S10G_CORE_STAT_3S_LINK_STATUS (5884L)\n+#define PHY3S10G_CORE_STAT_3S_LINK_SYNC (5885L)\n+#define PHY3S10G_CORE_STAT_3S_NT_LINK_STATE (5886L)\n+#define PHY3S10G_CORE_STAT_3S_PAUSE (5887L)\n+#define PHY3S10G_CORE_STAT_3S_PHY_LINK_STAT (5888L)\n+#define PHY3S10G_CORE_STAT_3S_REM_FAULT_ENC (5889L)\n+#define PHY3S10G_CORE_STAT_3S_RESERVED (5890L)\n+#define PHY3S10G_CORE_STAT_3S_RUDI_C (5891L)\n+#define PHY3S10G_CORE_STAT_3S_RUDI_I (5892L)\n+#define PHY3S10G_CORE_STAT_3S_RUDI_INVALID (5893L)\n+#define PHY3S10G_CORE_STAT_3S_RXDISPERR (5894L)\n+#define PHY3S10G_CORE_STAT_3S_RXNOTINTABLE (5895L)\n+#define PHY3S10G_CORE_STAT_3S_SPEED (5896L)\n+#define PHY3S10G_CTRL (5897L)\n+#define PHY3S10G_CTRL_FORCE_LINK_DOWN (5898L)\n+#define PHY3S10G_CTRL_HOST_LOOPBACK_10G (5899L)\n+#define PHY3S10G_CTRL_HOST_LOOPBACK_3S (5900L)\n+#define PHY3S10G_CTRL_LINE_LOOPBACK_10G (5901L)\n+#define PHY3S10G_CTRL_LINE_LOOPBACK_3S (5902L)\n+#define PHY3S10G_CTRL_LINKUP_LATENCY (5903L)\n+#define PHY3S10G_CTRL_PHY_CHANGE_FSM_DONE (5904L)\n+#define PHY3S10G_CTRL_PHY_SEL (5905L)\n+#define PHY3S10G_CTRL_SOFT_RESET (5906L)\n+#define PHY3S10G_GPIO (5907L)\n+#define PHY3S10G_GPIO_ABS (5908L)\n+#define PHY3S10G_GPIO_LED_MODE (5909L)\n+#define PHY3S10G_GPIO_RATE_SEL (5910L)\n+#define PHY3S10G_GPIO_RX_LOS (5911L)\n+#define PHY3S10G_GPIO_TX_DISABLE (5912L)\n+#define PHY3S10G_GPIO_TX_FAULT (5913L)\n+#define PHY3S10G_GT_CR (5914L)\n+#define PHY3S10G_GT_CR_EYESCANRESET (5915L)\n+#define PHY3S10G_GT_CR_EYESCANTRIGGER (5916L)\n+#define PHY3S10G_GT_CR_LOOPBACK (5917L)\n+#define PHY3S10G_GT_CR_RXCDRHOLD (5918L)\n+#define PHY3S10G_GT_CR_RXDFELPMRESET (5919L)\n+#define PHY3S10G_GT_CR_RXLPMEN (5920L)\n+#define PHY3S10G_GT_CR_RXPMARESET (5921L)\n+#define PHY3S10G_GT_CR_RXPRBSCNTRESET (5922L)\n+#define PHY3S10G_GT_CR_RXPRBSSEL (5923L)\n+#define PHY3S10G_GT_CR_TXDIFFCTRL (5924L)\n+#define PHY3S10G_GT_CR_TXPMARESET (5925L)\n+#define PHY3S10G_GT_CR_TXPOSTCURSOR (5926L)\n+#define PHY3S10G_GT_CR_TXPRBSFORCEERR (5927L)\n+#define PHY3S10G_GT_CR_TXPRBSSEL (5928L)\n+#define PHY3S10G_GT_CR_TXPRECURSOR (5929L)\n+#define PHY3S10G_GT_SR (5930L)\n+#define PHY3S10G_GT_SR_EYESCANDATAERROR (5931L)\n+#define PHY3S10G_GT_SR_RXBUFSTATUS (5932L)\n+#define PHY3S10G_GT_SR_RXPMARESETDONE (5933L)\n+#define PHY3S10G_GT_SR_RXPRBSERR (5934L)\n+#define PHY3S10G_GT_SR_RXRESETDONE (5935L)\n+#define PHY3S10G_GT_SR_TXBUFSTATUS (5936L)\n+#define PHY3S10G_GT_SR_TXRESETDONE (5937L)\n+#define PHY3S10G_INT (5938L)\n+#define PHY3S10G_INT_EN (5939L)\n+#define PHY3S10G_INT_MAX_PACE (5940L)\n+#define PHY3S10G_LINK_SUMMARY (5941L)\n+#define PHY3S10G_LINK_SUMMARY_ABS (5942L)\n+#define PHY3S10G_LINK_SUMMARY_ANEG_BYPASS (5943L)\n+#define PHY3S10G_LINK_SUMMARY_LINK_DOWN_CNT (5944L)\n+#define PHY3S10G_LINK_SUMMARY_NT_LINK_STATE (5945L)\n+#define PHY3S10G_TS_COMP (5946L)\n+#define PHY3S10G_TS_COMP_RX (5947L)\n+#define PHY3S10G_TS_COMP_RX_10G (5948L)\n+#define PHY3S10G_TS_COMP_RX_3S (5949L)\n+/* PM */\n+#define PM_CTRL (5950L)\n+#define PM_CTRL_SW_CLEAN_DONE (5951L)\n+#define PM_DEBUG_RP (5952L)\n+#define PM_DEBUG_RP_RP (5953L)\n+#define PM_DEBUG_RP_SETUP (5954L)\n+#define PM_DEBUG_RP_SETUP_HB (5955L)\n+#define PM_DEBUG_RX_BLOCK (5956L)\n+#define PM_DEBUG_RX_BLOCK_MASK (5957L)\n+#define PM_HB_SIZE_RX_MEM_CTRL (5958L)\n+#define PM_HB_SIZE_RX_MEM_CTRL_A (5959L)\n+#define PM_HB_SIZE_RX_MEM_CTRL_CNT (5960L)\n+#define PM_HB_SIZE_RX_MEM_DATA (5961L)\n+#define PM_HB_SIZE_RX_MEM_DATA_SIZE (5962L)\n+#define PM_HB_SIZE_RX_THRESHOLD (5963L)\n+#define PM_HB_SIZE_RX_THRESHOLD_D (5964L)\n+#define PM_HB_SIZE_TX_THRESHOLD (5965L)\n+#define PM_HB_SIZE_TX_THRESHOLD_D (5966L)\n+#define PM_PBI_MEM_CTRL (5967L)\n+#define PM_PBI_MEM_CTRL_A (5968L)\n+#define PM_PBI_MEM_CTRL_CNT (5969L)\n+#define PM_PBI_MEM_DATA (5970L)\n+#define PM_PBI_MEM_DATA_PHYADDR (5971L)\n+#define PM_PBI_MEM_DATA_SIZE (5972L)\n+#define PM_POINTER_BANKS (5973L)\n+#define PM_POINTER_BANKS_D (5974L)\n+#define PM_RXTX_FAST_MEM_CTRL (5975L)\n+#define PM_RXTX_FAST_MEM_CTRL_A (5976L)\n+#define PM_RXTX_FAST_MEM_CTRL_CNT (5977L)\n+#define PM_RXTX_FAST_MEM_DATA (5978L)\n+#define PM_RXTX_FAST_MEM_DATA_BANK (5979L)\n+#define PM_RXTX_FAST_MEM_DATA_ENTRY (5980L)\n+#define PM_RXTX_FAST_MEM_DATA_HOST_BUFFER (5981L)\n+#define PM_RXTX_FAST_MEM_DATA_RX_TX (5982L)\n+#define PM_RXTX_FAST_MEM_DATA_VLD (5983L)\n+#define PM_RXTX_SLOW_MEM_CTRL (5984L)\n+#define PM_RXTX_SLOW_MEM_CTRL_A (5985L)\n+#define PM_RXTX_SLOW_MEM_CTRL_CNT (5986L)\n+#define PM_RXTX_SLOW_MEM_DATA (5987L)\n+#define PM_RXTX_SLOW_MEM_DATA_BANK (5988L)\n+#define PM_RXTX_SLOW_MEM_DATA_ENTRY (5989L)\n+#define PM_RXTX_SLOW_MEM_DATA_HOST_BUFFER (5990L)\n+#define PM_RXTX_SLOW_MEM_DATA_RX_TX (5991L)\n+#define PM_RXTX_SLOW_MEM_DATA_VLD (5992L)\n+#define PM_RXWP_MEM_CTRL (5993L)\n+#define PM_RXWP_MEM_CTRL_A (5994L)\n+#define PM_RXWP_MEM_CTRL_CNT (5995L)\n+#define PM_RXWP_MEM_DATA (5996L)\n+#define PM_RXWP_MEM_DATA_BANK (5997L)\n+#define PM_RXWP_MEM_DATA_ENTRY (5998L)\n+#define PM_RXWP_MEM_DATA_HOST_BUFFER (5999L)\n+#define PM_RXWP_MEM_DATA_VLD (6000L)\n+#define PM_RX_BLOCKED_STATUS (6001L)\n+#define PM_RX_BLOCKED_STATUS_D (6002L)\n+#define PM_RX_BLOCKED_STATUS_HI (6003L)\n+#define PM_RX_BLOCKED_STATUS_HI_D (6004L)\n+#define PM_RX_OVERFLOW_STATUS (6005L)\n+#define PM_RX_OVERFLOW_STATUS_D (6006L)\n+#define PM_RX_READER (6007L)\n+#define PM_RX_READER_MASK (6008L)\n+#define PM_RX_TX_FAST_POINTER_BLOCK_INTERVAL (6009L)\n+#define PM_RX_TX_FAST_POINTER_BLOCK_INTERVAL_D (6010L)\n+#define PM_RX_TX_SLOW_POINTER_BLOCK_INTERVAL (6011L)\n+#define PM_RX_TX_SLOW_POINTER_BLOCK_INTERVAL_D (6012L)\n+#define PM_RX_WRITE_POINTER_BLOCK_INTERVAL (6013L)\n+#define PM_RX_WRITE_POINTER_BLOCK_INTERVAL_D (6014L)\n+#define PM_TXRP_MEM_CTRL (6015L)\n+#define PM_TXRP_MEM_CTRL_A (6016L)\n+#define PM_TXRP_MEM_CTRL_CNT (6017L)\n+#define PM_TXRP_MEM_DATA (6018L)\n+#define PM_TXRP_MEM_DATA_BANK (6019L)\n+#define PM_TXRP_MEM_DATA_ENTRY (6020L)\n+#define PM_TXRP_MEM_DATA_HOST_BUFFER (6021L)\n+#define PM_TXRP_MEM_DATA_VLD (6022L)\n+#define PM_TX_READ_POINTER_BLOCK_INTERVAL (6023L)\n+#define PM_TX_READ_POINTER_BLOCK_INTERVAL_D (6024L)\n+/* PRM_NT100A01_01 */\n+#define PRM_NT100A01_01_POWER (6025L)\n+#define PRM_NT100A01_01_POWER_PU_NSEB (6026L)\n+#define PRM_NT100A01_01_POWER_PU_PHY (6027L)\n+#define PRM_NT100A01_01_RST (6028L)\n+#define PRM_NT100A01_01_RST_PERIPH (6029L)\n+#define PRM_NT100A01_01_RST_PLATFORM (6030L)\n+/* PRM_NT50B01_01 */\n+#define PRM_NT50B01_01_POWER (6031L)\n+#define PRM_NT50B01_01_POWER_PU_NSEB (6032L)\n+#define PRM_NT50B01_01_POWER_PU_PHY (6033L)\n+#define PRM_NT50B01_01_RST (6034L)\n+#define PRM_NT50B01_01_RST_PERIPH (6035L)\n+#define PRM_NT50B01_01_RST_PLATFORM (6036L)\n+/* PTP1588 */\n+#define PTP1588_CONF (6037L)\n+#define PTP1588_CONF_MII_RX_TX_LOOP (6038L)\n+#define PTP1588_CONF_MII_TX_RX_LOOP (6039L)\n+#define PTP1588_CONF_PHY_RST (6040L)\n+#define PTP1588_CONF_PHY_RST1 (6041L)\n+#define PTP1588_CONF_PHY_RST2 (6042L)\n+#define PTP1588_CONF_PTP_CTRL_LOCAL (6043L)\n+#define PTP1588_CONF_PTP_RX_CTRL (6044L)\n+#define PTP1588_CONF_PTP_TX_CTRL (6045L)\n+#define PTP1588_CONF_PTP_TX_CTRL_OS (6046L)\n+#define PTP1588_CONF_RX_IGNORE_DEST_ADDR (6047L)\n+#define PTP1588_CONF_TG_CMD (6048L)\n+#define PTP1588_CONF_TG_MODE (6049L)\n+#define PTP1588_CONF_TSM_MI_ACK (6050L)\n+#define PTP1588_CONF_TSM_MI_BUSY (6051L)\n+#define PTP1588_CONF_TSM_MI_ENA (6052L)\n+#define PTP1588_CONF_TSM_MI_REQ (6053L)\n+#define PTP1588_CONF_TX_IFG (6054L)\n+#define PTP1588_CONF_TX_IGNORE_DEST_ADDR (6055L)\n+#define PTP1588_CTRL (6056L)\n+#define PTP1588_CTRL_CLK_ENABLE (6057L)\n+#define PTP1588_CTRL_MII_RX_TX_LOOP (6058L)\n+#define PTP1588_CTRL_MII_TX_RX_LOOP (6059L)\n+#define PTP1588_CTRL_PRESENT (6060L)\n+#define PTP1588_CTRL_RESET_N (6061L)\n+#define PTP1588_CTRL_TS_MI_ACK (6062L)\n+#define PTP1588_CTRL_TS_MI_BUSY (6063L)\n+#define PTP1588_CTRL_TS_MI_ENA (6064L)\n+#define PTP1588_CTRL_TS_MI_REQ (6065L)\n+#define PTP1588_CTRL_TX_IFG (6066L)\n+#define PTP1588_GP_DATA (6067L)\n+#define PTP1588_GP_DATA_GPIO (6068L)\n+#define PTP1588_GP_DATA_PWRDOWN_INTN (6069L)\n+#define PTP1588_GP_DATA_TIMESYNC_CON (6070L)\n+#define PTP1588_GP_DATA_LH (6071L)\n+#define PTP1588_GP_DATA_LH_GPIO (6072L)\n+#define PTP1588_GP_DATA_LH_PWRDOWN_INTN (6073L)\n+#define PTP1588_GP_DATA_LH_TIMESYNC_CON (6074L)\n+#define PTP1588_GP_DATA_LL (6075L)\n+#define PTP1588_GP_DATA_LL_GPIO (6076L)\n+#define PTP1588_GP_DATA_LL_PWRDOWN_INTN (6077L)\n+#define PTP1588_GP_DATA_LL_TIMESYNC_CON (6078L)\n+#define PTP1588_GP_OE (6079L)\n+#define PTP1588_GP_OE_GPIO (6080L)\n+#define PTP1588_GP_OE_PWRDOWN_INTN (6081L)\n+#define PTP1588_GP_OE_TIMESYNC_CON (6082L)\n+#define PTP1588_MAC_HOST_ADDR (6083L)\n+#define PTP1588_MAC_HOST_ADDR_ADDR (6084L)\n+#define PTP1588_MAC_HOST_ADDR_MDIO_ACCESS (6085L)\n+#define PTP1588_MAC_HOST_ADDR_OPCODE (6086L)\n+#define PTP1588_MAC_HOST_ADDR_RDY (6087L)\n+#define PTP1588_MAC_HOST_DATA_LSB (6088L)\n+#define PTP1588_MAC_HOST_DATA_LSB_DATA (6089L)\n+#define PTP1588_MAC_HOST_DATA_MSB (6090L)\n+#define PTP1588_MAC_HOST_DATA_MSB_DATA (6091L)\n+#define PTP1588_MAC_INBAND_STAT (6092L)\n+#define PTP1588_MAC_INBAND_STAT_DUPLEX (6093L)\n+#define PTP1588_MAC_INBAND_STAT_LINK (6094L)\n+#define PTP1588_MAC_INBAND_STAT_SPEED (6095L)\n+#define PTP1588_MAC_MI_CONF (6096L)\n+#define PTP1588_MAC_MI_CONF_ACCESS_TYPE (6097L)\n+#define PTP1588_MAC_MI_CONF_ADDRESS (6098L)\n+#define PTP1588_MAC_MI_CONF_RDY (6099L)\n+#define PTP1588_MAC_MI_DATA (6100L)\n+#define PTP1588_MAC_MI_DATA_DATA (6101L)\n+#define PTP1588_RX_HOST_ADR_LSB (6102L)\n+#define PTP1588_RX_HOST_ADR_LSB_LSB (6103L)\n+#define PTP1588_RX_HOST_ADR_MSB (6104L)\n+#define PTP1588_RX_HOST_ADR_MSB_MSB (6105L)\n+#define PTP1588_RX_HOST_CONF (6106L)\n+#define PTP1588_RX_HOST_CONF_ENA (6107L)\n+#define PTP1588_RX_HOST_CONF_RDPTR (6108L)\n+#define PTP1588_RX_HOST_CONF_REDUCED (6109L)\n+#define PTP1588_RX_HOST_CTRL (6110L)\n+#define PTP1588_RX_HOST_CTRL_ENA (6111L)\n+#define PTP1588_RX_HOST_CTRL_RDPTR (6112L)\n+#define PTP1588_RX_HOST_CTRL_REDUCED (6113L)\n+#define PTP1588_STAT (6114L)\n+#define PTP1588_STAT_DATA (6115L)\n+#define PTP1588_STAT_CONF (6116L)\n+#define PTP1588_STAT_CONF_INDEX (6117L)\n+#define PTP1588_STAT_CONF_LOCK (6118L)\n+#define PTP1588_STAT_CTRL (6119L)\n+#define PTP1588_STAT_CTRL_INDEX (6120L)\n+#define PTP1588_STAT_CTRL_LOCK (6121L)\n+#define PTP1588_TX_FIRST_DAT (6122L)\n+#define PTP1588_TX_FIRST_DAT_DAT (6123L)\n+#define PTP1588_TX_LAST1_DAT (6124L)\n+#define PTP1588_TX_LAST1_DAT_DAT (6125L)\n+#define PTP1588_TX_LAST2_DAT (6126L)\n+#define PTP1588_TX_LAST2_DAT_DAT (6127L)\n+#define PTP1588_TX_LAST3_DAT (6128L)\n+#define PTP1588_TX_LAST3_DAT_DAT (6129L)\n+#define PTP1588_TX_LAST4_DAT (6130L)\n+#define PTP1588_TX_LAST4_DAT_DAT (6131L)\n+#define PTP1588_TX_MID_DAT (6132L)\n+#define PTP1588_TX_MID_DAT_DAT (6133L)\n+#define PTP1588_TX_PACKET_STATE (6134L)\n+#define PTP1588_TX_PACKET_STATE_MSG_TYPE (6135L)\n+#define PTP1588_TX_PACKET_STATE_PCK_TYPE (6136L)\n+#define PTP1588_TX_PACKET_STATE_SEQ_ID (6137L)\n+#define PTP1588_TX_PACKET_STATE_TEST_MARGIN (6138L)\n+#define PTP1588_TX_PACKET_STATE_VALID (6139L)\n+#define PTP1588_TX_STATUS (6140L)\n+#define PTP1588_TX_STATUS_DB_ERR (6141L)\n+#define PTP1588_TX_STATUS_DB_FULL (6142L)\n+#define PTP1588_TX_STATUS_FIFO_STATUS (6143L)\n+#define PTP1588_TX_STATUS_RDY (6144L)\n+#define PTP1588_TX_STATUS_TG_ENA (6145L)\n+#define PTP1588_TX_STATUS_TG_MODE (6146L)\n+#define PTP1588_TX_TIMESTAMP_NS (6147L)\n+#define PTP1588_TX_TIMESTAMP_NS_TIMESTAMP (6148L)\n+#define PTP1588_TX_TIMESTAMP_SEC (6149L)\n+#define PTP1588_TX_TIMESTAMP_SEC_TIMESTAMP (6150L)\n+/* QM */\n+#define QM_BLOCK_SIZE (6151L)\n+#define QM_BLOCK_SIZE_CELLS (6152L)\n+#define QM_CTRL (6153L)\n+#define QM_CTRL_ACTIVE_QUEUES (6154L)\n+#define QM_CTRL_ACTIVE_QUEUES_QPI_BYPASS (6155L)\n+#define QM_CTRL_ENABLE (6156L)\n+#define QM_CTRL_PRIORITY_SCHEME (6157L)\n+#define QM_DEBUG_BLOCK_SIZE (6158L)\n+#define QM_DEBUG_BLOCK_SIZE_CELLS (6159L)\n+#define QM_DEBUG_CRC (6160L)\n+#define QM_DEBUG_CRC_FORCE_ERROR (6161L)\n+#define QM_DEBUG_SDRAM_SIZE (6162L)\n+#define QM_DEBUG_SDRAM_SIZE_MASK (6163L)\n+#define QM_GROUP_LIMIT_MEM_CTRL (6164L)\n+#define QM_GROUP_LIMIT_MEM_CTRL_A (6165L)\n+#define QM_GROUP_LIMIT_MEM_CTRL_CNT (6166L)\n+#define QM_GROUP_LIMIT_MEM_DATA (6167L)\n+#define QM_GROUP_LIMIT_MEM_DATA_LIMIT (6168L)\n+#define QM_GROUP_MAPPING_MEM_CTRL (6169L)\n+#define QM_GROUP_MAPPING_MEM_CTRL_A (6170L)\n+#define QM_GROUP_MAPPING_MEM_CTRL_CNT (6171L)\n+#define QM_GROUP_MAPPING_MEM_DATA (6172L)\n+#define QM_GROUP_MAPPING_MEM_DATA_GROUP0 (6173L)\n+#define QM_GROUP_MAPPING_MEM_DATA_GROUP1 (6174L)\n+#define QM_GROUP_MAPPING_MEM_DATA_GROUP2 (6175L)\n+#define QM_PRIO_LEVELS_MEM_CTRL (6176L)\n+#define QM_PRIO_LEVELS_MEM_CTRL_A (6177L)\n+#define QM_PRIO_LEVELS_MEM_CTRL_CNT (6178L)\n+#define QM_PRIO_LEVELS_MEM_DATA (6179L)\n+#define QM_PRIO_LEVELS_MEM_DATA_PRIO (6180L)\n+#define QM_QUEUE_LIMIT_MEM_CTRL (6181L)\n+#define QM_QUEUE_LIMIT_MEM_CTRL_A (6182L)\n+#define QM_QUEUE_LIMIT_MEM_CTRL_CNT (6183L)\n+#define QM_QUEUE_LIMIT_MEM_DATA (6184L)\n+#define QM_QUEUE_LIMIT_MEM_DATA_LIMIT (6185L)\n+#define QM_STATUS_BLOCKED (6186L)\n+#define QM_STATUS_BLOCKED_D (6187L)\n+#define QM_STATUS_BLOCKED_HI (6188L)\n+#define QM_STATUS_BLOCKED_HI_D (6189L)\n+#define QM_STATUS_BLOCKING (6190L)\n+#define QM_STATUS_BLOCKING_D (6191L)\n+#define QM_STATUS_BLOCKING_HI (6192L)\n+#define QM_STATUS_BLOCKING_HI_D (6193L)\n+#define QM_STATUS_CRC_ERROR (6194L)\n+#define QM_STATUS_CRC_ERROR_CNT (6195L)\n+#define QM_STATUS_EMPTY (6196L)\n+#define QM_STATUS_EMPTY_D (6197L)\n+#define QM_STATUS_EMPTY_HI (6198L)\n+#define QM_STATUS_EMPTY_HI_D (6199L)\n+#define QM_STATUS_FLUSH_DROP (6200L)\n+#define QM_STATUS_FLUSH_DROP_CNT (6201L)\n+#define QM_STATUS_SDRAM_BLOCK_MAX_USAGE (6202L)\n+#define QM_STATUS_SDRAM_BLOCK_MAX_USAGE_D (6203L)\n+#define QM_STATUS_SDRAM_BLOCK_USAGE (6204L)\n+#define QM_STATUS_SDRAM_BLOCK_USAGE_D (6205L)\n+#define QM_STATUS_SDRAM_CELL_MAX_USAGE (6206L)\n+#define QM_STATUS_SDRAM_CELL_MAX_USAGE_D (6207L)\n+#define QM_STATUS_SDRAM_CELL_USAGE (6208L)\n+#define QM_STATUS_SDRAM_CELL_USAGE_D (6209L)\n+/* QSL */\n+#define QSL_LTX_CTRL (6210L)\n+#define QSL_LTX_CTRL_ADR (6211L)\n+#define QSL_LTX_CTRL_CNT (6212L)\n+#define QSL_LTX_DATA (6213L)\n+#define QSL_LTX_DATA_LR (6214L)\n+#define QSL_LTX_DATA_TSA (6215L)\n+#define QSL_LTX_DATA_TX_PORT (6216L)\n+#define QSL_QEN_CTRL (6217L)\n+#define QSL_QEN_CTRL_ADR (6218L)\n+#define QSL_QEN_CTRL_CNT (6219L)\n+#define QSL_QEN_DATA (6220L)\n+#define QSL_QEN_DATA_EN (6221L)\n+#define QSL_QST_CTRL (6222L)\n+#define QSL_QST_CTRL_ADR (6223L)\n+#define QSL_QST_CTRL_CNT (6224L)\n+#define QSL_QST_DATA (6225L)\n+#define QSL_QST_DATA_EN (6226L)\n+#define QSL_QST_DATA_LRE (6227L)\n+#define QSL_QST_DATA_QEN (6228L)\n+#define QSL_QST_DATA_QUEUE (6229L)\n+#define QSL_QST_DATA_TCI (6230L)\n+#define QSL_QST_DATA_TX_PORT (6231L)\n+#define QSL_QST_DATA_VEN (6232L)\n+#define QSL_RCP_CTRL (6233L)\n+#define QSL_RCP_CTRL_ADR (6234L)\n+#define QSL_RCP_CTRL_CNT (6235L)\n+#define QSL_RCP_DATA (6236L)\n+#define QSL_RCP_DATA_CAO (6237L)\n+#define QSL_RCP_DATA_DISCARD (6238L)\n+#define QSL_RCP_DATA_DROP (6239L)\n+#define QSL_RCP_DATA_LR (6240L)\n+#define QSL_RCP_DATA_TBL_HI (6241L)\n+#define QSL_RCP_DATA_TBL_IDX (6242L)\n+#define QSL_RCP_DATA_TBL_LO (6243L)\n+#define QSL_RCP_DATA_TBL_MSK (6244L)\n+#define QSL_RCP_DATA_TSA (6245L)\n+#define QSL_RCP_DATA_VLI (6246L)\n+#define QSL_UNMQ_CTRL (6247L)\n+#define QSL_UNMQ_CTRL_ADR (6248L)\n+#define QSL_UNMQ_CTRL_CNT (6249L)\n+#define QSL_UNMQ_DATA (6250L)\n+#define QSL_UNMQ_DATA_DEST_QUEUE (6251L)\n+#define QSL_UNMQ_DATA_EN (6252L)\n+/* QSPI */\n+#define QSPI_CR (6253L)\n+#define QSPI_CR_CPHA (6254L)\n+#define QSPI_CR_CPOL (6255L)\n+#define QSPI_CR_LOOP (6256L)\n+#define QSPI_CR_LSBF (6257L)\n+#define QSPI_CR_MSSAE (6258L)\n+#define QSPI_CR_MST (6259L)\n+#define QSPI_CR_MTI (6260L)\n+#define QSPI_CR_RXFIFO_RST (6261L)\n+#define QSPI_CR_SPE (6262L)\n+#define QSPI_CR_TXFIFO_RST (6263L)\n+#define QSPI_DGIE (6264L)\n+#define QSPI_DGIE_GIE (6265L)\n+#define QSPI_DRR (6266L)\n+#define QSPI_DRR_DATA_VAL (6267L)\n+#define QSPI_DTR (6268L)\n+#define QSPI_DTR_DATA_VAL (6269L)\n+#define QSPI_IER (6270L)\n+#define QSPI_IER_CMD_ERR (6271L)\n+#define QSPI_IER_CPOL_CPHA_ERR (6272L)\n+#define QSPI_IER_DRR_FULL (6273L)\n+#define QSPI_IER_DRR_NEMPTY (6274L)\n+#define QSPI_IER_DRR_OR (6275L)\n+#define QSPI_IER_DTR_EMPTY (6276L)\n+#define QSPI_IER_DTR_UR (6277L)\n+#define QSPI_IER_LOOP_ERR (6278L)\n+#define QSPI_IER_MODF (6279L)\n+#define QSPI_IER_MSB_ERR (6280L)\n+#define QSPI_IER_SLV_ERR (6281L)\n+#define QSPI_IER_SLV_MODF (6282L)\n+#define QSPI_IER_SLV_MS (6283L)\n+#define QSPI_IER_TXFIFO_HEMPTY (6284L)\n+#define QSPI_ISR (6285L)\n+#define QSPI_ISR_CMD_ERR (6286L)\n+#define QSPI_ISR_CPOL_CPHA_ERR (6287L)\n+#define QSPI_ISR_DRR_FULL (6288L)\n+#define QSPI_ISR_DRR_NEMPTY (6289L)\n+#define QSPI_ISR_DRR_OR (6290L)\n+#define QSPI_ISR_DTR_EMPTY (6291L)\n+#define QSPI_ISR_DTR_UR (6292L)\n+#define QSPI_ISR_LOOP_ERR (6293L)\n+#define QSPI_ISR_MODF (6294L)\n+#define QSPI_ISR_MSB_ERR (6295L)\n+#define QSPI_ISR_SLV_ERR (6296L)\n+#define QSPI_ISR_SLV_MODF (6297L)\n+#define QSPI_ISR_SLV_MS (6298L)\n+#define QSPI_ISR_TXFIFO_HEMPTY (6299L)\n+#define QSPI_RX_FIFO_OCY (6300L)\n+#define QSPI_RX_FIFO_OCY_OCY_VAL (6301L)\n+#define QSPI_SR (6302L)\n+#define QSPI_SR_CMD_ERR (6303L)\n+#define QSPI_SR_CPOL_CPHA_ERR (6304L)\n+#define QSPI_SR_LOOP_ERR (6305L)\n+#define QSPI_SR_MODF (6306L)\n+#define QSPI_SR_MSB_ERR (6307L)\n+#define QSPI_SR_RXEMPTY (6308L)\n+#define QSPI_SR_RXFULL (6309L)\n+#define QSPI_SR_SLVMS (6310L)\n+#define QSPI_SR_SLV_ERR (6311L)\n+#define QSPI_SR_TXEMPTY (6312L)\n+#define QSPI_SR_TXFULL (6313L)\n+#define QSPI_SRR (6314L)\n+#define QSPI_SRR_RST (6315L)\n+#define QSPI_SSR (6316L)\n+#define QSPI_SSR_SEL_SLV (6317L)\n+#define QSPI_TX_FIFO_OCY (6318L)\n+#define QSPI_TX_FIFO_OCY_OCY_VAL (6319L)\n+/* R2DRP */\n+#define R2DRP_CTRL (6320L)\n+#define R2DRP_CTRL_ADR (6321L)\n+#define R2DRP_CTRL_DATA (6322L)\n+#define R2DRP_CTRL_DBG_BUSY (6323L)\n+#define R2DRP_CTRL_DONE (6324L)\n+#define R2DRP_CTRL_RES (6325L)\n+#define R2DRP_CTRL_WREN (6326L)\n+/* RAC */\n+#define RAC_DBG_CTRL (6327L)\n+#define RAC_DBG_CTRL_C (6328L)\n+#define RAC_DBG_DATA (6329L)\n+#define RAC_DBG_DATA_D (6330L)\n+#define RAC_DUMMY0 (6331L)\n+#define RAC_DUMMY1 (6332L)\n+#define RAC_DUMMY2 (6333L)\n+#define RAC_NDM_REGISTER (6334L)\n+#define RAC_NDM_REGISTER_NDM (6335L)\n+#define RAC_NMB_DATA (6336L)\n+#define RAC_NMB_DATA_NMB_DATA (6337L)\n+#define RAC_NMB_RD_ADR (6338L)\n+#define RAC_NMB_RD_ADR_ADR (6339L)\n+#define RAC_NMB_RD_ADR_RES (6340L)\n+#define RAC_NMB_STATUS (6341L)\n+#define RAC_NMB_STATUS_BUS_TIMEOUT (6342L)\n+#define RAC_NMB_STATUS_NMB_READY (6343L)\n+#define RAC_NMB_WR_ADR (6344L)\n+#define RAC_NMB_WR_ADR_ADR (6345L)\n+#define RAC_NMB_WR_ADR_RES (6346L)\n+#define RAC_RAB_BUF_FREE (6347L)\n+#define RAC_RAB_BUF_FREE_IB_FREE (6348L)\n+#define RAC_RAB_BUF_FREE_IB_OVF (6349L)\n+#define RAC_RAB_BUF_FREE_OB_FREE (6350L)\n+#define RAC_RAB_BUF_FREE_OB_OVF (6351L)\n+#define RAC_RAB_BUF_FREE_TIMEOUT (6352L)\n+#define RAC_RAB_BUF_USED (6353L)\n+#define RAC_RAB_BUF_USED_FLUSH (6354L)\n+#define RAC_RAB_BUF_USED_IB_USED (6355L)\n+#define RAC_RAB_BUF_USED_OB_USED (6356L)\n+#define RAC_RAB_DMA_IB_HI (6357L)\n+#define RAC_RAB_DMA_IB_HI_PHYADDR (6358L)\n+#define RAC_RAB_DMA_IB_LO (6359L)\n+#define RAC_RAB_DMA_IB_LO_PHYADDR (6360L)\n+#define RAC_RAB_DMA_IB_RD (6361L)\n+#define RAC_RAB_DMA_IB_RD_PTR (6362L)\n+#define RAC_RAB_DMA_IB_WR (6363L)\n+#define RAC_RAB_DMA_IB_WR_PTR (6364L)\n+#define RAC_RAB_DMA_OB_HI (6365L)\n+#define RAC_RAB_DMA_OB_HI_PHYADDR (6366L)\n+#define RAC_RAB_DMA_OB_LO (6367L)\n+#define RAC_RAB_DMA_OB_LO_PHYADDR (6368L)\n+#define RAC_RAB_DMA_OB_WR (6369L)\n+#define RAC_RAB_DMA_OB_WR_PTR (6370L)\n+#define RAC_RAB_IB_DATA (6371L)\n+#define RAC_RAB_IB_DATA_D (6372L)\n+#define RAC_RAB_INIT (6373L)\n+#define RAC_RAB_INIT_RAB (6374L)\n+#define RAC_RAB_OB_DATA (6375L)\n+#define RAC_RAB_OB_DATA_D (6376L)\n+/* RBH */\n+#define RBH_CTRL (6377L)\n+#define RBH_CTRL_ENABLE_METADATA_HB (6378L)\n+#define RBH_CTRL_ENABLE_PM (6379L)\n+#define RBH_CTRL_ENABLE_QHM (6380L)\n+#define RBH_CTRL_HB_MAX (6381L)\n+#define RBH_CTRL_HB_SEGMENT_SIZE (6382L)\n+#define RBH_CTRL_RESERVED (6383L)\n+#define RBH_CTRL_RESET_CREDITS_QHM (6384L)\n+#define RBH_DEB_REG1 (6385L)\n+#define RBH_DEB_REG1_VALUE (6386L)\n+#define RBH_DEB_REG2 (6387L)\n+#define RBH_DEB_REG2_VALUE (6388L)\n+#define RBH_DEB_REG3 (6389L)\n+#define RBH_DEB_REG3_VALUE (6390L)\n+#define RBH_FLUSH_ADR_HI (6391L)\n+#define RBH_FLUSH_ADR_HI_VALUE (6392L)\n+#define RBH_FLUSH_ADR_LO (6393L)\n+#define RBH_FLUSH_ADR_LO_VALUE (6394L)\n+#define RBH_HOST_BUF_SIZE_MEM_CTRL (6395L)\n+#define RBH_HOST_BUF_SIZE_MEM_CTRL_A (6396L)\n+#define RBH_HOST_BUF_SIZE_MEM_CTRL_CNT (6397L)\n+#define RBH_HOST_BUF_SIZE_MEM_DATA (6398L)\n+#define RBH_HOST_BUF_SIZE_MEM_DATA_HB_SEGMENT_CNT (6399L)\n+#define RBH_STATUS (6400L)\n+#define RBH_STATUS_BUFFER_EMPTY (6401L)\n+#define RBH_STATUS_DWA_DATAFIFO_EMPTY (6402L)\n+#define RBH_STATUS_PWA_DATAFIFO_EMPTY (6403L)\n+#define RBH_WP_SET_MEM_CTRL (6404L)\n+#define RBH_WP_SET_MEM_CTRL_A (6405L)\n+#define RBH_WP_SET_MEM_CTRL_CNT (6406L)\n+#define RBH_WP_SET_MEM_DATA (6407L)\n+#define RBH_WP_SET_MEM_DATA_WP (6408L)\n+/* RFD */\n+#define RFD_CTRL (6409L)\n+#define RFD_CTRL_CFP (6410L)\n+#define RFD_CTRL_ISL (6411L)\n+#define RFD_CTRL_PWMCW (6412L)\n+#define RFD_MAX_FRAME_SIZE (6413L)\n+#define RFD_MAX_FRAME_SIZE_MAX (6414L)\n+#define RFD_TNL_VLAN (6415L)\n+#define RFD_TNL_VLAN_TPID0 (6416L)\n+#define RFD_TNL_VLAN_TPID1 (6417L)\n+#define RFD_VLAN (6418L)\n+#define RFD_VLAN_TPID0 (6419L)\n+#define RFD_VLAN_TPID1 (6420L)\n+#define RFD_VXLAN (6421L)\n+#define RFD_VXLAN_DP0 (6422L)\n+#define RFD_VXLAN_DP1 (6423L)\n+/* RMC */\n+#define RMC_CTRL (6424L)\n+#define RMC_CTRL_BLOCK_KEEPA (6425L)\n+#define RMC_CTRL_BLOCK_MAC_PORT (6426L)\n+#define RMC_CTRL_BLOCK_RPP_SLICE (6427L)\n+#define RMC_CTRL_BLOCK_STATT (6428L)\n+#define RMC_CTRL_LAG_PHY_ODD_EVEN (6429L)\n+#define RMC_DBG (6430L)\n+#define RMC_DBG_MERGE (6431L)\n+#define RMC_MAC_IF (6432L)\n+#define RMC_MAC_IF_ERR (6433L)\n+#define RMC_STATUS (6434L)\n+#define RMC_STATUS_DESCR_FIFO_OF (6435L)\n+#define RMC_STATUS_SF_RAM_OF (6436L)\n+/* RNTC */\n+#define RNTC_CTRL (6437L)\n+#define RNTC_CTRL_RNTC_ENA (6438L)\n+#define RNTC_STAT (6439L)\n+#define RNTC_STAT_EMPTY (6440L)\n+#define RNTC_TX_DATA (6441L)\n+#define RNTC_TX_DATA_D (6442L)\n+/* ROA */\n+#define ROA_CONFIG (6443L)\n+#define ROA_CONFIG_FWD_CELLBUILDER_PCKS (6444L)\n+#define ROA_CONFIG_FWD_NON_NORMAL_PCKS (6445L)\n+#define ROA_CONFIG_FWD_NORMAL_PCKS (6446L)\n+#define ROA_CONFIG_FWD_RECIRCULATE (6447L)\n+#define ROA_CONFIG_FWD_TXPORT0 (6448L)\n+#define ROA_CONFIG_FWD_TXPORT1 (6449L)\n+#define ROA_IGS (6450L)\n+#define ROA_IGS_BYTE (6451L)\n+#define ROA_IGS_BYTE_DROP (6452L)\n+#define ROA_IGS_PKT (6453L)\n+#define ROA_IGS_PKT_DROP (6454L)\n+#define ROA_LAGCFG_CTRL (6455L)\n+#define ROA_LAGCFG_CTRL_ADR (6456L)\n+#define ROA_LAGCFG_CTRL_CNT (6457L)\n+#define ROA_LAGCFG_DATA (6458L)\n+#define ROA_LAGCFG_DATA_TXPHY_PORT (6459L)\n+#define ROA_RCC (6460L)\n+#define ROA_RCC_BYTE (6461L)\n+#define ROA_RCC_BYTE_DROP (6462L)\n+#define ROA_RCC_PKT (6463L)\n+#define ROA_RCC_PKT_DROP (6464L)\n+#define ROA_TUNCFG_CTRL (6465L)\n+#define ROA_TUNCFG_CTRL_ADR (6466L)\n+#define ROA_TUNCFG_CTRL_CNT (6467L)\n+#define ROA_TUNCFG_DATA (6468L)\n+#define ROA_TUNCFG_DATA_PUSH_TUNNEL (6469L)\n+#define ROA_TUNCFG_DATA_RECIRCULATE (6470L)\n+#define ROA_TUNCFG_DATA_RECIRC_BYPASS (6471L)\n+#define ROA_TUNCFG_DATA_RECIRC_PORT (6472L)\n+#define ROA_TUNCFG_DATA_TUN_IPCS_PRECALC (6473L)\n+#define ROA_TUNCFG_DATA_TUN_IPCS_UPD (6474L)\n+#define ROA_TUNCFG_DATA_TUN_IPTL_PRECALC (6475L)\n+#define ROA_TUNCFG_DATA_TUN_IPTL_UPD (6476L)\n+#define ROA_TUNCFG_DATA_TUN_IP_TYPE (6477L)\n+#define ROA_TUNCFG_DATA_TUN_LEN (6478L)\n+#define ROA_TUNCFG_DATA_TUN_TYPE (6479L)\n+#define ROA_TUNCFG_DATA_TUN_VLAN (6480L)\n+#define ROA_TUNCFG_DATA_TUN_VXLAN_UDP_LEN_UPD (6481L)\n+#define ROA_TUNCFG_DATA_TX_LAG_IX (6482L)\n+#define ROA_TUNHDR_CTRL (6483L)\n+#define ROA_TUNHDR_CTRL_ADR (6484L)\n+#define ROA_TUNHDR_CTRL_CNT (6485L)\n+#define ROA_TUNHDR_DATA (6486L)\n+#define ROA_TUNHDR_DATA_TUNNEL_HDR (6487L)\n+/* RPL */\n+#define RPL_EXT_CTRL (6488L)\n+#define RPL_EXT_CTRL_ADR (6489L)\n+#define RPL_EXT_CTRL_CNT (6490L)\n+#define RPL_EXT_DATA (6491L)\n+#define RPL_EXT_DATA_RPL_PTR (6492L)\n+#define RPL_RCP_CTRL (6493L)\n+#define RPL_RCP_CTRL_ADR (6494L)\n+#define RPL_RCP_CTRL_CNT (6495L)\n+#define RPL_RCP_DATA (6496L)\n+#define RPL_RCP_DATA_DYN (6497L)\n+#define RPL_RCP_DATA_EXT_PRIO (6498L)\n+#define RPL_RCP_DATA_LEN (6499L)\n+#define RPL_RCP_DATA_OFS (6500L)\n+#define RPL_RCP_DATA_RPL_PTR (6501L)\n+#define RPL_RPL_CTRL (6502L)\n+#define RPL_RPL_CTRL_ADR (6503L)\n+#define RPL_RPL_CTRL_CNT (6504L)\n+#define RPL_RPL_DATA (6505L)\n+#define RPL_RPL_DATA_VALUE (6506L)\n+/* RPP_LR */\n+#define RPP_LR_IFR_RCP_CTRL (6507L)\n+#define RPP_LR_IFR_RCP_CTRL_ADR (6508L)\n+#define RPP_LR_IFR_RCP_CTRL_CNT (6509L)\n+#define RPP_LR_IFR_RCP_DATA (6510L)\n+#define RPP_LR_IFR_RCP_DATA_EN (6511L)\n+#define RPP_LR_IFR_RCP_DATA_MTU (6512L)\n+#define RPP_LR_RCP_CTRL (6513L)\n+#define RPP_LR_RCP_CTRL_ADR (6514L)\n+#define RPP_LR_RCP_CTRL_CNT (6515L)\n+#define RPP_LR_RCP_DATA (6516L)\n+#define RPP_LR_RCP_DATA_EXP (6517L)\n+/* RST7000 */\n+#define RST7000_RST (6518L)\n+#define RST7000_RST_SYS (6519L)\n+/* RST7001 */\n+#define RST7001_RST (6520L)\n+#define RST7001_RST_SYS (6521L)\n+/* RST9500 */\n+#define RST9500_CTRL (6598L)\n+#define RST9500_CTRL_PTP_MMCM_CLKSEL (6599L)\n+#define RST9500_CTRL_TS_CLKSEL (6600L)\n+#define RST9500_CTRL_TS_CLKSEL_OVERRIDE (6601L)\n+#define RST9500_RST (6602L)\n+#define RST9500_RST_DDR3 (6603L)\n+#define RST9500_RST_DDR3_IDLY_MMCM (6604L)\n+#define RST9500_RST_PERIPH (6605L)\n+#define RST9500_RST_PHY10G_QPLL (6606L)\n+#define RST9500_RST_PHY3S10G (6607L)\n+#define RST9500_RST_PHY3S_MMCM (6608L)\n+#define RST9500_RST_PTP (6609L)\n+#define RST9500_RST_PTP_MMCM (6610L)\n+#define RST9500_RST_RPP (6611L)\n+#define RST9500_RST_SDC (6612L)\n+#define RST9500_RST_SI5326 (6613L)\n+#define RST9500_RST_SYS (6614L)\n+#define RST9500_RST_TS (6615L)\n+#define RST9500_RST_TS_MMCM (6616L)\n+#define RST9500_RST_STAT (6617L)\n+#define RST9500_RST_STAT_PCS_RESET_BY_SERDES (6618L)\n+#define RST9500_STAT (6619L)\n+#define RST9500_STAT_DDR3_IDLY_MMCM_LOCKED (6620L)\n+#define RST9500_STAT_DDR3_MMCM_LOCKED (6621L)\n+#define RST9500_STAT_DDR3_PLL_LOCKED (6622L)\n+#define RST9500_STAT_PHY10G_QPLL_LOCK_0_1 (6623L)\n+#define RST9500_STAT_PHY10G_QPLL_LOCK_2_3 (6624L)\n+#define RST9500_STAT_PHY3S_MMCM_LOCKED (6625L)\n+#define RST9500_STAT_PTP_MMCM_LOCKED (6626L)\n+#define RST9500_STAT_SYNCE_MAIN_CLK_LOS (6627L)\n+#define RST9500_STAT_SYS_MMCM_LOCKED (6628L)\n+#define RST9500_STAT_TS_MMCM_LOCKED (6629L)\n+#define RST9500_STICKY (6630L)\n+#define RST9500_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6631L)\n+#define RST9500_STICKY_DDR3_MMCM_UNLOCKED (6632L)\n+#define RST9500_STICKY_DDR3_PLL_UNLOCKED (6633L)\n+#define RST9500_STICKY_PHY10G_QPLL_UNLOCK_0_1 (6634L)\n+#define RST9500_STICKY_PHY10G_QPLL_UNLOCK_2_3 (6635L)\n+#define RST9500_STICKY_PHY3S_MMCM_UNLOCKED (6636L)\n+#define RST9500_STICKY_PTP_MMCM_UNLOCKED (6637L)\n+#define RST9500_STICKY_TS_MMCM_UNLOCKED (6638L)\n+/* RST9501 */\n+#define RST9501_CTRL (6639L)\n+#define RST9501_CTRL_PTP_MMCM_CLKSEL (6640L)\n+#define RST9501_CTRL_TS_CLKSEL (6641L)\n+#define RST9501_CTRL_TS_CLKSEL_OVERRIDE (6642L)\n+#define RST9501_RST (6643L)\n+#define RST9501_RST_DDR3 (6644L)\n+#define RST9501_RST_DDR3_IDLY_MMCM (6645L)\n+#define RST9501_RST_PERIPH (6646L)\n+#define RST9501_RST_PHY10G_QPLL (6647L)\n+#define RST9501_RST_PHY3S10G (6648L)\n+#define RST9501_RST_PHY3S_MMCM (6649L)\n+#define RST9501_RST_PTP (6650L)\n+#define RST9501_RST_PTP_MMCM (6651L)\n+#define RST9501_RST_RPP (6652L)\n+#define RST9501_RST_SDC (6653L)\n+#define RST9501_RST_SI5326 (6654L)\n+#define RST9501_RST_SYS (6655L)\n+#define RST9501_RST_TS (6656L)\n+#define RST9501_RST_TS_MMCM (6657L)\n+#define RST9501_RST_STAT (6658L)\n+#define RST9501_RST_STAT_PCS_RESET_BY_SERDES (6659L)\n+#define RST9501_STAT (6660L)\n+#define RST9501_STAT_DDR3_IDLY_MMCM_LOCKED (6661L)\n+#define RST9501_STAT_DDR3_MMCM_LOCKED (6662L)\n+#define RST9501_STAT_DDR3_PLL_LOCKED (6663L)\n+#define RST9501_STAT_PHY10G_QPLL_LOCK_0_1 (6664L)\n+#define RST9501_STAT_PHY10G_QPLL_LOCK_2_3 (6665L)\n+#define RST9501_STAT_PHY3S_MMCM_LOCKED (6666L)\n+#define RST9501_STAT_PTP_MMCM_LOCKED (6667L)\n+#define RST9501_STAT_SYNCE_MAIN_CLK_LOS (6668L)\n+#define RST9501_STAT_SYS_MMCM_LOCKED (6669L)\n+#define RST9501_STAT_TS_MMCM_LOCKED (6670L)\n+#define RST9501_STICKY (6671L)\n+#define RST9501_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6672L)\n+#define RST9501_STICKY_DDR3_MMCM_UNLOCKED (6673L)\n+#define RST9501_STICKY_DDR3_PLL_UNLOCKED (6674L)\n+#define RST9501_STICKY_PHY10G_QPLL_UNLOCK_0_1 (6675L)\n+#define RST9501_STICKY_PHY10G_QPLL_UNLOCK_2_3 (6676L)\n+#define RST9501_STICKY_PHY3S_MMCM_UNLOCKED (6677L)\n+#define RST9501_STICKY_PTP_MMCM_UNLOCKED (6678L)\n+#define RST9501_STICKY_TS_MMCM_UNLOCKED (6679L)\n+/* RST9502 */\n+#define RST9502_CTRL (6680L)\n+#define RST9502_CTRL_PTP_MMCM_CLKSEL (6681L)\n+#define RST9502_CTRL_TS_CLKSEL (6682L)\n+#define RST9502_CTRL_TS_CLKSEL_OVERRIDE (6683L)\n+#define RST9502_RST (6684L)\n+#define RST9502_RST_DDR3 (6685L)\n+#define RST9502_RST_DDR3_IDLY_MMCM (6686L)\n+#define RST9502_RST_NSEB (6687L)\n+#define RST9502_RST_PERIPH (6688L)\n+#define RST9502_RST_PHY10G_QPLL (6689L)\n+#define RST9502_RST_PHY3S10G (6690L)\n+#define RST9502_RST_PHY3S_MMCM (6691L)\n+#define RST9502_RST_PTP (6692L)\n+#define RST9502_RST_PTP_MMCM (6693L)\n+#define RST9502_RST_RPP (6694L)\n+#define RST9502_RST_SDC (6695L)\n+#define RST9502_RST_SI5326 (6696L)\n+#define RST9502_RST_SYS (6697L)\n+#define RST9502_RST_TS (6698L)\n+#define RST9502_RST_TS_MMCM (6699L)\n+#define RST9502_RST_STAT (6700L)\n+#define RST9502_RST_STAT_PCS_RESET_BY_SERDES (6701L)\n+#define RST9502_STAT (6702L)\n+#define RST9502_STAT_DDR3_IDLY_MMCM_LOCKED (6703L)\n+#define RST9502_STAT_DDR3_MMCM_LOCKED (6704L)\n+#define RST9502_STAT_DDR3_PLL_LOCKED (6705L)\n+#define RST9502_STAT_PHY10G_QPLL_LOCK_0_1 (6706L)\n+#define RST9502_STAT_PHY10G_QPLL_LOCK_2_3 (6707L)\n+#define RST9502_STAT_PHY3S_MMCM_LOCKED (6708L)\n+#define RST9502_STAT_PTP_MMCM_LOCKED (6709L)\n+#define RST9502_STAT_SYNCE_MAIN_CLK_LOS (6710L)\n+#define RST9502_STAT_SYS_MMCM_LOCKED (6711L)\n+#define RST9502_STAT_TS_MMCM_LOCKED (6712L)\n+#define RST9502_STICKY (6713L)\n+#define RST9502_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6714L)\n+#define RST9502_STICKY_DDR3_MMCM_UNLOCKED (6715L)\n+#define RST9502_STICKY_DDR3_PLL_UNLOCKED (6716L)\n+#define RST9502_STICKY_PHY10G_QPLL_UNLOCK_0_1 (6717L)\n+#define RST9502_STICKY_PHY10G_QPLL_UNLOCK_2_3 (6718L)\n+#define RST9502_STICKY_PHY3S_MMCM_UNLOCKED (6719L)\n+#define RST9502_STICKY_PTP_MMCM_UNLOCKED (6720L)\n+#define RST9502_STICKY_TS_MMCM_UNLOCKED (6721L)\n+/* RST9503 */\n+#define RST9503_CTRL (6722L)\n+#define RST9503_CTRL_PTP_MMCM_CLKSEL (6723L)\n+#define RST9503_CTRL_TS_CLKSEL (6724L)\n+#define RST9503_CTRL_TS_CLKSEL_OVERRIDE (6725L)\n+#define RST9503_PORT_CLK_SEL (6726L)\n+#define RST9503_PORT_CLK_SEL_PORT0 (6727L)\n+#define RST9503_PORT_CLK_SEL_PORT1 (6728L)\n+#define RST9503_RST (6729L)\n+#define RST9503_RST_DDR3 (6730L)\n+#define RST9503_RST_DDR3_IDLY_MMCM (6731L)\n+#define RST9503_RST_MAC_RX (6732L)\n+#define RST9503_RST_MAC_RX_MMCM (6733L)\n+#define RST9503_RST_MAC_TX (6734L)\n+#define RST9503_RST_NSEB (6735L)\n+#define RST9503_RST_PCS_RX (6736L)\n+#define RST9503_RST_PERIPH (6737L)\n+#define RST9503_RST_PHY40G (6738L)\n+#define RST9503_RST_PTP (6739L)\n+#define RST9503_RST_PTP_MMCM (6740L)\n+#define RST9503_RST_RPP (6741L)\n+#define RST9503_RST_SDC (6742L)\n+#define RST9503_RST_SERDES_RX (6743L)\n+#define RST9503_RST_SERDES_TX (6744L)\n+#define RST9503_RST_SI5326 (6745L)\n+#define RST9503_RST_SYS (6746L)\n+#define RST9503_RST_TS (6747L)\n+#define RST9503_RST_TS_MMCM (6748L)\n+#define RST9503_RST_STAT (6749L)\n+#define RST9503_RST_STAT_PCS_RESET_BY_SERDES (6750L)\n+#define RST9503_STAT (6751L)\n+#define RST9503_STAT_DDR3_IDLY_MMCM_LOCKED (6752L)\n+#define RST9503_STAT_DDR3_MMCM_LOCKED (6753L)\n+#define RST9503_STAT_DDR3_PLL_LOCKED (6754L)\n+#define RST9503_STAT_MAC_RX_MMCM_LOCKED (6755L)\n+#define RST9503_STAT_PTP_MMCM_LOCKED (6756L)\n+#define RST9503_STAT_SYNCE_MAIN_CLK_LOS (6757L)\n+#define RST9503_STAT_SYS_MMCM_LOCKED (6758L)\n+#define RST9503_STAT_TS_MMCM_LOCKED (6759L)\n+#define RST9503_STICKY (6760L)\n+#define RST9503_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6761L)\n+#define RST9503_STICKY_DDR3_MMCM_UNLOCKED (6762L)\n+#define RST9503_STICKY_DDR3_PLL_UNLOCKED (6763L)\n+#define RST9503_STICKY_MAC_RX_MMCM_UNLOCKED (6764L)\n+#define RST9503_STICKY_PTP_MMCM_UNLOCKED (6765L)\n+#define RST9503_STICKY_TS_MMCM_UNLOCKED (6766L)\n+/* RST9504 */\n+#define RST9504_CTRL (6767L)\n+#define RST9504_CTRL_PTP_MMCM_CLKSEL (6768L)\n+#define RST9504_CTRL_TS_CLKSEL (6769L)\n+#define RST9504_CTRL_TS_CLKSEL_OVERRIDE (6770L)\n+#define RST9504_RST (6771L)\n+#define RST9504_RST_DDR3 (6772L)\n+#define RST9504_RST_DDR3_IDLY_MMCM (6773L)\n+#define RST9504_RST_MAC_RX (6774L)\n+#define RST9504_RST_MAC_RX_MMCM (6775L)\n+#define RST9504_RST_MAC_TX (6776L)\n+#define RST9504_RST_NSEB (6777L)\n+#define RST9504_RST_PCS_RX (6778L)\n+#define RST9504_RST_PERIPH (6779L)\n+#define RST9504_RST_PHY100G (6780L)\n+#define RST9504_RST_PTP (6781L)\n+#define RST9504_RST_PTP_MMCM (6782L)\n+#define RST9504_RST_RPP (6783L)\n+#define RST9504_RST_SDC (6784L)\n+#define RST9504_RST_SERDES_RX (6785L)\n+#define RST9504_RST_SERDES_TX (6786L)\n+#define RST9504_RST_SI5326 (6787L)\n+#define RST9504_RST_SYS (6788L)\n+#define RST9504_RST_TS (6789L)\n+#define RST9504_RST_TS_MMCM (6790L)\n+#define RST9504_RST_STAT (6791L)\n+#define RST9504_RST_STAT_PCS_RESET_BY_SERDES (6792L)\n+#define RST9504_STAT (6793L)\n+#define RST9504_STAT_DDR3_IDLY_MMCM_LOCKED (6794L)\n+#define RST9504_STAT_DDR3_MMCM_LOCKED (6795L)\n+#define RST9504_STAT_DDR3_PLL_LOCKED (6796L)\n+#define RST9504_STAT_MAC_RX_MMCM_LOCKED (6797L)\n+#define RST9504_STAT_PTP_MMCM_LOCKED (6798L)\n+#define RST9504_STAT_SYNCE_MAIN_CLK_LOS (6799L)\n+#define RST9504_STAT_SYS_MMCM_LOCKED (6800L)\n+#define RST9504_STAT_TS_MMCM_LOCKED (6801L)\n+#define RST9504_STICKY (6802L)\n+#define RST9504_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6803L)\n+#define RST9504_STICKY_DDR3_MMCM_UNLOCKED (6804L)\n+#define RST9504_STICKY_DDR3_PLL_UNLOCKED (6805L)\n+#define RST9504_STICKY_MAC_RX_MMCM_UNLOCKED (6806L)\n+#define RST9504_STICKY_PTP_MMCM_UNLOCKED (6807L)\n+#define RST9504_STICKY_TS_MMCM_UNLOCKED (6808L)\n+/* RST9505 */\n+#define RST9505_CTRL (6809L)\n+#define RST9505_CTRL_PTP_MMCM_CLKSEL (6810L)\n+#define RST9505_CTRL_TS_CLKSEL (6811L)\n+#define RST9505_CTRL_TS_CLKSEL_OVERRIDE (6812L)\n+#define RST9505_RST (6813L)\n+#define RST9505_RST_DDR3 (6814L)\n+#define RST9505_RST_DDR3_IDLY_MMCM (6815L)\n+#define RST9505_RST_MAC_RX (6816L)\n+#define RST9505_RST_MAC_RX_MMCM (6817L)\n+#define RST9505_RST_MAC_TX (6818L)\n+#define RST9505_RST_NSEB (6819L)\n+#define RST9505_RST_PCS_RX (6820L)\n+#define RST9505_RST_PERIPH (6821L)\n+#define RST9505_RST_PHY100G (6822L)\n+#define RST9505_RST_PTP (6823L)\n+#define RST9505_RST_PTP_MMCM (6824L)\n+#define RST9505_RST_RPP (6825L)\n+#define RST9505_RST_SDC (6826L)\n+#define RST9505_RST_SERDES_RX (6827L)\n+#define RST9505_RST_SERDES_TX (6828L)\n+#define RST9505_RST_SI5326 (6829L)\n+#define RST9505_RST_SYS (6830L)\n+#define RST9505_RST_TS (6831L)\n+#define RST9505_RST_TS_MMCM (6832L)\n+#define RST9505_RST_STAT (6833L)\n+#define RST9505_RST_STAT_PCS_RESET_BY_SERDES (6834L)\n+#define RST9505_STAT (6835L)\n+#define RST9505_STAT_DDR3_IDLY_MMCM_LOCKED (6836L)\n+#define RST9505_STAT_DDR3_MMCM_LOCKED (6837L)\n+#define RST9505_STAT_DDR3_PLL_LOCKED (6838L)\n+#define RST9505_STAT_MAC_RX_MMCM_LOCKED (6839L)\n+#define RST9505_STAT_PTP_MMCM_LOCKED (6840L)\n+#define RST9505_STAT_SYNCE_MAIN_CLK_LOS (6841L)\n+#define RST9505_STAT_SYS_MMCM_LOCKED (6842L)\n+#define RST9505_STAT_TS_MMCM_LOCKED (6843L)\n+#define RST9505_STICKY (6844L)\n+#define RST9505_STICKY_DDR3_IDLY_MMCM_UNLOCKED (6845L)\n+#define RST9505_STICKY_DDR3_MMCM_UNLOCKED (6846L)\n+#define RST9505_STICKY_DDR3_PLL_UNLOCKED (6847L)\n+#define RST9505_STICKY_MAC_RX_MMCM_UNLOCKED (6848L)\n+#define RST9505_STICKY_PTP_MMCM_UNLOCKED (6849L)\n+#define RST9505_STICKY_TS_MMCM_UNLOCKED (6850L)\n+/* RST9506 */\n+/* RST9507 */\n+/* RST9508 */\n+#define RST9508_CTRL (6851L)\n+#define RST9508_CTRL_PTP_MMCM_CLKSEL (6852L)\n+#define RST9508_CTRL_TS_CLKSEL (6853L)\n+#define RST9508_CTRL_TS_CLKSEL_OVERRIDE (6854L)\n+#define RST9508_CTRL_TS_CLKSEL_REF (6855L)\n+#define RST9508_POWER (6856L)\n+#define RST9508_POWER_PU_NSEB (6857L)\n+#define RST9508_POWER_PU_PHY (6858L)\n+#define RST9508_RST (6859L)\n+#define RST9508_RST_CORE_MMCM (6860L)\n+#define RST9508_RST_DDR4 (6861L)\n+#define RST9508_RST_MAC_RX (6862L)\n+#define RST9508_RST_PERIPH (6863L)\n+#define RST9508_RST_PHY (6864L)\n+#define RST9508_RST_PTP (6865L)\n+#define RST9508_RST_PTP_MMCM (6866L)\n+#define RST9508_RST_RPP (6867L)\n+#define RST9508_RST_SDC (6868L)\n+#define RST9508_RST_SYS (6869L)\n+#define RST9508_RST_SYS_MMCM (6870L)\n+#define RST9508_RST_TMC (6871L)\n+#define RST9508_RST_TS (6872L)\n+#define RST9508_RST_TSM_REF_MMCM (6873L)\n+#define RST9508_RST_TS_MMCM (6874L)\n+#define RST9508_STAT (6875L)\n+#define RST9508_STAT_CORE_MMCM_LOCKED (6876L)\n+#define RST9508_STAT_DDR4_MMCM_LOCKED (6877L)\n+#define RST9508_STAT_DDR4_PLL_LOCKED (6878L)\n+#define RST9508_STAT_PCI_SYS_MMCM_LOCKED (6879L)\n+#define RST9508_STAT_PTP_MMCM_LOCKED (6880L)\n+#define RST9508_STAT_SYS_MMCM_LOCKED (6881L)\n+#define RST9508_STAT_TSM_REF_MMCM_LOCKED (6882L)\n+#define RST9508_STAT_TS_MMCM_LOCKED (6883L)\n+#define RST9508_STICKY (6884L)\n+#define RST9508_STICKY_CORE_MMCM_UNLOCKED (6885L)\n+#define RST9508_STICKY_DDR4_MMCM_UNLOCKED (6886L)\n+#define RST9508_STICKY_DDR4_PLL_UNLOCKED (6887L)\n+#define RST9508_STICKY_PCI_SYS_MMCM_UNLOCKED (6888L)\n+#define RST9508_STICKY_PTP_MMCM_UNLOCKED (6889L)\n+#define RST9508_STICKY_SYS_MMCM_UNLOCKED (6890L)\n+#define RST9508_STICKY_TSM_REF_MMCM_UNLOCKED (6891L)\n+#define RST9508_STICKY_TS_MMCM_UNLOCKED (6892L)\n+/* RST9509 */\n+/* RST9510 */\n+/* RST9512 */\n+#define RST9512_CTRL (6893L)\n+#define RST9512_CTRL_PTP_MMCM_CLKSEL (6894L)\n+#define RST9512_CTRL_TS_CLKSEL (6895L)\n+#define RST9512_CTRL_TS_CLKSEL_OVERRIDE (6896L)\n+#define RST9512_CTRL_TS_CLKSEL_REF (6897L)\n+#define RST9512_POWER (6898L)\n+#define RST9512_POWER_PU_NSEB (6899L)\n+#define RST9512_POWER_PU_PHY (6900L)\n+#define RST9512_RST (6901L)\n+#define RST9512_RST_CORE_MMCM (6902L)\n+#define RST9512_RST_DDR4 (6903L)\n+#define RST9512_RST_MAC_RX (6904L)\n+#define RST9512_RST_MAC_TX (6905L)\n+#define RST9512_RST_PCS_RX (6906L)\n+#define RST9512_RST_PERIPH (6907L)\n+#define RST9512_RST_PHY (6908L)\n+#define RST9512_RST_PTP (6909L)\n+#define RST9512_RST_PTP_MMCM (6910L)\n+#define RST9512_RST_RPP (6911L)\n+#define RST9512_RST_SDC (6912L)\n+#define RST9512_RST_SERDES_RX (6913L)\n+#define RST9512_RST_SERDES_RX_DATAPATH (6914L)\n+#define RST9512_RST_SERDES_TX (6915L)\n+#define RST9512_RST_SYS (6916L)\n+#define RST9512_RST_SYS_MMCM (6917L)\n+#define RST9512_RST_TS (6918L)\n+#define RST9512_RST_TSM_REF_MMCM (6919L)\n+#define RST9512_RST_TS_MMCM (6920L)\n+#define RST9512_STAT (6921L)\n+#define RST9512_STAT_CORE_MMCM_LOCKED (6922L)\n+#define RST9512_STAT_DDR4_MMCM_LOCKED (6923L)\n+#define RST9512_STAT_DDR4_PLL_LOCKED (6924L)\n+#define RST9512_STAT_PCI_SYS_MMCM_LOCKED (6925L)\n+#define RST9512_STAT_PTP_MMCM_LOCKED (6926L)\n+#define RST9512_STAT_SYS_MMCM_LOCKED (6927L)\n+#define RST9512_STAT_TSM_REF_MMCM_LOCKED (6928L)\n+#define RST9512_STAT_TS_MMCM_LOCKED (6929L)\n+#define RST9512_STICKY (6930L)\n+#define RST9512_STICKY_CORE_MMCM_UNLOCKED (6931L)\n+#define RST9512_STICKY_DDR4_MMCM_UNLOCKED (6932L)\n+#define RST9512_STICKY_DDR4_PLL_UNLOCKED (6933L)\n+#define RST9512_STICKY_PCI_SYS_MMCM_UNLOCKED (6934L)\n+#define RST9512_STICKY_PTP_MMCM_UNLOCKED (6935L)\n+#define RST9512_STICKY_SYS_MMCM_UNLOCKED (6936L)\n+#define RST9512_STICKY_TSM_REF_MMCM_UNLOCKED (6937L)\n+#define RST9512_STICKY_TS_MMCM_UNLOCKED (6938L)\n+/* RST9513 */\n+/* RST9515 */\n+#define RST9515_CTRL (6939L)\n+#define RST9515_CTRL_PTP_MMCM_CLKSEL (6940L)\n+#define RST9515_CTRL_TS_CLKSEL (6941L)\n+#define RST9515_CTRL_TS_CLKSEL_OVERRIDE (6942L)\n+#define RST9515_CTRL_TS_CLKSEL_REF (6943L)\n+#define RST9515_POWER (6944L)\n+#define RST9515_POWER_PU_NSEB (6945L)\n+#define RST9515_POWER_PU_PHY (6946L)\n+#define RST9515_RST (6947L)\n+#define RST9515_RST_CORE_MMCM (6948L)\n+#define RST9515_RST_DDR4 (6949L)\n+#define RST9515_RST_MAC_RX (6950L)\n+#define RST9515_RST_PERIPH (6951L)\n+#define RST9515_RST_PHY (6952L)\n+#define RST9515_RST_PTP (6953L)\n+#define RST9515_RST_PTP_MMCM (6954L)\n+#define RST9515_RST_RPP (6955L)\n+#define RST9515_RST_SDC (6956L)\n+#define RST9515_RST_SYS (6957L)\n+#define RST9515_RST_SYS_MMCM (6958L)\n+#define RST9515_RST_TMC (6959L)\n+#define RST9515_RST_TS (6960L)\n+#define RST9515_RST_TSM_REF_MMCM (6961L)\n+#define RST9515_RST_TS_MMCM (6962L)\n+#define RST9515_STAT (6963L)\n+#define RST9515_STAT_CORE_MMCM_LOCKED (6964L)\n+#define RST9515_STAT_DDR4_MMCM_LOCKED (6965L)\n+#define RST9515_STAT_DDR4_PLL_LOCKED (6966L)\n+#define RST9515_STAT_PCI_SYS_MMCM_LOCKED (6967L)\n+#define RST9515_STAT_PTP_MMCM_LOCKED (6968L)\n+#define RST9515_STAT_SYS_MMCM_LOCKED (6969L)\n+#define RST9515_STAT_TSM_REF_MMCM_LOCKED (6970L)\n+#define RST9515_STAT_TS_MMCM_LOCKED (6971L)\n+#define RST9515_STICKY (6972L)\n+#define RST9515_STICKY_CORE_MMCM_UNLOCKED (6973L)\n+#define RST9515_STICKY_DDR4_MMCM_UNLOCKED (6974L)\n+#define RST9515_STICKY_DDR4_PLL_UNLOCKED (6975L)\n+#define RST9515_STICKY_PCI_SYS_MMCM_UNLOCKED (6976L)\n+#define RST9515_STICKY_PTP_MMCM_UNLOCKED (6977L)\n+#define RST9515_STICKY_SYS_MMCM_UNLOCKED (6978L)\n+#define RST9515_STICKY_TSM_REF_MMCM_UNLOCKED (6979L)\n+#define RST9515_STICKY_TS_MMCM_UNLOCKED (6980L)\n+/* RST9516 */\n+#define RST9516_CTRL (6981L)\n+#define RST9516_CTRL_PTP_MMCM_CLKSEL (6982L)\n+#define RST9516_CTRL_TS_CLKSEL (6983L)\n+#define RST9516_CTRL_TS_CLKSEL_OVERRIDE (6984L)\n+#define RST9516_CTRL_TS_CLKSEL_REF (6985L)\n+#define RST9516_POWER (6986L)\n+#define RST9516_POWER_PU_NSEB (6987L)\n+#define RST9516_POWER_PU_PHY (6988L)\n+#define RST9516_RST (6989L)\n+#define RST9516_RST_CORE_MMCM (6990L)\n+#define RST9516_RST_DDR4 (6991L)\n+#define RST9516_RST_MAC_RX (6992L)\n+#define RST9516_RST_PCS_RX (6993L)\n+#define RST9516_RST_PERIPH (6994L)\n+#define RST9516_RST_PHY (6995L)\n+#define RST9516_RST_PTP (6996L)\n+#define RST9516_RST_PTP_MMCM (6997L)\n+#define RST9516_RST_RPP (6998L)\n+#define RST9516_RST_SDC (6999L)\n+#define RST9516_RST_SERDES_RX (7000L)\n+#define RST9516_RST_SERDES_TX (7001L)\n+#define RST9516_RST_SYS (7002L)\n+#define RST9516_RST_SYS_MMCM (7003L)\n+#define RST9516_RST_TMC (7004L)\n+#define RST9516_RST_TS (7005L)\n+#define RST9516_RST_TSM_REF_MMCM (7006L)\n+#define RST9516_RST_TS_MMCM (7007L)\n+#define RST9516_STAT (7008L)\n+#define RST9516_STAT_CORE_MMCM_LOCKED (7009L)\n+#define RST9516_STAT_DDR4_MMCM_LOCKED (7010L)\n+#define RST9516_STAT_DDR4_PLL_LOCKED (7011L)\n+#define RST9516_STAT_PCI_SYS_MMCM_LOCKED (7012L)\n+#define RST9516_STAT_PTP_MMCM_LOCKED (7013L)\n+#define RST9516_STAT_SYS_MMCM_LOCKED (7014L)\n+#define RST9516_STAT_TSM_REF_MMCM_LOCKED (7015L)\n+#define RST9516_STAT_TS_MMCM_LOCKED (7016L)\n+#define RST9516_STICKY (7017L)\n+#define RST9516_STICKY_CORE_MMCM_UNLOCKED (7018L)\n+#define RST9516_STICKY_DDR4_MMCM_UNLOCKED (7019L)\n+#define RST9516_STICKY_DDR4_PLL_UNLOCKED (7020L)\n+#define RST9516_STICKY_PCI_SYS_MMCM_UNLOCKED (7021L)\n+#define RST9516_STICKY_PTP_MMCM_UNLOCKED (7022L)\n+#define RST9516_STICKY_SYS_MMCM_UNLOCKED (7023L)\n+#define RST9516_STICKY_TSM_REF_MMCM_UNLOCKED (7024L)\n+#define RST9516_STICKY_TS_MMCM_UNLOCKED (7025L)\n+/* RST9517 */\n+#define RST9517_CTRL (7026L)\n+#define RST9517_CTRL_PTP_MMCM_CLKSEL (7027L)\n+#define RST9517_CTRL_TS_CLKSEL (7028L)\n+#define RST9517_CTRL_TS_CLKSEL_OVERRIDE (7029L)\n+#define RST9517_RST (7030L)\n+#define RST9517_RST_DDR3 (7031L)\n+#define RST9517_RST_DDR3_IDLY_MMCM (7032L)\n+#define RST9517_RST_NSEB (7033L)\n+#define RST9517_RST_PERIPH (7034L)\n+#define RST9517_RST_PHY10G_QPLL (7035L)\n+#define RST9517_RST_PHY3S10G (7036L)\n+#define RST9517_RST_PHY3S_MMCM (7037L)\n+#define RST9517_RST_PTP (7038L)\n+#define RST9517_RST_PTP_MMCM (7039L)\n+#define RST9517_RST_RPP (7040L)\n+#define RST9517_RST_SDC (7041L)\n+#define RST9517_RST_SI5326 (7042L)\n+#define RST9517_RST_SYS (7043L)\n+#define RST9517_RST_TS (7044L)\n+#define RST9517_RST_TS_MMCM (7045L)\n+#define RST9517_RST_STAT (7046L)\n+#define RST9517_RST_STAT_PCS_RESET_BY_SERDES (7047L)\n+#define RST9517_STAT (7048L)\n+#define RST9517_STAT_DDR3_IDLY_MMCM_LOCKED (7049L)\n+#define RST9517_STAT_DDR3_MMCM_LOCKED (7050L)\n+#define RST9517_STAT_DDR3_PLL_LOCKED (7051L)\n+#define RST9517_STAT_PHY10G_QPLL_LOCK_0_1 (7052L)\n+#define RST9517_STAT_PHY10G_QPLL_LOCK_2_3 (7053L)\n+#define RST9517_STAT_PHY3S_MMCM_LOCKED (7054L)\n+#define RST9517_STAT_PTP_MMCM_LOCKED (7055L)\n+#define RST9517_STAT_SYNCE_MAIN_CLK_LOS (7056L)\n+#define RST9517_STAT_SYS_MMCM_LOCKED (7057L)\n+#define RST9517_STAT_TS_MMCM_LOCKED (7058L)\n+#define RST9517_STICKY (7059L)\n+#define RST9517_STICKY_DDR3_IDLY_MMCM_UNLOCKED (7060L)\n+#define RST9517_STICKY_DDR3_MMCM_UNLOCKED (7061L)\n+#define RST9517_STICKY_DDR3_PLL_UNLOCKED (7062L)\n+#define RST9517_STICKY_PHY10G_QPLL_UNLOCK_0_1 (7063L)\n+#define RST9517_STICKY_PHY10G_QPLL_UNLOCK_2_3 (7064L)\n+#define RST9517_STICKY_PHY3S_MMCM_UNLOCKED (7065L)\n+#define RST9517_STICKY_PTP_MMCM_UNLOCKED (7066L)\n+#define RST9517_STICKY_TS_MMCM_UNLOCKED (7067L)\n+/* RST9519 */\n+#define RST9519_CTRL (7068L)\n+#define RST9519_CTRL_PTP_MMCM_CLKSEL (7069L)\n+#define RST9519_CTRL_TS_CLKSEL (7070L)\n+#define RST9519_CTRL_TS_CLKSEL_OVERRIDE (7071L)\n+#define RST9519_RST (7072L)\n+#define RST9519_RST_DDR3 (7073L)\n+#define RST9519_RST_DDR3_IDLY_MMCM (7074L)\n+#define RST9519_RST_PERIPH (7075L)\n+#define RST9519_RST_PHY10G (7076L)\n+#define RST9519_RST_PHY10G_QPLL (7077L)\n+#define RST9519_RST_PTP (7078L)\n+#define RST9519_RST_PTP_MMCM (7079L)\n+#define RST9519_RST_RPP (7080L)\n+#define RST9519_RST_SDC (7081L)\n+#define RST9519_RST_SI5326 (7082L)\n+#define RST9519_RST_SYS (7083L)\n+#define RST9519_RST_TS (7084L)\n+#define RST9519_RST_TS_MMCM (7085L)\n+#define RST9519_RST_STAT (7086L)\n+#define RST9519_RST_STAT_PCS_RESET_BY_SERDES (7087L)\n+#define RST9519_STAT (7088L)\n+#define RST9519_STAT_DDR3_IDLY_MMCM_LOCKED (7089L)\n+#define RST9519_STAT_DDR3_MMCM_LOCKED (7090L)\n+#define RST9519_STAT_DDR3_PLL_LOCKED (7091L)\n+#define RST9519_STAT_PHY10G_QPLL_LOCK (7092L)\n+#define RST9519_STAT_PTP_MMCM_LOCKED (7093L)\n+#define RST9519_STAT_SYNCE_MAIN_CLK_LOS (7094L)\n+#define RST9519_STAT_SYS_MMCM_LOCKED (7095L)\n+#define RST9519_STAT_TS_MMCM_LOCKED (7096L)\n+#define RST9519_STICKY (7097L)\n+#define RST9519_STICKY_DDR3_IDLY_MMCM_UNLOCKED (7098L)\n+#define RST9519_STICKY_DDR3_MMCM_UNLOCKED (7099L)\n+#define RST9519_STICKY_DDR3_PLL_UNLOCKED (7100L)\n+#define RST9519_STICKY_PHY10G_QPLL_UNLOCK (7101L)\n+#define RST9519_STICKY_PTP_MMCM_UNLOCKED (7102L)\n+#define RST9519_STICKY_TS_MMCM_UNLOCKED (7103L)\n+/* RST9520 */\n+/* RST9521 */\n+#define RST9521_CTRL (7104L)\n+#define RST9521_CTRL_PTP_MMCM_CLKSEL (7105L)\n+#define RST9521_CTRL_TS_CLKSEL (7106L)\n+#define RST9521_CTRL_TS_CLKSEL_OVERRIDE (7107L)\n+#define RST9521_POWER (7108L)\n+#define RST9521_POWER_PU_NSEB (7109L)\n+#define RST9521_POWER_PU_PHY (7110L)\n+#define RST9521_RST (7111L)\n+#define RST9521_RST_CORE_MMCM (7112L)\n+#define RST9521_RST_DDR4 (7113L)\n+#define RST9521_RST_MAC_RX (7114L)\n+#define RST9521_RST_PERIPH (7115L)\n+#define RST9521_RST_PHY (7116L)\n+#define RST9521_RST_PTP (7117L)\n+#define RST9521_RST_PTP_MMCM (7118L)\n+#define RST9521_RST_RPP (7119L)\n+#define RST9521_RST_SDC (7120L)\n+#define RST9521_RST_SYS (7121L)\n+#define RST9521_RST_SYS_MMCM (7122L)\n+#define RST9521_RST_TMC (7123L)\n+#define RST9521_RST_TS (7124L)\n+#define RST9521_RST_TSM_REF_MMCM (7125L)\n+#define RST9521_RST_TS_MMCM (7126L)\n+#define RST9521_STAT (7127L)\n+#define RST9521_STAT_CORE_MMCM_LOCKED (7128L)\n+#define RST9521_STAT_DDR4_MMCM_LOCKED (7129L)\n+#define RST9521_STAT_DDR4_PLL_LOCKED (7130L)\n+#define RST9521_STAT_PTP_MMCM_LOCKED (7131L)\n+#define RST9521_STAT_SYS_MMCM_LOCKED (7132L)\n+#define RST9521_STAT_TS_MMCM_LOCKED (7133L)\n+#define RST9521_STICKY (7134L)\n+#define RST9521_STICKY_CORE_MMCM_UNLOCKED (7135L)\n+#define RST9521_STICKY_DDR4_MMCM_UNLOCKED (7136L)\n+#define RST9521_STICKY_DDR4_PLL_UNLOCKED (7137L)\n+#define RST9521_STICKY_PTP_MMCM_UNLOCKED (7138L)\n+#define RST9521_STICKY_SYS_MMCM_UNLOCKED (7139L)\n+#define RST9521_STICKY_TS_MMCM_UNLOCKED (7140L)\n+/* RST9522 */\n+#define RST9522_CTRL (7141L)\n+#define RST9522_CTRL_PTP_MMCM_CLKSEL (7142L)\n+#define RST9522_CTRL_TS_CLKSEL (7143L)\n+#define RST9522_CTRL_TS_CLKSEL_OVERRIDE (7144L)\n+#define RST9522_CTRL_TS_CLKSEL_REF (7145L)\n+#define RST9522_POWER (7146L)\n+#define RST9522_POWER_PU_NSEB (7147L)\n+#define RST9522_POWER_PU_PHY (7148L)\n+#define RST9522_RST (7149L)\n+#define RST9522_RST_CORE_MMCM (7150L)\n+#define RST9522_RST_DDR4 (7151L)\n+#define RST9522_RST_PERIPH (7152L)\n+#define RST9522_RST_PHY10G (7153L)\n+#define RST9522_RST_PHY10G_QPLL (7154L)\n+#define RST9522_RST_PTP (7155L)\n+#define RST9522_RST_PTP_MMCM (7156L)\n+#define RST9522_RST_RPP (7157L)\n+#define RST9522_RST_SDC (7158L)\n+#define RST9522_RST_SYS (7159L)\n+#define RST9522_RST_SYS_MMCM (7160L)\n+#define RST9522_RST_TS (7161L)\n+#define RST9522_RST_TSM_REF_MMCM (7162L)\n+#define RST9522_RST_TS_MMCM (7163L)\n+#define RST9522_STAT (7164L)\n+#define RST9522_STAT_CORE_MMCM_LOCKED (7165L)\n+#define RST9522_STAT_DDR4_MMCM_LOCKED (7166L)\n+#define RST9522_STAT_DDR4_PLL_LOCKED (7167L)\n+#define RST9522_STAT_PCI_SYS_MMCM_LOCKED (7168L)\n+#define RST9522_STAT_PHY10G_QPLL_LOCKED (7169L)\n+#define RST9522_STAT_PTP_MMCM_LOCKED (7170L)\n+#define RST9522_STAT_SYS_MMCM_LOCKED (7171L)\n+#define RST9522_STAT_TSM_REF_MMCM_LOCKED (7172L)\n+#define RST9522_STAT_TS_MMCM_LOCKED (7173L)\n+#define RST9522_STICKY (7174L)\n+#define RST9522_STICKY_CORE_MMCM_UNLOCKED (7175L)\n+#define RST9522_STICKY_DDR4_MMCM_UNLOCKED (7176L)\n+#define RST9522_STICKY_DDR4_PLL_UNLOCKED (7177L)\n+#define RST9522_STICKY_PCI_SYS_MMCM_UNLOCKED (7178L)\n+#define RST9522_STICKY_PHY10G_QPLL_UNLOCKED (7179L)\n+#define RST9522_STICKY_PTP_MMCM_UNLOCKED (7180L)\n+#define RST9522_STICKY_SYS_MMCM_UNLOCKED (7181L)\n+#define RST9522_STICKY_TSM_REF_MMCM_UNLOCKED (7182L)\n+#define RST9522_STICKY_TS_MMCM_UNLOCKED (7183L)\n+/* RST9523 */\n+/* RST9524 */\n+#define RST9524_CTRL (7184L)\n+#define RST9524_CTRL_PTP_MMCM_CLKSEL (7185L)\n+#define RST9524_CTRL_TS_CLKSEL (7186L)\n+#define RST9524_CTRL_TS_CLKSEL_OVERRIDE (7187L)\n+#define RST9524_POWER (7188L)\n+#define RST9524_POWER_PU_NSEB (7189L)\n+#define RST9524_POWER_PU_PHY (7190L)\n+#define RST9524_RST (7191L)\n+#define RST9524_RST_CORE_MMCM (7192L)\n+#define RST9524_RST_DDR4 (7193L)\n+#define RST9524_RST_MAC_RX (7194L)\n+#define RST9524_RST_PERIPH (7195L)\n+#define RST9524_RST_PHY (7196L)\n+#define RST9524_RST_PTP (7197L)\n+#define RST9524_RST_PTP_MMCM (7198L)\n+#define RST9524_RST_RPP (7199L)\n+#define RST9524_RST_SDC (7200L)\n+#define RST9524_RST_SYS (7201L)\n+#define RST9524_RST_SYS_MMCM (7202L)\n+#define RST9524_RST_TMC (7203L)\n+#define RST9524_RST_TS (7204L)\n+#define RST9524_RST_TS_MMCM (7205L)\n+#define RST9524_STAT (7206L)\n+#define RST9524_STAT_CORE_MMCM_LOCKED (7207L)\n+#define RST9524_STAT_DDR4_MMCM_LOCKED (7208L)\n+#define RST9524_STAT_DDR4_PLL_LOCKED (7209L)\n+#define RST9524_STAT_PTP_MMCM_LOCKED (7210L)\n+#define RST9524_STAT_SYS_MMCM_LOCKED (7211L)\n+#define RST9524_STAT_TS_MMCM_LOCKED (7212L)\n+#define RST9524_STICKY (7213L)\n+#define RST9524_STICKY_CORE_MMCM_UNLOCKED (7214L)\n+#define RST9524_STICKY_DDR4_MMCM_UNLOCKED (7215L)\n+#define RST9524_STICKY_DDR4_PLL_UNLOCKED (7216L)\n+#define RST9524_STICKY_PTP_MMCM_UNLOCKED (7217L)\n+#define RST9524_STICKY_SYS_MMCM_UNLOCKED (7218L)\n+#define RST9524_STICKY_TS_MMCM_UNLOCKED (7219L)\n+/* RST9525 */\n+#define RST9525_CTRL (7220L)\n+#define RST9525_CTRL_PTP_MMCM_CLKSEL (7221L)\n+#define RST9525_CTRL_TS_CLKSEL (7222L)\n+#define RST9525_CTRL_TS_CLKSEL_OVERRIDE (7223L)\n+#define RST9525_CTRL_TS_CLKSEL_REF (7224L)\n+#define RST9525_POWER (7225L)\n+#define RST9525_POWER_PU_NSEB (7226L)\n+#define RST9525_POWER_PU_PHY (7227L)\n+#define RST9525_RST (7228L)\n+#define RST9525_RST_CORE_MMCM (7229L)\n+#define RST9525_RST_DDR4 (7230L)\n+#define RST9525_RST_MAC_RX (7231L)\n+#define RST9525_RST_MAC_TX (7232L)\n+#define RST9525_RST_PCS_RX (7233L)\n+#define RST9525_RST_PERIPH (7234L)\n+#define RST9525_RST_PHY (7235L)\n+#define RST9525_RST_PTP (7236L)\n+#define RST9525_RST_PTP_MMCM (7237L)\n+#define RST9525_RST_RPP (7238L)\n+#define RST9525_RST_SDC (7239L)\n+#define RST9525_RST_SERDES_RX (7240L)\n+#define RST9525_RST_SERDES_RX_DATAPATH (7241L)\n+#define RST9525_RST_SERDES_TX (7242L)\n+#define RST9525_RST_SYS (7243L)\n+#define RST9525_RST_SYS_MMCM (7244L)\n+#define RST9525_RST_TS (7245L)\n+#define RST9525_RST_TSM_REF_MMCM (7246L)\n+#define RST9525_RST_TS_MMCM (7247L)\n+#define RST9525_STAT (7248L)\n+#define RST9525_STAT_CORE_MMCM_LOCKED (7249L)\n+#define RST9525_STAT_DDR4_MMCM_LOCKED (7250L)\n+#define RST9525_STAT_DDR4_PLL_LOCKED (7251L)\n+#define RST9525_STAT_PCI_SYS_MMCM_LOCKED (7252L)\n+#define RST9525_STAT_PTP_MMCM_LOCKED (7253L)\n+#define RST9525_STAT_SYS_MMCM_LOCKED (7254L)\n+#define RST9525_STAT_TSM_REF_MMCM_LOCKED (7255L)\n+#define RST9525_STAT_TS_MMCM_LOCKED (7256L)\n+#define RST9525_STICKY (7257L)\n+#define RST9525_STICKY_CORE_MMCM_UNLOCKED (7258L)\n+#define RST9525_STICKY_DDR4_MMCM_UNLOCKED (7259L)\n+#define RST9525_STICKY_DDR4_PLL_UNLOCKED (7260L)\n+#define RST9525_STICKY_PCI_SYS_MMCM_UNLOCKED (7261L)\n+#define RST9525_STICKY_PTP_MMCM_UNLOCKED (7262L)\n+#define RST9525_STICKY_SYS_MMCM_UNLOCKED (7263L)\n+#define RST9525_STICKY_TSM_REF_MMCM_UNLOCKED (7264L)\n+#define RST9525_STICKY_TS_MMCM_UNLOCKED (7265L)\n+/* RST9526 */\n+#define RST9526_CTRL (7266L)\n+#define RST9526_CTRL_PTP_MMCM_CLKSEL (7267L)\n+#define RST9526_CTRL_TS_CLKSEL (7268L)\n+#define RST9526_CTRL_TS_CLKSEL_OVERRIDE (7269L)\n+#define RST9526_POWER (7270L)\n+#define RST9526_POWER_PU_NSEB (7271L)\n+#define RST9526_POWER_PU_PHY (7272L)\n+#define RST9526_RST (7273L)\n+#define RST9526_RST_CORE_MMCM (7274L)\n+#define RST9526_RST_DDR4 (7275L)\n+#define RST9526_RST_MAC_RX (7276L)\n+#define RST9526_RST_MAC_TX (7277L)\n+#define RST9526_RST_PCS_RX (7278L)\n+#define RST9526_RST_PERIPH (7279L)\n+#define RST9526_RST_PHY (7280L)\n+#define RST9526_RST_PTP (7281L)\n+#define RST9526_RST_PTP_MMCM (7282L)\n+#define RST9526_RST_RPP (7283L)\n+#define RST9526_RST_SDC (7284L)\n+#define RST9526_RST_SERDES_RX (7285L)\n+#define RST9526_RST_SERDES_RX_DATAPATH (7286L)\n+#define RST9526_RST_SERDES_TX (7287L)\n+#define RST9526_RST_SYS (7288L)\n+#define RST9526_RST_SYS_MMCM (7289L)\n+#define RST9526_RST_TMC (7290L)\n+#define RST9526_RST_TS (7291L)\n+#define RST9526_RST_TS_MMCM (7292L)\n+#define RST9526_STAT (7293L)\n+#define RST9526_STAT_CORE_MMCM_LOCKED (7294L)\n+#define RST9526_STAT_DDR4_MMCM_LOCKED (7295L)\n+#define RST9526_STAT_DDR4_PLL_LOCKED (7296L)\n+#define RST9526_STAT_PTP_MMCM_LOCKED (7297L)\n+#define RST9526_STAT_SYS_MMCM_LOCKED (7298L)\n+#define RST9526_STAT_TS_MMCM_LOCKED (7299L)\n+#define RST9526_STICKY (7300L)\n+#define RST9526_STICKY_CORE_MMCM_UNLOCKED (7301L)\n+#define RST9526_STICKY_DDR4_MMCM_UNLOCKED (7302L)\n+#define RST9526_STICKY_DDR4_PLL_UNLOCKED (7303L)\n+#define RST9526_STICKY_PTP_MMCM_UNLOCKED (7304L)\n+#define RST9526_STICKY_SYS_MMCM_UNLOCKED (7305L)\n+#define RST9526_STICKY_TS_MMCM_UNLOCKED (7306L)\n+/* RST9527 */\n+#define RST9527_CTRL (7307L)\n+#define RST9527_CTRL_PTP_MMCM_CLKSEL (7308L)\n+#define RST9527_CTRL_TS_CLKSEL (7309L)\n+#define RST9527_CTRL_TS_CLKSEL_OVERRIDE (7310L)\n+#define RST9527_POWER (7311L)\n+#define RST9527_POWER_PU_NSEB (7312L)\n+#define RST9527_POWER_PU_PHY (7313L)\n+#define RST9527_RST (7314L)\n+#define RST9527_RST_CORE_MMCM (7315L)\n+#define RST9527_RST_DDR4 (7316L)\n+#define RST9527_RST_MAC_RX (7317L)\n+#define RST9527_RST_MAC_TX (7318L)\n+#define RST9527_RST_PCS_RX (7319L)\n+#define RST9527_RST_PERIPH (7320L)\n+#define RST9527_RST_PHY (7321L)\n+#define RST9527_RST_PTP (7322L)\n+#define RST9527_RST_PTP_MMCM (7323L)\n+#define RST9527_RST_RPP (7324L)\n+#define RST9527_RST_SDC (7325L)\n+#define RST9527_RST_SERDES_RX (7326L)\n+#define RST9527_RST_SERDES_RX_DATAPATH (7327L)\n+#define RST9527_RST_SERDES_TX (7328L)\n+#define RST9527_RST_SYS (7329L)\n+#define RST9527_RST_SYS_MMCM (7330L)\n+#define RST9527_RST_TMC (7331L)\n+#define RST9527_RST_TS (7332L)\n+#define RST9527_RST_TS_MMCM (7333L)\n+#define RST9527_STAT (7334L)\n+#define RST9527_STAT_CORE_MMCM_LOCKED (7335L)\n+#define RST9527_STAT_DDR4_MMCM_LOCKED (7336L)\n+#define RST9527_STAT_DDR4_PLL_LOCKED (7337L)\n+#define RST9527_STAT_PTP_MMCM_LOCKED (7338L)\n+#define RST9527_STAT_SYS_MMCM_LOCKED (7339L)\n+#define RST9527_STAT_TS_MMCM_LOCKED (7340L)\n+#define RST9527_STICKY (7341L)\n+#define RST9527_STICKY_CORE_MMCM_UNLOCKED (7342L)\n+#define RST9527_STICKY_DDR4_MMCM_UNLOCKED (7343L)\n+#define RST9527_STICKY_DDR4_PLL_UNLOCKED (7344L)\n+#define RST9527_STICKY_PTP_MMCM_UNLOCKED (7345L)\n+#define RST9527_STICKY_SYS_MMCM_UNLOCKED (7346L)\n+#define RST9527_STICKY_TS_MMCM_UNLOCKED (7347L)\n+/* RST9528 */\n+/* RST9529 */\n+#define RST9529_CTRL (7348L)\n+#define RST9529_CTRL_PTP_MMCM_CLKSEL (7349L)\n+#define RST9529_CTRL_TS_CLKSEL (7350L)\n+#define RST9529_CTRL_TS_CLKSEL_OVERRIDE (7351L)\n+#define RST9529_CTRL_TS_CLKSEL_REF (7352L)\n+#define RST9529_POWER (7353L)\n+#define RST9529_POWER_PU_NSEB (7354L)\n+#define RST9529_POWER_PU_PHY (7355L)\n+#define RST9529_RST (7356L)\n+#define RST9529_RST_CORE_MMCM (7357L)\n+#define RST9529_RST_DDR4 (7358L)\n+#define RST9529_RST_PERIPH (7359L)\n+#define RST9529_RST_PHY (7360L)\n+#define RST9529_RST_PTP (7361L)\n+#define RST9529_RST_PTP_MMCM (7362L)\n+#define RST9529_RST_RPP (7363L)\n+#define RST9529_RST_SDC (7364L)\n+#define RST9529_RST_SYS (7365L)\n+#define RST9529_RST_SYS_MMCM (7366L)\n+#define RST9529_RST_TS (7367L)\n+#define RST9529_RST_TSM_REF_MMCM (7368L)\n+#define RST9529_RST_TS_MMCM (7369L)\n+#define RST9529_STAT (7370L)\n+#define RST9529_STAT_CORE_MMCM_LOCKED (7371L)\n+#define RST9529_STAT_DDR4_MMCM_LOCKED (7372L)\n+#define RST9529_STAT_DDR4_PLL_LOCKED (7373L)\n+#define RST9529_STAT_PCI_SYS_MMCM_LOCKED (7374L)\n+#define RST9529_STAT_PTP_MMCM_LOCKED (7375L)\n+#define RST9529_STAT_SYS_MMCM_LOCKED (7376L)\n+#define RST9529_STAT_TSM_REF_MMCM_LOCKED (7377L)\n+#define RST9529_STAT_TS_MMCM_LOCKED (7378L)\n+#define RST9529_STICKY (7379L)\n+#define RST9529_STICKY_CORE_MMCM_UNLOCKED (7380L)\n+#define RST9529_STICKY_DDR4_MMCM_UNLOCKED (7381L)\n+#define RST9529_STICKY_DDR4_PLL_UNLOCKED (7382L)\n+#define RST9529_STICKY_PCI_SYS_MMCM_UNLOCKED (7383L)\n+#define RST9529_STICKY_PTP_MMCM_UNLOCKED (7384L)\n+#define RST9529_STICKY_SYS_MMCM_UNLOCKED (7385L)\n+#define RST9529_STICKY_TSM_REF_MMCM_UNLOCKED (7386L)\n+#define RST9529_STICKY_TS_MMCM_UNLOCKED (7387L)\n+/* RST9530 */\n+#define RST9530_CTRL (7388L)\n+#define RST9530_CTRL_PTP_MMCM_CLKSEL (7389L)\n+#define RST9530_CTRL_TS_CLKSEL (7390L)\n+#define RST9530_CTRL_TS_CLKSEL_OVERRIDE (7391L)\n+#define RST9530_CTRL_TS_CLKSEL_REF (7392L)\n+#define RST9530_POWER (7393L)\n+#define RST9530_POWER_PU_NSEB (7394L)\n+#define RST9530_POWER_PU_PHY (7395L)\n+#define RST9530_RST (7396L)\n+#define RST9530_RST_CORE_MMCM (7397L)\n+#define RST9530_RST_DDR4 (7398L)\n+#define RST9530_RST_NFV_OVS (7399L)\n+#define RST9530_RST_PERIPH (7400L)\n+#define RST9530_RST_PHY (7401L)\n+#define RST9530_RST_PTP (7402L)\n+#define RST9530_RST_PTP_MMCM (7403L)\n+#define RST9530_RST_RPP (7404L)\n+#define RST9530_RST_SDC (7405L)\n+#define RST9530_RST_SYS (7406L)\n+#define RST9530_RST_SYS_MMCM (7407L)\n+#define RST9530_RST_TMC (7408L)\n+#define RST9530_RST_TS (7409L)\n+#define RST9530_RST_TSM_REF_MMCM (7410L)\n+#define RST9530_RST_TS_MMCM (7411L)\n+#define RST9530_STAT (7412L)\n+#define RST9530_STAT_CORE_MMCM_LOCKED (7413L)\n+#define RST9530_STAT_DDR4_MMCM_LOCKED (7414L)\n+#define RST9530_STAT_DDR4_PLL_LOCKED (7415L)\n+#define RST9530_STAT_PTP_MMCM_LOCKED (7416L)\n+#define RST9530_STAT_SYS_MMCM_LOCKED (7417L)\n+#define RST9530_STAT_TSM_REF_MMCM_LOCKED (7418L)\n+#define RST9530_STAT_TS_MMCM_LOCKED (7419L)\n+#define RST9530_STICKY (7420L)\n+#define RST9530_STICKY_CORE_MMCM_UNLOCKED (7421L)\n+#define RST9530_STICKY_DDR4_MMCM_UNLOCKED (7422L)\n+#define RST9530_STICKY_DDR4_PLL_UNLOCKED (7423L)\n+#define RST9530_STICKY_PCI_SYS_MMCM_UNLOCKED (7424L)\n+#define RST9530_STICKY_PTP_MMCM_UNLOCKED (7425L)\n+#define RST9530_STICKY_SYS_MMCM_UNLOCKED (7426L)\n+#define RST9530_STICKY_TSM_REF_MMCM_UNLOCKED (7427L)\n+#define RST9530_STICKY_TS_MMCM_UNLOCKED (7428L)\n+/* RST9531 */\n+#define RST9531_CTRL (7429L)\n+#define RST9531_CTRL_PTP_MMCM_CLKSEL (7430L)\n+#define RST9531_CTRL_TS_CLKSEL (7431L)\n+#define RST9531_CTRL_TS_CLKSEL_OVERRIDE (7432L)\n+#define RST9531_CTRL_TS_CLKSEL_REF (7433L)\n+#define RST9531_POWER (7434L)\n+#define RST9531_POWER_PU_NSEB (7435L)\n+#define RST9531_POWER_PU_PHY (7436L)\n+#define RST9531_RST (7437L)\n+#define RST9531_RST_CORE_MMCM (7438L)\n+#define RST9531_RST_DDR4 (7439L)\n+#define RST9531_RST_PERIPH (7440L)\n+#define RST9531_RST_PHY (7441L)\n+#define RST9531_RST_PTP (7442L)\n+#define RST9531_RST_PTP_MMCM (7443L)\n+#define RST9531_RST_RPP (7444L)\n+#define RST9531_RST_SDC (7445L)\n+#define RST9531_RST_SYS (7446L)\n+#define RST9531_RST_SYS_MMCM (7447L)\n+#define RST9531_RST_TS (7448L)\n+#define RST9531_RST_TSM_REF_MMCM (7449L)\n+#define RST9531_RST_TS_MMCM (7450L)\n+#define RST9531_STAT (7451L)\n+#define RST9531_STAT_CORE_MMCM_LOCKED (7452L)\n+#define RST9531_STAT_DDR4_MMCM_LOCKED (7453L)\n+#define RST9531_STAT_DDR4_PLL_LOCKED (7454L)\n+#define RST9531_STAT_PCI_SYS_MMCM_LOCKED (7455L)\n+#define RST9531_STAT_PTP_MMCM_LOCKED (7456L)\n+#define RST9531_STAT_SYS_MMCM_LOCKED (7457L)\n+#define RST9531_STAT_TSM_REF_MMCM_LOCKED (7458L)\n+#define RST9531_STAT_TS_MMCM_LOCKED (7459L)\n+#define RST9531_STICKY (7460L)\n+#define RST9531_STICKY_CORE_MMCM_UNLOCKED (7461L)\n+#define RST9531_STICKY_DDR4_MMCM_UNLOCKED (7462L)\n+#define RST9531_STICKY_DDR4_PLL_UNLOCKED (7463L)\n+#define RST9531_STICKY_PCI_SYS_MMCM_UNLOCKED (7464L)\n+#define RST9531_STICKY_PTP_MMCM_UNLOCKED (7465L)\n+#define RST9531_STICKY_SYS_MMCM_UNLOCKED (7466L)\n+#define RST9531_STICKY_TSM_REF_MMCM_UNLOCKED (7467L)\n+#define RST9531_STICKY_TS_MMCM_UNLOCKED (7468L)\n+/* RST9532 */\n+#define RST9532_CTRL (7469L)\n+#define RST9532_CTRL_PTP_MMCM_CLKSEL (7470L)\n+#define RST9532_CTRL_TS_CLKSEL (7471L)\n+#define RST9532_CTRL_TS_CLKSEL_OVERRIDE (7472L)\n+#define RST9532_POWER (7473L)\n+#define RST9532_POWER_PU_NSEB (7474L)\n+#define RST9532_POWER_PU_PHY (7475L)\n+#define RST9532_RST (7476L)\n+#define RST9532_RST_CORE_MMCM (7477L)\n+#define RST9532_RST_DDR4 (7478L)\n+#define RST9532_RST_PERIPH (7479L)\n+#define RST9532_RST_PHY (7480L)\n+#define RST9532_RST_PTP (7481L)\n+#define RST9532_RST_PTP_MMCM (7482L)\n+#define RST9532_RST_RPP (7483L)\n+#define RST9532_RST_SDC (7484L)\n+#define RST9532_RST_SYS (7485L)\n+#define RST9532_RST_SYS_MMCM (7486L)\n+#define RST9532_RST_TMC (7487L)\n+#define RST9532_RST_TS (7488L)\n+#define RST9532_RST_TS_MMCM (7489L)\n+#define RST9532_STAT (7490L)\n+#define RST9532_STAT_CORE_MMCM_LOCKED (7491L)\n+#define RST9532_STAT_DDR4_MMCM_LOCKED (7492L)\n+#define RST9532_STAT_DDR4_PLL_LOCKED (7493L)\n+#define RST9532_STAT_PTP_MMCM_LOCKED (7494L)\n+#define RST9532_STAT_SYS_MMCM_LOCKED (7495L)\n+#define RST9532_STAT_TS_MMCM_LOCKED (7496L)\n+#define RST9532_STICKY (7497L)\n+#define RST9532_STICKY_CORE_MMCM_UNLOCKED (7498L)\n+#define RST9532_STICKY_DDR4_MMCM_UNLOCKED (7499L)\n+#define RST9532_STICKY_DDR4_PLL_UNLOCKED (7500L)\n+#define RST9532_STICKY_PTP_MMCM_UNLOCKED (7501L)\n+#define RST9532_STICKY_SYS_MMCM_UNLOCKED (7502L)\n+#define RST9532_STICKY_TS_MMCM_UNLOCKED (7503L)\n+/* RST9533 */\n+#define RST9533_CTRL (7504L)\n+#define RST9533_CTRL_PTP_MMCM_CLKSEL (7505L)\n+#define RST9533_CTRL_TS_CLKSEL (7506L)\n+#define RST9533_CTRL_TS_CLKSEL_OVERRIDE (7507L)\n+#define RST9533_POWER (7508L)\n+#define RST9533_POWER_PU_NSEB (7509L)\n+#define RST9533_POWER_PU_PHY (7510L)\n+#define RST9533_RST (7511L)\n+#define RST9533_RST_CORE_MMCM (7512L)\n+#define RST9533_RST_DDR4 (7513L)\n+#define RST9533_RST_PERIPH (7514L)\n+#define RST9533_RST_PHY (7515L)\n+#define RST9533_RST_PTP (7516L)\n+#define RST9533_RST_PTP_MMCM (7517L)\n+#define RST9533_RST_RPP (7518L)\n+#define RST9533_RST_SDC (7519L)\n+#define RST9533_RST_SYS (7520L)\n+#define RST9533_RST_SYS_MMCM (7521L)\n+#define RST9533_RST_TMC (7522L)\n+#define RST9533_RST_TS (7523L)\n+#define RST9533_RST_TS_MMCM (7524L)\n+#define RST9533_STAT (7525L)\n+#define RST9533_STAT_CORE_MMCM_LOCKED (7526L)\n+#define RST9533_STAT_DDR4_MMCM_LOCKED (7527L)\n+#define RST9533_STAT_DDR4_PLL_LOCKED (7528L)\n+#define RST9533_STAT_PTP_MMCM_LOCKED (7529L)\n+#define RST9533_STAT_SYS_MMCM_LOCKED (7530L)\n+#define RST9533_STAT_TS_MMCM_LOCKED (7531L)\n+#define RST9533_STICKY (7532L)\n+#define RST9533_STICKY_CORE_MMCM_UNLOCKED (7533L)\n+#define RST9533_STICKY_DDR4_MMCM_UNLOCKED (7534L)\n+#define RST9533_STICKY_DDR4_PLL_UNLOCKED (7535L)\n+#define RST9533_STICKY_PTP_MMCM_UNLOCKED (7536L)\n+#define RST9533_STICKY_SYS_MMCM_UNLOCKED (7537L)\n+#define RST9533_STICKY_TS_MMCM_UNLOCKED (7538L)\n+/* RST9534 */\n+#define RST9534_CTRL (7539L)\n+#define RST9534_CTRL_PTP_MMCM_CLKSEL (7540L)\n+#define RST9534_CTRL_TS_CLKSEL (7541L)\n+#define RST9534_CTRL_TS_CLKSEL_OVERRIDE (7542L)\n+#define RST9534_POWER (7543L)\n+#define RST9534_POWER_PU_NSEB (7544L)\n+#define RST9534_POWER_PU_PHY (7545L)\n+#define RST9534_RST (7546L)\n+#define RST9534_RST_CORE_MMCM (7547L)\n+#define RST9534_RST_DDR4 (7548L)\n+#define RST9534_RST_PERIPH (7549L)\n+#define RST9534_RST_PHY (7550L)\n+#define RST9534_RST_PTP (7551L)\n+#define RST9534_RST_PTP_MMCM (7552L)\n+#define RST9534_RST_RPP (7553L)\n+#define RST9534_RST_SDC (7554L)\n+#define RST9534_RST_SYS (7555L)\n+#define RST9534_RST_SYS_MMCM (7556L)\n+#define RST9534_RST_TMC (7557L)\n+#define RST9534_RST_TS (7558L)\n+#define RST9534_RST_TS_MMCM (7559L)\n+#define RST9534_STAT (7560L)\n+#define RST9534_STAT_CORE_MMCM_LOCKED (7561L)\n+#define RST9534_STAT_DDR4_MMCM_LOCKED (7562L)\n+#define RST9534_STAT_DDR4_PLL_LOCKED (7563L)\n+#define RST9534_STAT_PTP_MMCM_LOCKED (7564L)\n+#define RST9534_STAT_SYS_MMCM_LOCKED (7565L)\n+#define RST9534_STAT_TS_MMCM_LOCKED (7566L)\n+#define RST9534_STICKY (7567L)\n+#define RST9534_STICKY_CORE_MMCM_UNLOCKED (7568L)\n+#define RST9534_STICKY_DDR4_MMCM_UNLOCKED (7569L)\n+#define RST9534_STICKY_DDR4_PLL_UNLOCKED (7570L)\n+#define RST9534_STICKY_PTP_MMCM_UNLOCKED (7571L)\n+#define RST9534_STICKY_SYS_MMCM_UNLOCKED (7572L)\n+#define RST9534_STICKY_TS_MMCM_UNLOCKED (7573L)\n+/* RST9535 */\n+#define RST9535_CTRL (7574L)\n+#define RST9535_CTRL_PTP_MMCM_CLKSEL (7575L)\n+#define RST9535_CTRL_TS_CLKSEL (7576L)\n+#define RST9535_CTRL_TS_CLKSEL_OVERRIDE (7577L)\n+#define RST9535_POWER (7578L)\n+#define RST9535_POWER_PU_NSEB (7579L)\n+#define RST9535_POWER_PU_PHY (7580L)\n+#define RST9535_RST (7581L)\n+#define RST9535_RST_CORE_MMCM (7582L)\n+#define RST9535_RST_DDR4 (7583L)\n+#define RST9535_RST_MAC_RX (7584L)\n+#define RST9535_RST_MAC_TX (7585L)\n+#define RST9535_RST_PCS_RX (7586L)\n+#define RST9535_RST_PERIPH (7587L)\n+#define RST9535_RST_PHY (7588L)\n+#define RST9535_RST_PTP (7589L)\n+#define RST9535_RST_PTP_MMCM (7590L)\n+#define RST9535_RST_RPP (7591L)\n+#define RST9535_RST_SDC (7592L)\n+#define RST9535_RST_SERDES_RX (7593L)\n+#define RST9535_RST_SERDES_RX_DATAPATH (7594L)\n+#define RST9535_RST_SERDES_TX (7595L)\n+#define RST9535_RST_SYS (7596L)\n+#define RST9535_RST_SYS_MMCM (7597L)\n+#define RST9535_RST_TMC (7598L)\n+#define RST9535_RST_TS (7599L)\n+#define RST9535_RST_TS_MMCM (7600L)\n+#define RST9535_STAT (7601L)\n+#define RST9535_STAT_CORE_MMCM_LOCKED (7602L)\n+#define RST9535_STAT_DDR4_MMCM_LOCKED (7603L)\n+#define RST9535_STAT_DDR4_PLL_LOCKED (7604L)\n+#define RST9535_STAT_PTP_MMCM_LOCKED (7605L)\n+#define RST9535_STAT_SYS_MMCM_LOCKED (7606L)\n+#define RST9535_STAT_TS_MMCM_LOCKED (7607L)\n+#define RST9535_STICKY (7608L)\n+#define RST9535_STICKY_CORE_MMCM_UNLOCKED (7609L)\n+#define RST9535_STICKY_DDR4_MMCM_UNLOCKED (7610L)\n+#define RST9535_STICKY_DDR4_PLL_UNLOCKED (7611L)\n+#define RST9535_STICKY_PTP_MMCM_UNLOCKED (7612L)\n+#define RST9535_STICKY_SYS_MMCM_UNLOCKED (7613L)\n+#define RST9535_STICKY_TS_MMCM_UNLOCKED (7614L)\n+/* RST9536 */\n+#define RST9536_CTRL (7615L)\n+#define RST9536_CTRL_PTP_MMCM_CLKSEL (7616L)\n+#define RST9536_CTRL_TS_CLKSEL (7617L)\n+#define RST9536_CTRL_TS_CLKSEL_OVERRIDE (7618L)\n+#define RST9536_POWER (7619L)\n+#define RST9536_POWER_PU_NSEB (7620L)\n+#define RST9536_POWER_PU_PHY (7621L)\n+#define RST9536_RST (7622L)\n+#define RST9536_RST_CORE_MMCM (7623L)\n+#define RST9536_RST_DDR4 (7624L)\n+#define RST9536_RST_MAC_RX (7625L)\n+#define RST9536_RST_PERIPH (7626L)\n+#define RST9536_RST_PHY (7627L)\n+#define RST9536_RST_PTP (7628L)\n+#define RST9536_RST_PTP_MMCM (7629L)\n+#define RST9536_RST_RPP (7630L)\n+#define RST9536_RST_SDC (7631L)\n+#define RST9536_RST_SYS (7632L)\n+#define RST9536_RST_SYS_MMCM (7633L)\n+#define RST9536_RST_TMC (7634L)\n+#define RST9536_RST_TS (7635L)\n+#define RST9536_RST_TS_MMCM (7636L)\n+#define RST9536_STAT (7637L)\n+#define RST9536_STAT_CORE_MMCM_LOCKED (7638L)\n+#define RST9536_STAT_DDR4_MMCM_LOCKED (7639L)\n+#define RST9536_STAT_DDR4_PLL_LOCKED (7640L)\n+#define RST9536_STAT_PTP_MMCM_LOCKED (7641L)\n+#define RST9536_STAT_SYS_MMCM_LOCKED (7642L)\n+#define RST9536_STAT_TS_MMCM_LOCKED (7643L)\n+#define RST9536_STICKY (7644L)\n+#define RST9536_STICKY_CORE_MMCM_UNLOCKED (7645L)\n+#define RST9536_STICKY_DDR4_MMCM_UNLOCKED (7646L)\n+#define RST9536_STICKY_DDR4_PLL_UNLOCKED (7647L)\n+#define RST9536_STICKY_PTP_MMCM_UNLOCKED (7648L)\n+#define RST9536_STICKY_SYS_MMCM_UNLOCKED (7649L)\n+#define RST9536_STICKY_TS_MMCM_UNLOCKED (7650L)\n+/* RST9537 */\n+#define RST9537_CTRL (7651L)\n+#define RST9537_CTRL_PTP_MMCM_CLKSEL (7652L)\n+#define RST9537_CTRL_TS_CLKSEL (7653L)\n+#define RST9537_CTRL_TS_CLKSEL_OVERRIDE (7654L)\n+#define RST9537_RST (7655L)\n+#define RST9537_RST_DDR3 (7656L)\n+#define RST9537_RST_DDR3_IDLY_MMCM (7657L)\n+#define RST9537_RST_NSEB (7658L)\n+#define RST9537_RST_PERIPH (7659L)\n+#define RST9537_RST_PHY10G_QPLL (7660L)\n+#define RST9537_RST_PHY3S10G (7661L)\n+#define RST9537_RST_PHY3S_MMCM (7662L)\n+#define RST9537_RST_PTP (7663L)\n+#define RST9537_RST_PTP_MMCM (7664L)\n+#define RST9537_RST_RPP (7665L)\n+#define RST9537_RST_SDC (7666L)\n+#define RST9537_RST_SI5326 (7667L)\n+#define RST9537_RST_SYS (7668L)\n+#define RST9537_RST_TS (7669L)\n+#define RST9537_RST_TS_MMCM (7670L)\n+#define RST9537_RST_STAT (7671L)\n+#define RST9537_RST_STAT_PCS_RESET_BY_SERDES (7672L)\n+#define RST9537_STAT (7673L)\n+#define RST9537_STAT_DDR3_IDLY_MMCM_LOCKED (7674L)\n+#define RST9537_STAT_DDR3_MMCM_LOCKED (7675L)\n+#define RST9537_STAT_DDR3_PLL_LOCKED (7676L)\n+#define RST9537_STAT_PHY10G_QPLL_LOCK_0_1 (7677L)\n+#define RST9537_STAT_PHY10G_QPLL_LOCK_2_3 (7678L)\n+#define RST9537_STAT_PHY3S_MMCM_LOCKED (7679L)\n+#define RST9537_STAT_PTP_MMCM_LOCKED (7680L)\n+#define RST9537_STAT_SYNCE_MAIN_CLK_LOS (7681L)\n+#define RST9537_STAT_SYS_MMCM_LOCKED (7682L)\n+#define RST9537_STAT_TS_MMCM_LOCKED (7683L)\n+#define RST9537_STICKY (7684L)\n+#define RST9537_STICKY_DDR3_IDLY_MMCM_UNLOCKED (7685L)\n+#define RST9537_STICKY_DDR3_MMCM_UNLOCKED (7686L)\n+#define RST9537_STICKY_DDR3_PLL_UNLOCKED (7687L)\n+#define RST9537_STICKY_PHY10G_QPLL_UNLOCK_0_1 (7688L)\n+#define RST9537_STICKY_PHY10G_QPLL_UNLOCK_2_3 (7689L)\n+#define RST9537_STICKY_PHY3S_MMCM_UNLOCKED (7690L)\n+#define RST9537_STICKY_PTP_MMCM_UNLOCKED (7691L)\n+#define RST9537_STICKY_TS_MMCM_UNLOCKED (7692L)\n+/* RST9538 */\n+#define RST9538_CTRL (7693L)\n+#define RST9538_CTRL_PTP_MMCM_CLKSEL (7694L)\n+#define RST9538_CTRL_TS_CLKSEL (7695L)\n+#define RST9538_CTRL_TS_CLKSEL_OVERRIDE (7696L)\n+#define RST9538_RST (7697L)\n+#define RST9538_RST_DDR3 (7698L)\n+#define RST9538_RST_DDR3_IDLY_MMCM (7699L)\n+#define RST9538_RST_NSEB (7700L)\n+#define RST9538_RST_PERIPH (7701L)\n+#define RST9538_RST_PHY10G_QPLL (7702L)\n+#define RST9538_RST_PHY3S10G (7703L)\n+#define RST9538_RST_PHY3S_MMCM (7704L)\n+#define RST9538_RST_PTP (7705L)\n+#define RST9538_RST_PTP_MMCM (7706L)\n+#define RST9538_RST_RPP (7707L)\n+#define RST9538_RST_SDC (7708L)\n+#define RST9538_RST_SI5326 (7709L)\n+#define RST9538_RST_SYS (7710L)\n+#define RST9538_RST_TS (7711L)\n+#define RST9538_RST_TS_MMCM (7712L)\n+#define RST9538_RST_STAT (7713L)\n+#define RST9538_RST_STAT_PCS_RESET_BY_SERDES (7714L)\n+#define RST9538_STAT (7715L)\n+#define RST9538_STAT_DDR3_IDLY_MMCM_LOCKED (7716L)\n+#define RST9538_STAT_DDR3_MMCM_LOCKED (7717L)\n+#define RST9538_STAT_DDR3_PLL_LOCKED (7718L)\n+#define RST9538_STAT_PHY10G_QPLL_LOCK_0_1 (7719L)\n+#define RST9538_STAT_PHY10G_QPLL_LOCK_2_3 (7720L)\n+#define RST9538_STAT_PHY3S_MMCM_LOCKED (7721L)\n+#define RST9538_STAT_PTP_MMCM_LOCKED (7722L)\n+#define RST9538_STAT_SYNCE_MAIN_CLK_LOS (7723L)\n+#define RST9538_STAT_SYS_MMCM_LOCKED (7724L)\n+#define RST9538_STAT_TS_MMCM_LOCKED (7725L)\n+#define RST9538_STICKY (7726L)\n+#define RST9538_STICKY_DDR3_IDLY_MMCM_UNLOCKED (7727L)\n+#define RST9538_STICKY_DDR3_MMCM_UNLOCKED (7728L)\n+#define RST9538_STICKY_DDR3_PLL_UNLOCKED (7729L)\n+#define RST9538_STICKY_PHY10G_QPLL_UNLOCK_0_1 (7730L)\n+#define RST9538_STICKY_PHY10G_QPLL_UNLOCK_2_3 (7731L)\n+#define RST9538_STICKY_PHY3S_MMCM_UNLOCKED (7732L)\n+#define RST9538_STICKY_PTP_MMCM_UNLOCKED (7733L)\n+#define RST9538_STICKY_TS_MMCM_UNLOCKED (7734L)\n+/* RST9539 */\n+#define RST9539_CTRL (7735L)\n+#define RST9539_CTRL_PTP_MMCM_CLKSEL (7736L)\n+#define RST9539_CTRL_TS_CLKSEL (7737L)\n+#define RST9539_CTRL_TS_CLKSEL_OVERRIDE (7738L)\n+#define RST9539_POWER (7739L)\n+#define RST9539_POWER_PU_NSEB (7740L)\n+#define RST9539_POWER_PU_PHY (7741L)\n+#define RST9539_RST (7742L)\n+#define RST9539_RST_CORE_MMCM (7743L)\n+#define RST9539_RST_DDR4 (7744L)\n+#define RST9539_RST_PERIPH (7745L)\n+#define RST9539_RST_PHY (7746L)\n+#define RST9539_RST_PTP (7747L)\n+#define RST9539_RST_PTP_MMCM (7748L)\n+#define RST9539_RST_RPP (7749L)\n+#define RST9539_RST_SDC (7750L)\n+#define RST9539_RST_SYS (7751L)\n+#define RST9539_RST_SYS_MMCM (7752L)\n+#define RST9539_RST_TMC (7753L)\n+#define RST9539_RST_TS (7754L)\n+#define RST9539_RST_TS_MMCM (7755L)\n+#define RST9539_STAT (7756L)\n+#define RST9539_STAT_CORE_MMCM_LOCKED (7757L)\n+#define RST9539_STAT_DDR4_MMCM_LOCKED (7758L)\n+#define RST9539_STAT_DDR4_PLL_LOCKED (7759L)\n+#define RST9539_STAT_PTP_MMCM_LOCKED (7760L)\n+#define RST9539_STAT_SYS_MMCM_LOCKED (7761L)\n+#define RST9539_STAT_TS_MMCM_LOCKED (7762L)\n+#define RST9539_STICKY (7763L)\n+#define RST9539_STICKY_CORE_MMCM_UNLOCKED (7764L)\n+#define RST9539_STICKY_DDR4_MMCM_UNLOCKED (7765L)\n+#define RST9539_STICKY_DDR4_PLL_UNLOCKED (7766L)\n+#define RST9539_STICKY_PTP_MMCM_UNLOCKED (7767L)\n+#define RST9539_STICKY_SYS_MMCM_UNLOCKED (7768L)\n+#define RST9539_STICKY_TS_MMCM_UNLOCKED (7769L)\n+/* RST9540 */\n+#define RST9540_CTRL (7770L)\n+#define RST9540_CTRL_PTP_MMCM_CLKSEL (7771L)\n+#define RST9540_CTRL_TS_CLKSEL (7772L)\n+#define RST9540_CTRL_TS_CLKSEL_OVERRIDE (7773L)\n+#define RST9540_POWER (7774L)\n+#define RST9540_POWER_PU_NSEB (7775L)\n+#define RST9540_POWER_PU_PHY (7776L)\n+#define RST9540_RST (7777L)\n+#define RST9540_RST_CORE_MMCM (7778L)\n+#define RST9540_RST_DDR4 (7779L)\n+#define RST9540_RST_MAC_RX (7780L)\n+#define RST9540_RST_MAC_TX (7781L)\n+#define RST9540_RST_PCS_RX (7782L)\n+#define RST9540_RST_PERIPH (7783L)\n+#define RST9540_RST_PHY (7784L)\n+#define RST9540_RST_PTP (7785L)\n+#define RST9540_RST_PTP_MMCM (7786L)\n+#define RST9540_RST_RPP (7787L)\n+#define RST9540_RST_SDC (7788L)\n+#define RST9540_RST_SERDES_RX (7789L)\n+#define RST9540_RST_SERDES_RX_DATAPATH (7790L)\n+#define RST9540_RST_SERDES_TX (7791L)\n+#define RST9540_RST_SYS (7792L)\n+#define RST9540_RST_SYS_MMCM (7793L)\n+#define RST9540_RST_TMC (7794L)\n+#define RST9540_RST_TS (7795L)\n+#define RST9540_RST_TS_MMCM (7796L)\n+#define RST9540_STAT (7797L)\n+#define RST9540_STAT_CORE_MMCM_LOCKED (7798L)\n+#define RST9540_STAT_DDR4_MMCM_LOCKED (7799L)\n+#define RST9540_STAT_DDR4_PLL_LOCKED (7800L)\n+#define RST9540_STAT_PTP_MMCM_LOCKED (7801L)\n+#define RST9540_STAT_SYS_MMCM_LOCKED (7802L)\n+#define RST9540_STAT_TS_MMCM_LOCKED (7803L)\n+#define RST9540_STICKY (7804L)\n+#define RST9540_STICKY_CORE_MMCM_UNLOCKED (7805L)\n+#define RST9540_STICKY_DDR4_MMCM_UNLOCKED (7806L)\n+#define RST9540_STICKY_DDR4_PLL_UNLOCKED (7807L)\n+#define RST9540_STICKY_PTP_MMCM_UNLOCKED (7808L)\n+#define RST9540_STICKY_SYS_MMCM_UNLOCKED (7809L)\n+#define RST9540_STICKY_TS_MMCM_UNLOCKED (7810L)\n+/* RST9541 */\n+#define RST9541_LATCH (7811L)\n+#define RST9541_LATCH_DDR4_CALIB_COMPLETE (7812L)\n+#define RST9541_LATCH_PHY_RDY (7813L)\n+#define RST9541_POWER (7814L)\n+#define RST9541_POWER_PU_PHY (7815L)\n+#define RST9541_RST (7816L)\n+#define RST9541_RST_DDR4 (7817L)\n+#define RST9541_RST_PERIPH (7818L)\n+#define RST9541_RST_PHY (7819L)\n+#define RST9541_RST_POWER (7820L)\n+#define RST9541_RST_SYS (7821L)\n+#define RST9541_STAT (7822L)\n+#define RST9541_STAT_DDR4_CALIB_COMPLETE (7823L)\n+#define RST9541_STAT_PHY_RDY (7824L)\n+/* RST9542 */\n+#define RST9542_LATCH (7825L)\n+#define RST9542_LATCH_DDR4_CALIB_COMPLETE (7826L)\n+#define RST9542_LATCH_PHY_RDY (7827L)\n+#define RST9542_POWER (7828L)\n+#define RST9542_POWER_PU_PHY (7829L)\n+#define RST9542_RST (7830L)\n+#define RST9542_RST_DDR4 (7831L)\n+#define RST9542_RST_PERIPH (7832L)\n+#define RST9542_RST_PHY (7833L)\n+#define RST9542_RST_SYS (7834L)\n+#define RST9542_STAT (7835L)\n+#define RST9542_STAT_DDR4_CALIB_COMPLETE (7836L)\n+#define RST9542_STAT_PHY_RDY (7837L)\n+/* RST9543 */\n+#define RST9543_CTRL (7838L)\n+#define RST9543_CTRL_PTP_MMCM_CLKSEL (7839L)\n+#define RST9543_CTRL_TS_CLKSEL (7840L)\n+#define RST9543_CTRL_TS_CLKSEL_OVERRIDE (7841L)\n+#define RST9543_POWER (7842L)\n+#define RST9543_POWER_PU_NSEB (7843L)\n+#define RST9543_POWER_PU_PHY (7844L)\n+#define RST9543_RST (7845L)\n+#define RST9543_RST_CORE_MMCM (7846L)\n+#define RST9543_RST_DDR4 (7847L)\n+#define RST9543_RST_MAC_RX (7848L)\n+#define RST9543_RST_PERIPH (7849L)\n+#define RST9543_RST_PHY (7850L)\n+#define RST9543_RST_PTP (7851L)\n+#define RST9543_RST_PTP_MMCM (7852L)\n+#define RST9543_RST_RPP (7853L)\n+#define RST9543_RST_SDC (7854L)\n+#define RST9543_RST_SYS (7855L)\n+#define RST9543_RST_SYS_MMCM (7856L)\n+#define RST9543_RST_TMC (7857L)\n+#define RST9543_RST_TS (7858L)\n+#define RST9543_RST_TS_MMCM (7859L)\n+#define RST9543_STAT (7860L)\n+#define RST9543_STAT_CORE_MMCM_LOCKED (7861L)\n+#define RST9543_STAT_DDR4_MMCM_LOCKED (7862L)\n+#define RST9543_STAT_DDR4_PLL_LOCKED (7863L)\n+#define RST9543_STAT_PTP_MMCM_LOCKED (7864L)\n+#define RST9543_STAT_SYS_MMCM_LOCKED (7865L)\n+#define RST9543_STAT_TS_MMCM_LOCKED (7866L)\n+#define RST9543_STICKY (7867L)\n+#define RST9543_STICKY_CORE_MMCM_UNLOCKED (7868L)\n+#define RST9543_STICKY_DDR4_MMCM_UNLOCKED (7869L)\n+#define RST9543_STICKY_DDR4_PLL_UNLOCKED (7870L)\n+#define RST9543_STICKY_PTP_MMCM_UNLOCKED (7871L)\n+#define RST9543_STICKY_SYS_MMCM_UNLOCKED (7872L)\n+#define RST9543_STICKY_TS_MMCM_UNLOCKED (7873L)\n+/* RST9544 */\n+#define RST9544_CTRL (7874L)\n+#define RST9544_CTRL_PTP_MMCM_CLKSEL (7875L)\n+#define RST9544_CTRL_TS_CLKSEL (7876L)\n+#define RST9544_CTRL_TS_CLKSEL_OVERRIDE (7877L)\n+#define RST9544_CTRL_TS_CLKSEL_REF (7878L)\n+#define RST9544_POWER (7879L)\n+#define RST9544_POWER_PU_NSEB (7880L)\n+#define RST9544_POWER_PU_PHY (7881L)\n+#define RST9544_RST (7882L)\n+#define RST9544_RST_CORE_MMCM (7883L)\n+#define RST9544_RST_DDR4 (7884L)\n+#define RST9544_RST_NFV_OVS (7885L)\n+#define RST9544_RST_PERIPH (7886L)\n+#define RST9544_RST_PHY (7887L)\n+#define RST9544_RST_PTP (7888L)\n+#define RST9544_RST_PTP_MMCM (7889L)\n+#define RST9544_RST_RPP (7890L)\n+#define RST9544_RST_SDC (7891L)\n+#define RST9544_RST_SYS (7892L)\n+#define RST9544_RST_SYS_MMCM (7893L)\n+#define RST9544_RST_TMC (7894L)\n+#define RST9544_RST_TS (7895L)\n+#define RST9544_RST_TSM_REF_MMCM (7896L)\n+#define RST9544_RST_TS_MMCM (7897L)\n+#define RST9544_STAT (7898L)\n+#define RST9544_STAT_CORE_MMCM_LOCKED (7899L)\n+#define RST9544_STAT_DDR4_MMCM_LOCKED (7900L)\n+#define RST9544_STAT_DDR4_PLL_LOCKED (7901L)\n+#define RST9544_STAT_PTP_MMCM_LOCKED (7902L)\n+#define RST9544_STAT_SYS_MMCM_LOCKED (7903L)\n+#define RST9544_STAT_TSM_REF_MMCM_LOCKED (7904L)\n+#define RST9544_STAT_TS_MMCM_LOCKED (7905L)\n+#define RST9544_STICKY (7906L)\n+#define RST9544_STICKY_CORE_MMCM_UNLOCKED (7907L)\n+#define RST9544_STICKY_DDR4_MMCM_UNLOCKED (7908L)\n+#define RST9544_STICKY_DDR4_PLL_UNLOCKED (7909L)\n+#define RST9544_STICKY_PCI_SYS_MMCM_UNLOCKED (7910L)\n+#define RST9544_STICKY_PTP_MMCM_UNLOCKED (7911L)\n+#define RST9544_STICKY_SYS_MMCM_UNLOCKED (7912L)\n+#define RST9544_STICKY_TSM_REF_MMCM_UNLOCKED (7913L)\n+#define RST9544_STICKY_TS_MMCM_UNLOCKED (7914L)\n+/* RST9545 */\n+#define RST9545_CTRL (7915L)\n+#define RST9545_CTRL_PTP_MMCM_CLKSEL (7916L)\n+#define RST9545_CTRL_TS_CLKSEL (7917L)\n+#define RST9545_CTRL_TS_CLKSEL_OVERRIDE (7918L)\n+#define RST9545_POWER (7919L)\n+#define RST9545_POWER_PU_NSEB (7920L)\n+#define RST9545_POWER_PU_PHY (7921L)\n+#define RST9545_RST (7922L)\n+#define RST9545_RST_CORE_MMCM (7923L)\n+#define RST9545_RST_DDR4 (7924L)\n+#define RST9545_RST_PERIPH (7925L)\n+#define RST9545_RST_PHY (7926L)\n+#define RST9545_RST_PTP (7927L)\n+#define RST9545_RST_PTP_MMCM (7928L)\n+#define RST9545_RST_RPP (7929L)\n+#define RST9545_RST_SDC (7930L)\n+#define RST9545_RST_SYS (7931L)\n+#define RST9545_RST_SYS_MMCM (7932L)\n+#define RST9545_RST_TMC (7933L)\n+#define RST9545_RST_TS (7934L)\n+#define RST9545_RST_TS_MMCM (7935L)\n+#define RST9545_STAT (7936L)\n+#define RST9545_STAT_CORE_MMCM_LOCKED (7937L)\n+#define RST9545_STAT_DDR4_MMCM_LOCKED (7938L)\n+#define RST9545_STAT_DDR4_PLL_LOCKED (7939L)\n+#define RST9545_STAT_PTP_MMCM_LOCKED (7940L)\n+#define RST9545_STAT_SYS_MMCM_LOCKED (7941L)\n+#define RST9545_STAT_TS_MMCM_LOCKED (7942L)\n+#define RST9545_STICKY (7943L)\n+#define RST9545_STICKY_CORE_MMCM_UNLOCKED (7944L)\n+#define RST9545_STICKY_DDR4_MMCM_UNLOCKED (7945L)\n+#define RST9545_STICKY_DDR4_PLL_UNLOCKED (7946L)\n+#define RST9545_STICKY_PTP_MMCM_UNLOCKED (7947L)\n+#define RST9545_STICKY_SYS_MMCM_UNLOCKED (7948L)\n+#define RST9545_STICKY_TS_MMCM_UNLOCKED (7949L)\n+/* RST9546 */\n+#define RST9546_CTRL (7950L)\n+#define RST9546_CTRL_PTP_MMCM_CLKSEL (7951L)\n+#define RST9546_CTRL_TS_CLKSEL (7952L)\n+#define RST9546_CTRL_TS_CLKSEL_OVERRIDE (7953L)\n+#define RST9546_POWER (7954L)\n+#define RST9546_POWER_PU_NSEB (7955L)\n+#define RST9546_POWER_PU_PHY (7956L)\n+#define RST9546_RST (7957L)\n+#define RST9546_RST_CORE_MMCM (7958L)\n+#define RST9546_RST_DDR4 (7959L)\n+#define RST9546_RST_MAC_RX (7960L)\n+#define RST9546_RST_MAC_TX (7961L)\n+#define RST9546_RST_PCS_RX (7962L)\n+#define RST9546_RST_PERIPH (7963L)\n+#define RST9546_RST_PHY (7964L)\n+#define RST9546_RST_PTP (7965L)\n+#define RST9546_RST_PTP_MMCM (7966L)\n+#define RST9546_RST_RPP (7967L)\n+#define RST9546_RST_SDC (7968L)\n+#define RST9546_RST_SERDES_RX (7969L)\n+#define RST9546_RST_SERDES_RX_DATAPATH (7970L)\n+#define RST9546_RST_SERDES_TX (7971L)\n+#define RST9546_RST_SYS (7972L)\n+#define RST9546_RST_SYS_MMCM (7973L)\n+#define RST9546_RST_TMC (7974L)\n+#define RST9546_RST_TS (7975L)\n+#define RST9546_RST_TS_MMCM (7976L)\n+#define RST9546_STAT (7977L)\n+#define RST9546_STAT_CORE_MMCM_LOCKED (7978L)\n+#define RST9546_STAT_DDR4_MMCM_LOCKED (7979L)\n+#define RST9546_STAT_DDR4_PLL_LOCKED (7980L)\n+#define RST9546_STAT_PTP_MMCM_LOCKED (7981L)\n+#define RST9546_STAT_SYS_MMCM_LOCKED (7982L)\n+#define RST9546_STAT_TS_MMCM_LOCKED (7983L)\n+#define RST9546_STICKY (7984L)\n+#define RST9546_STICKY_CORE_MMCM_UNLOCKED (7985L)\n+#define RST9546_STICKY_DDR4_MMCM_UNLOCKED (7986L)\n+#define RST9546_STICKY_DDR4_PLL_UNLOCKED (7987L)\n+#define RST9546_STICKY_PTP_MMCM_UNLOCKED (7988L)\n+#define RST9546_STICKY_SYS_MMCM_UNLOCKED (7989L)\n+#define RST9546_STICKY_TS_MMCM_UNLOCKED (7990L)\n+/* RST9547 */\n+#define RST9547_LATCH (7991L)\n+#define RST9547_LATCH_DDR4_CALIB_COMPLETE (7992L)\n+#define RST9547_LATCH_PHY_RDY (7993L)\n+#define RST9547_POWER (7994L)\n+#define RST9547_POWER_PU_PHY (7995L)\n+#define RST9547_RST (7996L)\n+#define RST9547_RST_DDR4 (7997L)\n+#define RST9547_RST_PERIPH (7998L)\n+#define RST9547_RST_PHY (7999L)\n+#define RST9547_RST_SYS (8000L)\n+#define RST9547_STAT (8001L)\n+#define RST9547_STAT_DDR4_CALIB_COMPLETE (8002L)\n+#define RST9547_STAT_PHY_RDY (8003L)\n+/* RST9548 */\n+#define RST9548_CTRL (8004L)\n+#define RST9548_CTRL_PTP_MMCM_CLKSEL (8005L)\n+#define RST9548_CTRL_TS_CLKSEL (8006L)\n+#define RST9548_CTRL_TS_CLKSEL_OVERRIDE (8007L)\n+#define RST9548_POWER (8008L)\n+#define RST9548_POWER_PU_NSEB (8009L)\n+#define RST9548_POWER_PU_PHY (8010L)\n+#define RST9548_RST (8011L)\n+#define RST9548_RST_CORE_MMCM (8012L)\n+#define RST9548_RST_DDR4 (8013L)\n+#define RST9548_RST_PERIPH (8014L)\n+#define RST9548_RST_PHY (8015L)\n+#define RST9548_RST_PTP (8016L)\n+#define RST9548_RST_PTP_MMCM (8017L)\n+#define RST9548_RST_RPP (8018L)\n+#define RST9548_RST_SDC (8019L)\n+#define RST9548_RST_SYS (8020L)\n+#define RST9548_RST_SYS_MMCM (8021L)\n+#define RST9548_RST_TMC (8022L)\n+#define RST9548_RST_TS (8023L)\n+#define RST9548_RST_TS_MMCM (8024L)\n+#define RST9548_STAT (8025L)\n+#define RST9548_STAT_CORE_MMCM_LOCKED (8026L)\n+#define RST9548_STAT_DDR4_MMCM_LOCKED (8027L)\n+#define RST9548_STAT_DDR4_PLL_LOCKED (8028L)\n+#define RST9548_STAT_PTP_MMCM_LOCKED (8029L)\n+#define RST9548_STAT_SYS_MMCM_LOCKED (8030L)\n+#define RST9548_STAT_TS_MMCM_LOCKED (8031L)\n+#define RST9548_STICKY (8032L)\n+#define RST9548_STICKY_CORE_MMCM_UNLOCKED (8033L)\n+#define RST9548_STICKY_DDR4_MMCM_UNLOCKED (8034L)\n+#define RST9548_STICKY_DDR4_PLL_UNLOCKED (8035L)\n+#define RST9548_STICKY_PTP_MMCM_UNLOCKED (8036L)\n+#define RST9548_STICKY_SYS_MMCM_UNLOCKED (8037L)\n+#define RST9548_STICKY_TS_MMCM_UNLOCKED (8038L)\n+/* RST9549 */\n+#define RST9549_CTRL (8039L)\n+#define RST9549_CTRL_PTP_MMCM_CLKSEL (8040L)\n+#define RST9549_CTRL_TS_CLKSEL (8041L)\n+#define RST9549_CTRL_TS_CLKSEL_OVERRIDE (8042L)\n+#define RST9549_POWER (8043L)\n+#define RST9549_POWER_PU_NSEB (8044L)\n+#define RST9549_POWER_PU_PHY (8045L)\n+#define RST9549_RST (8046L)\n+#define RST9549_RST_CORE_MMCM (8047L)\n+#define RST9549_RST_DDR4 (8048L)\n+#define RST9549_RST_PERIPH (8049L)\n+#define RST9549_RST_PHY (8050L)\n+#define RST9549_RST_PTP (8051L)\n+#define RST9549_RST_PTP_MMCM (8052L)\n+#define RST9549_RST_RPP (8053L)\n+#define RST9549_RST_SDC (8054L)\n+#define RST9549_RST_SYS (8055L)\n+#define RST9549_RST_SYS_MMCM (8056L)\n+#define RST9549_RST_TMC (8057L)\n+#define RST9549_RST_TS (8058L)\n+#define RST9549_RST_TS_MMCM (8059L)\n+#define RST9549_STAT (8060L)\n+#define RST9549_STAT_CORE_MMCM_LOCKED (8061L)\n+#define RST9549_STAT_DDR4_MMCM_LOCKED (8062L)\n+#define RST9549_STAT_DDR4_PLL_LOCKED (8063L)\n+#define RST9549_STAT_PTP_MMCM_LOCKED (8064L)\n+#define RST9549_STAT_SYS_MMCM_LOCKED (8065L)\n+#define RST9549_STAT_TS_MMCM_LOCKED (8066L)\n+#define RST9549_STICKY (8067L)\n+#define RST9549_STICKY_CORE_MMCM_UNLOCKED (8068L)\n+#define RST9549_STICKY_DDR4_MMCM_UNLOCKED (8069L)\n+#define RST9549_STICKY_DDR4_PLL_UNLOCKED (8070L)\n+#define RST9549_STICKY_PTP_MMCM_UNLOCKED (8071L)\n+#define RST9549_STICKY_SYS_MMCM_UNLOCKED (8072L)\n+#define RST9549_STICKY_TS_MMCM_UNLOCKED (8073L)\n+/* RST9553 */\n+#define RST9553_LATCH (8074L)\n+#define RST9553_LATCH_DDR4_CALIB_COMPLETE (8075L)\n+#define RST9553_LATCH_PHY_RDY (8076L)\n+#define RST9553_RST (8077L)\n+#define RST9553_RST_DDR4 (8078L)\n+#define RST9553_RST_PHY (8079L)\n+#define RST9553_RST_SYS (8080L)\n+#define RST9553_STAT (8081L)\n+#define RST9553_STAT_DDR4_CALIB_COMPLETE (8082L)\n+#define RST9553_STAT_PHY_RDY (8083L)\n+/* RST9555 */\n+#define RST9555_CTRL (8094L)\n+#define RST9555_CTRL_PTP_MMCM_CLKSEL (8095L)\n+#define RST9555_CTRL_TS_CLKSEL (8096L)\n+#define RST9555_CTRL_TS_CLKSEL_OVERRIDE (8097L)\n+#define RST9555_POWER (8098L)\n+#define RST9555_POWER_PU_NSEB (8099L)\n+#define RST9555_POWER_PU_PHY (8100L)\n+#define RST9555_RST (8101L)\n+#define RST9555_RST_CORE_MMCM (8102L)\n+#define RST9555_RST_DDR4 (8103L)\n+#define RST9555_RST_PERIPH (8104L)\n+#define RST9555_RST_PHY (8105L)\n+#define RST9555_RST_PTP (8106L)\n+#define RST9555_RST_PTP_MMCM (8107L)\n+#define RST9555_RST_RPP (8108L)\n+#define RST9555_RST_SDC (8109L)\n+#define RST9555_RST_SYS (8110L)\n+#define RST9555_RST_SYS_MMCM (8111L)\n+#define RST9555_RST_TMC (8112L)\n+#define RST9555_RST_TS (8113L)\n+#define RST9555_RST_TS_MMCM (8114L)\n+#define RST9555_STAT (8115L)\n+#define RST9555_STAT_CORE_MMCM_LOCKED (8116L)\n+#define RST9555_STAT_DDR4_MMCM_LOCKED (8117L)\n+#define RST9555_STAT_DDR4_PLL_LOCKED (8118L)\n+#define RST9555_STAT_PTP_MMCM_LOCKED (8119L)\n+#define RST9555_STAT_SYS_MMCM_LOCKED (8120L)\n+#define RST9555_STAT_TS_MMCM_LOCKED (8121L)\n+#define RST9555_STICKY (8122L)\n+#define RST9555_STICKY_CORE_MMCM_UNLOCKED (8123L)\n+#define RST9555_STICKY_DDR4_MMCM_UNLOCKED (8124L)\n+#define RST9555_STICKY_DDR4_PLL_UNLOCKED (8125L)\n+#define RST9555_STICKY_PTP_MMCM_UNLOCKED (8126L)\n+#define RST9555_STICKY_SYS_MMCM_UNLOCKED (8127L)\n+#define RST9555_STICKY_TS_MMCM_UNLOCKED (8128L)\n+/* RST9559 */\n+#define RST9559_LATCH (8129L)\n+#define RST9559_LATCH_DDR4_CALIB_COMPLETE (8130L)\n+#define RST9559_LATCH_PHY_RDY (8131L)\n+#define RST9559_RST (8132L)\n+#define RST9559_RST_DDR4 (8133L)\n+#define RST9559_RST_PHY (8134L)\n+#define RST9559_RST_SYS (8135L)\n+#define RST9559_STAT (8136L)\n+#define RST9559_STAT_DDR4_CALIB_COMPLETE (8137L)\n+#define RST9559_STAT_PHY_RDY (8138L)\n+/* RST9563 */\n+#define RST9563_CTRL (8159L)\n+#define RST9563_CTRL_PTP_MMCM_CLKSEL (8160L)\n+#define RST9563_CTRL_TS_CLKSEL (8161L)\n+#define RST9563_CTRL_TS_CLKSEL_OVERRIDE (8162L)\n+#define RST9563_POWER (8163L)\n+#define RST9563_POWER_PU_NSEB (8164L)\n+#define RST9563_POWER_PU_PHY (8165L)\n+#define RST9563_RST (8166L)\n+#define RST9563_RST_CORE_MMCM (8167L)\n+#define RST9563_RST_DDR4 (8168L)\n+#define RST9563_RST_MAC_RX (8169L)\n+#define RST9563_RST_PERIPH (8170L)\n+#define RST9563_RST_PHY (8171L)\n+#define RST9563_RST_PTP (8172L)\n+#define RST9563_RST_PTP_MMCM (8173L)\n+#define RST9563_RST_RPP (8174L)\n+#define RST9563_RST_SDC (8175L)\n+#define RST9563_RST_SYS (8176L)\n+#define RST9563_RST_SYS_MMCM (8177L)\n+#define RST9563_RST_TMC (8178L)\n+#define RST9563_RST_TS (8179L)\n+#define RST9563_RST_TSM_REF_MMCM (8180L)\n+#define RST9563_RST_TS_MMCM (8181L)\n+#define RST9563_STAT (8182L)\n+#define RST9563_STAT_CORE_MMCM_LOCKED (8183L)\n+#define RST9563_STAT_DDR4_MMCM_LOCKED (8184L)\n+#define RST9563_STAT_DDR4_PLL_LOCKED (8185L)\n+#define RST9563_STAT_PTP_MMCM_LOCKED (8186L)\n+#define RST9563_STAT_SYS_MMCM_LOCKED (8187L)\n+#define RST9563_STAT_TS_MMCM_LOCKED (8188L)\n+#define RST9563_STICKY (8189L)\n+#define RST9563_STICKY_CORE_MMCM_UNLOCKED (8190L)\n+#define RST9563_STICKY_DDR4_MMCM_UNLOCKED (8191L)\n+#define RST9563_STICKY_DDR4_PLL_UNLOCKED (8192L)\n+#define RST9563_STICKY_PTP_MMCM_UNLOCKED (8193L)\n+#define RST9563_STICKY_SYS_MMCM_UNLOCKED (8194L)\n+#define RST9563_STICKY_TS_MMCM_UNLOCKED (8195L)\n+/* RTD */\n+#define RTD_CTRL (8196L)\n+#define RTD_CTRL_ENABLE_RTD (8197L)\n+#define RTD_CTRL_ENABLE_TX_FLUSH (8198L)\n+#define RTD_CTRL_ENABLE_TX_MACPHY (8199L)\n+#define RTD_CTRL_RDPTR_UPDATE_TIMER (8200L)\n+#define RTD_CTRL_RESERVED (8201L)\n+#define RTD_CTRL_TX_SPEED (8202L)\n+#define RTD_DEB_REG1 (8203L)\n+#define RTD_DEB_REG1_VALUE (8204L)\n+#define RTD_DEB_REG2 (8205L)\n+#define RTD_DEB_REG2_VALUE (8206L)\n+#define RTD_DEB_REG3 (8207L)\n+#define RTD_DEB_REG3_VALUE (8208L)\n+#define RTD_HOSTBUFFER_ADR_HI (8209L)\n+#define RTD_HOSTBUFFER_ADR_HI_VALUE (8210L)\n+#define RTD_HOSTBUFFER_ADR_LO (8211L)\n+#define RTD_HOSTBUFFER_ADR_LO_VALUE (8212L)\n+#define RTD_RDPTR_ADR_HI (8213L)\n+#define RTD_RDPTR_ADR_HI_VALUE (8214L)\n+#define RTD_RDPTR_ADR_LO (8215L)\n+#define RTD_RDPTR_ADR_LO_VALUE (8216L)\n+#define RTD_STATUS (8217L)\n+#define RTD_STATUS_HB_EMPTY (8218L)\n+#define RTD_STATUS_LHF_EMPTY (8219L)\n+#define RTD_STATUS_UNPACKER_STATUS (8220L)\n+#define RTD_WRPTR (8221L)\n+#define RTD_WRPTR_VALUE (8222L)\n+/* RTD_HMP */\n+#define RTD_HMP_CTRL (8223L)\n+#define RTD_HMP_CTRL_ENABLE_HMP_0 (8224L)\n+#define RTD_HMP_CTRL_ENABLE_HMP_1 (8225L)\n+#define RTD_HMP_CTRL_ENABLE_HMP_2 (8226L)\n+#define RTD_HMP_CTRL_ENABLE_HMP_3 (8227L)\n+#define RTD_HMP_CTRL_WRPTR_POLL_TIMER (8228L)\n+#define RTD_HMP_DEB_REG1 (8229L)\n+#define RTD_HMP_DEB_REG1_VALUE (8230L)\n+#define RTD_HMP_DEB_REG2 (8231L)\n+#define RTD_HMP_DEB_REG2_VALUE (8232L)\n+#define RTD_HMP_DEB_REG3 (8233L)\n+#define RTD_HMP_DEB_REG3_VALUE (8234L)\n+#define RTD_HMP_STATUS (8235L)\n+#define RTD_HMP_STATUS_HMP_ACTIVE (8236L)\n+#define RTD_HMP_WRPTR_ADR_HI (8237L)\n+#define RTD_HMP_WRPTR_ADR_HI_VALUE (8238L)\n+#define RTD_HMP_WRPTR_ADR_LO (8239L)\n+#define RTD_HMP_WRPTR_ADR_LO_VALUE (8240L)\n+/* RTX */\n+#define RTX_CTRL (8241L)\n+#define RTX_CTRL_PORT (8242L)\n+#define RTX_CTRL_SIZE (8243L)\n+#define RTX_STATUS (8244L)\n+#define RTX_STATUS_AF (8245L)\n+#define RTX_STATUS_BUSY (8246L)\n+#define RTX_TXF_CTRL (8247L)\n+#define RTX_TXF_CTRL_CNT (8248L)\n+#define RTX_TXF_DATA (8249L)\n+#define RTX_TXF_DATA_PAYLOAD (8250L)\n+#define RXAUI_DEBUG (8268L)\n+#define RXAUI_DEBUG_MGT_CV_0 (8269L)\n+#define RXAUI_DEBUG_MGT_CV_1 (8270L)\n+#define RXAUI_DEBUG_MGT_CV_2 (8271L)\n+#define RXAUI_DEBUG_MGT_CV_3 (8272L)\n+#define RXAUI_DEBUG_MGT_CV_4 (8273L)\n+#define RXAUI_DEBUG_MGT_CV_5 (8274L)\n+#define RXAUI_DEBUG_MGT_CV_6 (8275L)\n+#define RXAUI_DEBUG_MGT_CV_7 (8276L)\n+#define RXAUI_DEBUG_MGT_RXLOCK_0 (8277L)\n+#define RXAUI_DEBUG_MGT_RXLOCK_1 (8278L)\n+#define RXAUI_DEBUG_MGT_RX_RESET (8279L)\n+#define RXAUI_DEBUG_MGT_TX_RESET (8280L)\n+#define RXAUI_DEBUG_MMCM1_LOCKED (8281L)\n+#define RXAUI_DRP_AD (8282L)\n+#define RXAUI_DRP_AD_ADDRESS (8283L)\n+#define RXAUI_DRP_AD_DFEEYEDACMON (8284L)\n+#define RXAUI_DRP_AD_GTX_NO (8285L)\n+#define RXAUI_DRP_AD_READY (8286L)\n+#define RXAUI_DRP_AD_RESERVED3 (8287L)\n+#define RXAUI_DRP_AD_RESERVED4 (8288L)\n+#define RXAUI_DRP_DA (8289L)\n+#define RXAUI_DRP_DA_DATA (8290L)\n+#define RXAUI_GTX_CONFIG (8291L)\n+#define RXAUI_GTX_CONFIG_LOOPBACK (8292L)\n+#define RXAUI_GTX_CONFIG_LOOPBACKMUX (8293L)\n+#define RXAUI_GTX_CONFIG_PRBSCNTRESET (8294L)\n+#define RXAUI_GTX_CONFIG_RESERVED6 (8295L)\n+#define RXAUI_GTX_CONFIG_RESERVED7 (8296L)\n+#define RXAUI_GTX_CONFIG_RXENPRBSTST (8297L)\n+#define RXAUI_GTX_CONFIG_RXEQMIX (8298L)\n+#define RXAUI_GTX_CONFIG_TXDIFFCTRL (8299L)\n+#define RXAUI_GTX_CONFIG_TXENPRBSTST (8300L)\n+#define RXAUI_GTX_CONFIG_TXPOSTEMPHAS (8301L)\n+#define RXAUI_GTX_CONFIG_TXPRBSFORCEE (8302L)\n+#define RXAUI_GTX_CONFIG_TXPREEMPHASI (8303L)\n+#define RXAUI_GTX_STAT (8304L)\n+#define RXAUI_GTX_STAT_RESERVED10 (8305L)\n+#define RXAUI_GTX_STAT_RESERVED11 (8306L)\n+#define RXAUI_GTX_STAT_RESERVED12 (8307L)\n+#define RXAUI_GTX_STAT_RESERVED13 (8308L)\n+#define RXAUI_GTX_STAT_RESERVED8 (8309L)\n+#define RXAUI_GTX_STAT_RESERVED9 (8310L)\n+#define RXAUI_GTX_STAT_RXBUFSTATUS0 (8311L)\n+#define RXAUI_GTX_STAT_RXBUFSTATUS1 (8312L)\n+#define RXAUI_GTX_STAT_RXBYTEISAL_0 (8313L)\n+#define RXAUI_GTX_STAT_RXBYTEISAL_1 (8314L)\n+#define RXAUI_GTX_STAT_RXBYTEREAL_0 (8315L)\n+#define RXAUI_GTX_STAT_RXBYTEREAL_1 (8316L)\n+#define RXAUI_GTX_STAT_RXCHANREAL_0 (8317L)\n+#define RXAUI_GTX_STAT_RXCHANREAL_1 (8318L)\n+#define RXAUI_GTX_STAT_RXCOMMADET_0 (8319L)\n+#define RXAUI_GTX_STAT_RXCOMMADET_1 (8320L)\n+#define RXAUI_GTX_STAT_RXPRBSERR_0 (8321L)\n+#define RXAUI_GTX_STAT_RXPRBSERR_1 (8322L)\n+/* SDC */\n+#define SDC_CELL_CNT (8612L)\n+#define SDC_CELL_CNT_CELL_CNT (8613L)\n+#define SDC_CELL_CNT_PERIOD (8614L)\n+#define SDC_CELL_CNT_PERIOD_CELL_CNT_PERIOD (8615L)\n+#define SDC_CTRL (8616L)\n+#define SDC_CTRL_INIT (8617L)\n+#define SDC_CTRL_RESET_POINTERS (8618L)\n+#define SDC_CTRL_RUN_TEST (8619L)\n+#define SDC_CTRL_STOP_CLIENT (8620L)\n+#define SDC_CTRL_TEST_EN (8621L)\n+#define SDC_FILL_LVL (8622L)\n+#define SDC_FILL_LVL_FILL_LVL (8623L)\n+#define SDC_MAX_FILL_LVL (8624L)\n+#define SDC_MAX_FILL_LVL_MAX_FILL_LVL (8625L)\n+#define SDC_STAT (8626L)\n+#define SDC_STAT_CALIB (8627L)\n+#define SDC_STAT_CELL_CNT_STOPPED (8628L)\n+#define SDC_STAT_ERR_FOUND (8629L)\n+#define SDC_STAT_INIT_DONE (8630L)\n+#define SDC_STAT_MMCM_LOCK (8631L)\n+#define SDC_STAT_PLL_LOCK (8632L)\n+#define SDC_STAT_RESETTING (8633L)\n+/* SLC */\n+#define SLC_RCP_CTRL (8681L)\n+#define SLC_RCP_CTRL_ADR (8682L)\n+#define SLC_RCP_CTRL_CNT (8683L)\n+#define SLC_RCP_DATA (8684L)\n+#define SLC_RCP_DATA_PCAP (8685L)\n+#define SLC_RCP_DATA_TAIL_DYN (8686L)\n+#define SLC_RCP_DATA_TAIL_OFS (8687L)\n+#define SLC_RCP_DATA_TAIL_SLC_EN (8688L)\n+/* SLC_LR */\n+/* SMM */\n+#define SMM_CTRL (8770L)\n+#define SMM_CTRL_ENABLE (8771L)\n+#define SMM_READY_STATUS (8772L)\n+#define SMM_READY_STATUS_D (8773L)\n+#define SMM_SEG_INVLD_STICKY_STATUS (8774L)\n+#define SMM_SEG_INVLD_STICKY_STATUS_D (8775L)\n+#define SMM_SEG_MEM_CTRL (8776L)\n+#define SMM_SEG_MEM_CTRL_A (8777L)\n+#define SMM_SEG_MEM_CTRL_CNT (8778L)\n+#define SMM_SEG_MEM_DATA (8779L)\n+#define SMM_SEG_MEM_DATA_PHYADDR (8780L)\n+#define SMM_SEG_MEM_DATA_SIZE (8781L)\n+#define SMM_START_SEG_MEM_CTRL (8782L)\n+#define SMM_START_SEG_MEM_CTRL_A (8783L)\n+#define SMM_START_SEG_MEM_CTRL_CNT (8784L)\n+#define SMM_START_SEG_MEM_DATA (8785L)\n+#define SMM_START_SEG_MEM_DATA_SEG (8786L)\n+/* SPIM */\n+#define SPIM_CFG (8793L)\n+#define SPIM_CFG_PRE (8794L)\n+#define SPIM_CMD (8795L)\n+#define SPIM_CMD_ADDR (8796L)\n+#define SPIM_CMD_CMD (8797L)\n+#define SPIM_CMD_DATA (8798L)\n+#define SPIM_CONF0 (8799L)\n+#define SPIM_CONF0_BYTE_PACE (8800L)\n+#define SPIM_CONF0_MIRROR_EN (8801L)\n+#define SPIM_CONF0_MSB_FIRST (8802L)\n+#define SPIM_CONF0_PRESCAL_CLK (8803L)\n+#define SPIM_CONF0_RESTART (8804L)\n+#define SPIM_CONF0_RST (8805L)\n+#define SPIM_CONF0_SYNC_MON_EN (8806L)\n+#define SPIM_CONF1 (8807L)\n+#define SPIM_CONF1_MIRROR_PACE (8808L)\n+#define SPIM_CONF1_MIRROR_SCAN (8809L)\n+#define SPIM_CONF1_SYNCTIMEOUT (8810L)\n+#define SPIM_CONF2 (8811L)\n+#define SPIM_CONF2_MIRROR_PRESC (8812L)\n+#define SPIM_CONF2_OPCODE_RD (8813L)\n+#define SPIM_CONF2_OPCODE_WR (8814L)\n+#define SPIM_CONF3 (8815L)\n+#define SPIM_CONF3_MIRROR_RDADR (8816L)\n+#define SPIM_CONF3_MIRROR_WRADR (8817L)\n+#define SPIM_CR (8818L)\n+#define SPIM_CR_EN (8819L)\n+#define SPIM_CR_LOOP (8820L)\n+#define SPIM_CR_RXRST (8821L)\n+#define SPIM_CR_TXRST (8822L)\n+#define SPIM_DRR (8823L)\n+#define SPIM_DRR_DRR (8824L)\n+#define SPIM_DTR (8825L)\n+#define SPIM_DTR_DTR (8826L)\n+#define SPIM_REPLY (8827L)\n+#define SPIM_REPLY_RDDATA (8828L)\n+#define SPIM_SR (8829L)\n+#define SPIM_SR_DONE (8830L)\n+#define SPIM_SR_RXEMPTY (8831L)\n+#define SPIM_SR_RXFULL (8832L)\n+#define SPIM_SR_RXLVL (8833L)\n+#define SPIM_SR_TXEMPTY (8834L)\n+#define SPIM_SR_TXFULL (8835L)\n+#define SPIM_SR_TXLVL (8836L)\n+#define SPIM_SRR (8837L)\n+#define SPIM_SRR_RST (8838L)\n+#define SPIM_STATUS (8839L)\n+#define SPIM_STATUS_CMDPENDING (8840L)\n+#define SPIM_STATUS_RESERVED (8841L)\n+#define SPIM_STATUS_RESYNCDETECT (8842L)\n+#define SPIM_STATUS_RESYNCING (8843L)\n+/* SPIS */\n+#define SPIS_CR (8844L)\n+#define SPIS_CR_DEBUG (8845L)\n+#define SPIS_CR_EN (8846L)\n+#define SPIS_CR_LOOP (8847L)\n+#define SPIS_CR_RXRST (8848L)\n+#define SPIS_CR_TXRST (8849L)\n+#define SPIS_DRR (8850L)\n+#define SPIS_DRR_DRR (8851L)\n+#define SPIS_DTR (8852L)\n+#define SPIS_DTR_DTR (8853L)\n+#define SPIS_RAM_CTRL (8854L)\n+#define SPIS_RAM_CTRL_ADR (8855L)\n+#define SPIS_RAM_CTRL_CNT (8856L)\n+#define SPIS_RAM_DATA (8857L)\n+#define SPIS_RAM_DATA_DATA (8858L)\n+#define SPIS_SR (8859L)\n+#define SPIS_SR_DONE (8860L)\n+#define SPIS_SR_FRAME_ERR (8861L)\n+#define SPIS_SR_READ_ERR (8862L)\n+#define SPIS_SR_RXEMPTY (8863L)\n+#define SPIS_SR_RXFULL (8864L)\n+#define SPIS_SR_RXLVL (8865L)\n+#define SPIS_SR_TXEMPTY (8866L)\n+#define SPIS_SR_TXFULL (8867L)\n+#define SPIS_SR_TXLVL (8868L)\n+#define SPIS_SR_WRITE_ERR (8869L)\n+#define SPIS_SRR (8870L)\n+#define SPIS_SRR_RST (8871L)\n+/* STA */\n+#define STA_BYTE (8872L)\n+#define STA_BYTE_CNT (8873L)\n+#define STA_CFG (8874L)\n+#define STA_CFG_CNT_CLEAR (8875L)\n+#define STA_CFG_CNT_FRZ (8876L)\n+#define STA_CFG_DMA_ENA (8877L)\n+#define STA_CFG_TX_DISABLE (8878L)\n+#define STA_CV_ERR (8879L)\n+#define STA_CV_ERR_CNT (8880L)\n+#define STA_FCS_ERR (8881L)\n+#define STA_FCS_ERR_CNT (8882L)\n+#define STA_HOST_ADR_LSB (8883L)\n+#define STA_HOST_ADR_LSB_LSB (8884L)\n+#define STA_HOST_ADR_MSB (8885L)\n+#define STA_HOST_ADR_MSB_MSB (8886L)\n+#define STA_PCKT (8887L)\n+#define STA_PCKT_CNT (8888L)\n+#define STA_STATUS (8889L)\n+#define STA_STATUS_STAT_TOGGLE_MISSED (8890L)\n+/* TBH */\n+#define TBH_CTRL (9103L)\n+#define TBH_CTRL_DISABLE_LR_LB (9104L)\n+#define TBH_CTRL_ENABLE (9105L)\n+#define TBH_CTRL_PORT (9106L)\n+#define TBH_CTRL_PORT_AUS (9107L)\n+#define TBH_CTRL_SEGMENT (9108L)\n+#define TBH_CTRL_SEGMENT_SIZE (9109L)\n+#define TBH_DBG_DLN_ERR (9110L)\n+#define TBH_DBG_DLN_ERR_E (9111L)\n+#define TBH_DBG_DLN_ERR_HB (9112L)\n+#define TBH_DBG_ILLEGAL_RANGE (9113L)\n+#define TBH_DBG_ILLEGAL_RANGE_E (9114L)\n+#define TBH_DBG_ILLEGAL_RANGE_HB (9115L)\n+#define TBH_DBG_MAX_PCI_QUIET (9116L)\n+#define TBH_DBG_MAX_PCI_QUIET_CYCLES (9117L)\n+#define TBH_DISABLE (9118L)\n+#define TBH_DISABLE_DISABLE (9119L)\n+#define TBH_DISABLE_HB (9120L)\n+#define TBH_HB_DSC_MEM_CTRL (9121L)\n+#define TBH_HB_DSC_MEM_CTRL_ADR (9122L)\n+#define TBH_HB_DSC_MEM_CTRL_CNT (9123L)\n+#define TBH_HB_DSC_MEM_DATA (9124L)\n+#define TBH_HB_DSC_MEM_DATA_DT (9125L)\n+#define TBH_HB_DSC_MEM_DATA_FCS (9126L)\n+#define TBH_HB_DSC_MEM_DATA_FCS_CTL_POS (9127L)\n+#define TBH_HB_DSC_MEM_DATA_FCS_CTL_USE (9128L)\n+#define TBH_HB_DSC_MEM_DATA_IG_POS (9129L)\n+#define TBH_HB_DSC_MEM_DATA_IG_USE (9130L)\n+#define TBH_HB_DSC_MEM_DATA_OCS_CMD_POS (9131L)\n+#define TBH_HB_DSC_MEM_DATA_OCS_CMD_USE (9132L)\n+#define TBH_HB_DSC_MEM_DATA_OFS0_POS (9133L)\n+#define TBH_HB_DSC_MEM_DATA_OFS0_USE (9134L)\n+#define TBH_HB_DSC_MEM_DATA_OFS1_POS (9135L)\n+#define TBH_HB_DSC_MEM_DATA_OFS1_USE (9136L)\n+#define TBH_HB_DSC_MEM_DATA_OFS2_POS (9137L)\n+#define TBH_HB_DSC_MEM_DATA_OFS2_USE (9138L)\n+#define TBH_HB_DSC_MEM_DATA_PFD (9139L)\n+#define TBH_HB_DSC_MEM_DATA_PORT (9140L)\n+#define TBH_HB_DSC_MEM_DATA_PORT_MASK (9141L)\n+#define TBH_HB_DSC_MEM_DATA_PORT_POS (9142L)\n+#define TBH_HB_DSC_MEM_DATA_SET_CLOCK_POS (9143L)\n+#define TBH_HB_DSC_MEM_DATA_SET_CLOCK_USE (9144L)\n+#define TBH_HB_DSC_MEM_DATA_SW_TFD_TYPE_POS (9145L)\n+#define TBH_HB_DSC_MEM_DATA_SW_TFD_TYPE_USE (9146L)\n+#define TBH_HB_DSC_MEM_DATA_TS_APPEND (9147L)\n+#define TBH_HB_DSC_MEM_DATA_TS_FMT (9148L)\n+#define TBH_HB_DSC_MEM_DATA_TS_INJECT_POS (9149L)\n+#define TBH_HB_DSC_MEM_DATA_TS_INJECT_USE (9150L)\n+#define TBH_HB_DSC_MEM_DATA_TX_NOW_POS (9151L)\n+#define TBH_HB_DSC_MEM_DATA_TX_NOW_USE (9152L)\n+#define TBH_HB_DSC_MEM_DATA_TX_ON_TS (9153L)\n+#define TBH_HB_DSC_MEM_DATA_WL_USE (9154L)\n+#define TBH_HB_INFO_MEM_CTRL (9155L)\n+#define TBH_HB_INFO_MEM_CTRL_A (9156L)\n+#define TBH_HB_INFO_MEM_CTRL_CNT (9157L)\n+#define TBH_HB_INFO_MEM_DATA (9158L)\n+#define TBH_HB_INFO_MEM_DATA_SIZE (9159L)\n+#define TBH_HB_PORTS_MEM_CTRL (9160L)\n+#define TBH_HB_PORTS_MEM_CTRL_A (9161L)\n+#define TBH_HB_PORTS_MEM_CTRL_CNT (9162L)\n+#define TBH_HB_PORTS_MEM_DATA (9163L)\n+#define TBH_HB_PORTS_MEM_DATA_MAPPING (9164L)\n+#define TBH_PORT_MAPPING (9165L)\n+#define TBH_PORT_MAPPING_P0 (9166L)\n+#define TBH_PORT_MAPPING_P1 (9167L)\n+#define TBH_PORT_MAPPING_P2 (9168L)\n+#define TBH_PORT_MAPPING_P3 (9169L)\n+#define TBH_PORT_MAPPING_P4 (9170L)\n+#define TBH_PORT_MAPPING_P5 (9171L)\n+#define TBH_PORT_MAPPING_P6 (9172L)\n+#define TBH_PORT_MAPPING_P7 (9173L)\n+#define TBH_SET_RD_POINTER (9174L)\n+#define TBH_SET_RD_POINTER_HB (9175L)\n+#define TBH_SET_RD_POINTER_OFFSET (9176L)\n+#define TBH_STATUS (9177L)\n+#define TBH_STATUS_STOPPED (9178L)\n+/* TEMPMON */\n+#define TEMPMON_ALARMS (9179L)\n+#define TEMPMON_ALARMS_OT (9180L)\n+#define TEMPMON_ALARMS_OT_OVERWR (9181L)\n+#define TEMPMON_ALARMS_OT_OVERWRVAL (9182L)\n+#define TEMPMON_ALARMS_TEMP (9183L)\n+#define TEMPMON_STAT (9184L)\n+#define TEMPMON_STAT_TEMP (9185L)\n+/* TINT */\n+#define TINT_CTRL (9186L)\n+#define TINT_CTRL_INTERVAL (9187L)\n+#define TINT_STATUS (9188L)\n+#define TINT_STATUS_DELAYED (9189L)\n+#define TINT_STATUS_SKIPPED (9190L)\n+/* TMC */\n+#define TMC_PORT_RPL (9191L)\n+#define TMC_PORT_RPL_P0 (9192L)\n+#define TMC_PORT_RPL_P1 (9193L)\n+#define TMC_PORT_RPL_P2 (9194L)\n+#define TMC_PORT_RPL_P3 (9195L)\n+#define TMC_PORT_RPL_P4 (9196L)\n+#define TMC_PORT_RPL_P5 (9197L)\n+#define TMC_PORT_RPL_P6 (9198L)\n+#define TMC_PORT_RPL_P7 (9199L)\n+/* TSM */\n+#define TSM_ADJ_FINE_N (9200L)\n+#define TSM_ADJ_FINE_N_2DY (9201L)\n+#define TSM_ADJ_FINE_N_2DY2DX (9202L)\n+#define TSM_ADJ_FINE_P (9203L)\n+#define TSM_ADJ_FINE_P_2DY (9204L)\n+#define TSM_ADJ_FINE_P_2DY2DX (9205L)\n+#define TSM_ADJ_LIMIT_HI (9206L)\n+#define TSM_ADJ_LIMIT_HI_LIMIT (9207L)\n+#define TSM_ADJ_LIMIT_LO (9208L)\n+#define TSM_ADJ_LIMIT_LO_LIMIT (9209L)\n+#define TSM_BASIC_2DY (9210L)\n+#define TSM_BASIC_2DY_2DY (9211L)\n+#define TSM_BASIC_2DY2DX (9212L)\n+#define TSM_BASIC_2DY2DX_2DY2DX (9213L)\n+#define TSM_CON0_CONFIG (9214L)\n+#define TSM_CON0_CONFIG_BLIND (9215L)\n+#define TSM_CON0_CONFIG_DC_SRC (9216L)\n+#define TSM_CON0_CONFIG_PORT (9217L)\n+#define TSM_CON0_CONFIG_PPSIN_2_5V (9218L)\n+#define TSM_CON0_CONFIG_SAMPLE_EDGE (9219L)\n+#define TSM_CON0_INTERFACE (9220L)\n+#define TSM_CON0_INTERFACE_EX_TERM (9221L)\n+#define TSM_CON0_INTERFACE_IN_REF_PWM (9222L)\n+#define TSM_CON0_INTERFACE_PWM_ENA (9223L)\n+#define TSM_CON0_INTERFACE_RESERVED (9224L)\n+#define TSM_CON0_INTERFACE_VTERM_PWM (9225L)\n+#define TSM_CON0_SAMPLE_HI (9226L)\n+#define TSM_CON0_SAMPLE_HI_SEC (9227L)\n+#define TSM_CON0_SAMPLE_LO (9228L)\n+#define TSM_CON0_SAMPLE_LO_NS (9229L)\n+#define TSM_CON1_CONFIG (9230L)\n+#define TSM_CON1_CONFIG_BLIND (9231L)\n+#define TSM_CON1_CONFIG_DC_SRC (9232L)\n+#define TSM_CON1_CONFIG_PORT (9233L)\n+#define TSM_CON1_CONFIG_PPSIN_2_5V (9234L)\n+#define TSM_CON1_CONFIG_SAMPLE_EDGE (9235L)\n+#define TSM_CON1_SAMPLE_HI (9236L)\n+#define TSM_CON1_SAMPLE_HI_SEC (9237L)\n+#define TSM_CON1_SAMPLE_LO (9238L)\n+#define TSM_CON1_SAMPLE_LO_NS (9239L)\n+#define TSM_CON2_CONFIG (9240L)\n+#define TSM_CON2_CONFIG_BLIND (9241L)\n+#define TSM_CON2_CONFIG_DC_SRC (9242L)\n+#define TSM_CON2_CONFIG_PORT (9243L)\n+#define TSM_CON2_CONFIG_PPSIN_2_5V (9244L)\n+#define TSM_CON2_CONFIG_SAMPLE_EDGE (9245L)\n+#define TSM_CON2_SAMPLE_HI (9246L)\n+#define TSM_CON2_SAMPLE_HI_SEC (9247L)\n+#define TSM_CON2_SAMPLE_LO (9248L)\n+#define TSM_CON2_SAMPLE_LO_NS (9249L)\n+#define TSM_CON3_CONFIG (9250L)\n+#define TSM_CON3_CONFIG_BLIND (9251L)\n+#define TSM_CON3_CONFIG_PORT (9252L)\n+#define TSM_CON3_CONFIG_SAMPLE_EDGE (9253L)\n+#define TSM_CON3_SAMPLE_HI (9254L)\n+#define TSM_CON3_SAMPLE_HI_SEC (9255L)\n+#define TSM_CON3_SAMPLE_LO (9256L)\n+#define TSM_CON3_SAMPLE_LO_NS (9257L)\n+#define TSM_CON4_CONFIG (9258L)\n+#define TSM_CON4_CONFIG_BLIND (9259L)\n+#define TSM_CON4_CONFIG_PORT (9260L)\n+#define TSM_CON4_CONFIG_SAMPLE_EDGE (9261L)\n+#define TSM_CON4_SAMPLE_HI (9262L)\n+#define TSM_CON4_SAMPLE_HI_SEC (9263L)\n+#define TSM_CON4_SAMPLE_LO (9264L)\n+#define TSM_CON4_SAMPLE_LO_NS (9265L)\n+#define TSM_CON5_CONFIG (9266L)\n+#define TSM_CON5_CONFIG_BLIND (9267L)\n+#define TSM_CON5_CONFIG_PORT (9268L)\n+#define TSM_CON5_CONFIG_SAMPLE_EDGE (9269L)\n+#define TSM_CON5_SAMPLE_HI (9270L)\n+#define TSM_CON5_SAMPLE_HI_SEC (9271L)\n+#define TSM_CON5_SAMPLE_LO (9272L)\n+#define TSM_CON5_SAMPLE_LO_TIME (9273L)\n+#define TSM_CON6_CONFIG (9274L)\n+#define TSM_CON6_CONFIG_BLIND (9275L)\n+#define TSM_CON6_CONFIG_PORT (9276L)\n+#define TSM_CON6_CONFIG_SAMPLE_EDGE (9277L)\n+#define TSM_CON6_SAMPLE_HI (9278L)\n+#define TSM_CON6_SAMPLE_HI_SEC (9279L)\n+#define TSM_CON6_SAMPLE_LO (9280L)\n+#define TSM_CON6_SAMPLE_LO_NS (9281L)\n+#define TSM_CON7_HOST_SAMPLE_HI (9282L)\n+#define TSM_CON7_HOST_SAMPLE_HI_SEC (9283L)\n+#define TSM_CON7_HOST_SAMPLE_LO (9284L)\n+#define TSM_CON7_HOST_SAMPLE_LO_NS (9285L)\n+#define TSM_CONFIG (9286L)\n+#define TSM_CONFIG_NTTS_SRC (9287L)\n+#define TSM_CONFIG_NTTS_SYNC (9288L)\n+#define TSM_CONFIG_TIMESET_EDGE (9289L)\n+#define TSM_CONFIG_TIMESET_SRC (9290L)\n+#define TSM_CONFIG_TIMESET_UP (9291L)\n+#define TSM_CONFIG_TS_FORMAT (9292L)\n+#define TSM_CTRL (9293L)\n+#define TSM_CTRL_DCEN_CON0 (9294L)\n+#define TSM_CTRL_DCEN_CON1 (9295L)\n+#define TSM_CTRL_DCEN_CON2 (9296L)\n+#define TSM_CTRL_FORMAT (9297L)\n+#define TSM_CTRL_HIGH_SAMPLE (9298L)\n+#define TSM_CTRL_LED_CON0 (9299L)\n+#define TSM_CTRL_LED_CON1 (9300L)\n+#define TSM_CTRL_LED_CON2 (9301L)\n+#define TSM_CTRL_OEN_CON0 (9303L)\n+#define TSM_CTRL_OEN_CON1 (9304L)\n+#define TSM_CTRL_OEN_CON2 (9305L)\n+#define TSM_CTRL_PPSEN (9306L)\n+#define TSM_CTRL_PPS_NEGEDGE (9307L)\n+#define TSM_CTRL_PPS_TIME_UP (9308L)\n+#define TSM_CTRL_PTP_TIME_UP (9309L)\n+#define TSM_CTRL_RESERVED (9310L)\n+#define TSM_CTRL_SEL_EXTSRC (9311L)\n+#define TSM_CTRL_SYNEN (9312L)\n+#define TSM_CTRL_TS_CON0 (9313L)\n+#define TSM_CTRL_TS_CON1 (9314L)\n+#define TSM_CTRL_TS_CON2 (9315L)\n+#define TSM_EXT_STAT (9316L)\n+#define TSM_EXT_STAT_STAT (9317L)\n+#define TSM_EXT_TIME_HI (9318L)\n+#define TSM_EXT_TIME_HI_TIME (9319L)\n+#define TSM_EXT_TIME_LO (9320L)\n+#define TSM_EXT_TIME_LO_TIME (9321L)\n+#define TSM_INTERFACE (9322L)\n+#define TSM_INTERFACE_EX_TERM (9323L)\n+#define TSM_INTERFACE_IN_REF_PWM (9324L)\n+#define TSM_INTERFACE_PWM_ENA (9325L)\n+#define TSM_INTERFACE_RESERVED (9326L)\n+#define TSM_INTERFACE_VTERM_PWM (9327L)\n+#define TSM_INT_CONFIG (9328L)\n+#define TSM_INT_CONFIG_AUTO_DISABLE (9329L)\n+#define TSM_INT_CONFIG_MASK (9330L)\n+#define TSM_INT_STAT (9331L)\n+#define TSM_INT_STAT_CAUSE (9332L)\n+#define TSM_INT_STAT_ENABLE (9333L)\n+#define TSM_INT_TIME_HI (9334L)\n+#define TSM_INT_TIME_HI_TIME (9335L)\n+#define TSM_INT_TIME_LO (9336L)\n+#define TSM_INT_TIME_LO_TIME (9337L)\n+#define TSM_LED (9338L)\n+#define TSM_LED_LED0_BG_COLOR (9339L)\n+#define TSM_LED_LED0_COLOR (9340L)\n+#define TSM_LED_LED0_MODE (9341L)\n+#define TSM_LED_LED0_SRC (9342L)\n+#define TSM_LED_LED1_BG_COLOR (9343L)\n+#define TSM_LED_LED1_COLOR (9344L)\n+#define TSM_LED_LED1_MODE (9345L)\n+#define TSM_LED_LED1_SRC (9346L)\n+#define TSM_LED_LED2_BG_COLOR (9347L)\n+#define TSM_LED_LED2_COLOR (9348L)\n+#define TSM_LED_LED2_MODE (9349L)\n+#define TSM_LED_LED2_SRC (9350L)\n+#define TSM_NTTS_CONFIG (9351L)\n+#define TSM_NTTS_CONFIG_AUTO_HARDSET (9352L)\n+#define TSM_NTTS_CONFIG_EXT_CLK_ADJ (9353L)\n+#define TSM_NTTS_CONFIG_HIGH_SAMPLE (9354L)\n+#define TSM_NTTS_CONFIG_TS_SRC_FORMAT (9355L)\n+#define TSM_NTTS_CTRL (9356L)\n+#define TSM_NTTS_CTRL_NTTS_CMD (9357L)\n+#define TSM_NTTS_DATA_HI (9358L)\n+#define TSM_NTTS_DATA_HI_DATA (9359L)\n+#define TSM_NTTS_DATA_LO (9360L)\n+#define TSM_NTTS_DATA_LO_DATA (9361L)\n+#define TSM_NTTS_EXT_STAT (9362L)\n+#define TSM_NTTS_LIMIT_HI (9366L)\n+#define TSM_NTTS_LIMIT_HI_SEC (9367L)\n+#define TSM_NTTS_LIMIT_LO (9368L)\n+#define TSM_NTTS_LIMIT_LO_NS (9369L)\n+#define TSM_NTTS_OFFSET (9370L)\n+#define TSM_NTTS_OFFSET_NS (9371L)\n+#define TSM_NTTS_SAMPLE_HI (9372L)\n+#define TSM_NTTS_SAMPLE_HI_SEC (9373L)\n+#define TSM_NTTS_SAMPLE_LO (9374L)\n+#define TSM_NTTS_SAMPLE_LO_NS (9375L)\n+#define TSM_NTTS_STAT (9376L)\n+#define TSM_NTTS_STAT_NTTS_VALID (9377L)\n+#define TSM_NTTS_STAT_SIGNAL_LOST (9378L)\n+#define TSM_NTTS_STAT_SYNC_LOST (9379L)\n+#define TSM_NTTS_TS_T0_HI (9380L)\n+#define TSM_NTTS_TS_T0_HI_TIME (9381L)\n+#define TSM_NTTS_TS_T0_LO (9382L)\n+#define TSM_NTTS_TS_T0_LO_TIME (9383L)\n+#define TSM_NTTS_TS_T0_OFFSET (9384L)\n+#define TSM_NTTS_TS_T0_OFFSET_COUNT (9385L)\n+#define TSM_OFFSET_HI (9386L)\n+#define TSM_OFFSET_HI_OFFSET (9387L)\n+#define TSM_OFFSET_LO (9388L)\n+#define TSM_OFFSET_LO_OFFSET (9389L)\n+#define TSM_PB_CTRL (9390L)\n+#define TSM_PB_CTRL_INSTMEM_WR (9391L)\n+#define TSM_PB_CTRL_RESET (9392L)\n+#define TSM_PB_CTRL_RST (9393L)\n+#define TSM_PB_INSTMEM (9394L)\n+#define TSM_PB_INSTMEM_ADDR (9395L)\n+#define TSM_PB_INSTMEM_DATA (9396L)\n+#define TSM_PB_INSTMEM_MEM_ADDR (9397L)\n+#define TSM_PB_INSTMEM_MEM_DATA (9398L)\n+#define TSM_PI_CTRL_I (9399L)\n+#define TSM_PI_CTRL_I_VAL (9400L)\n+#define TSM_PI_CTRL_KI (9401L)\n+#define TSM_PI_CTRL_KI_GAIN (9402L)\n+#define TSM_PI_CTRL_KP (9403L)\n+#define TSM_PI_CTRL_KP_GAIN (9404L)\n+#define TSM_PI_CTRL_SHL (9405L)\n+#define TSM_PI_CTRL_SHL_VAL (9406L)\n+#define TSM_RSYNC_COUNT (9407L)\n+#define TSM_RSYNC_COUNT_COUNT (9408L)\n+#define TSM_STAT (9409L)\n+#define TSM_STAT_EXT_SRC_OK (9410L)\n+#define TSM_STAT_HARD_SYNC (9411L)\n+#define TSM_STAT_INSYNC (9412L)\n+#define TSM_STAT_LINK_ACTIVE (9413L)\n+#define TSM_STAT_LINK_CON0 (9414L)\n+#define TSM_STAT_LINK_CON1 (9415L)\n+#define TSM_STAT_LINK_CON2 (9416L)\n+#define TSM_STAT_LINK_CON3 (9417L)\n+#define TSM_STAT_LINK_CON4 (9418L)\n+#define TSM_STAT_LINK_CON5 (9419L)\n+#define TSM_STAT_NTTS_INSYNC (9420L)\n+#define TSM_STAT_PTP_MI_PRESENT (9421L)\n+#define TSM_TIMER_CTRL (9422L)\n+#define TSM_TIMER_CTRL_TIMER_EN_T0 (9423L)\n+#define TSM_TIMER_CTRL_TIMER_EN_T1 (9424L)\n+#define TSM_TIMER_CTRL_TRIGGER_SEL (9425L)\n+#define TSM_TIMER_D_T0 (9426L)\n+#define TSM_TIMER_D_T0_MAX_COUNT (9427L)\n+#define TSM_TIMER_T0 (9428L)\n+#define TSM_TIMER_T0_MAX_COUNT (9429L)\n+#define TSM_TIMER_T1 (9430L)\n+#define TSM_TIMER_T1_MAX_COUNT (9431L)\n+#define TSM_TIMESTAMP_HI (9432L)\n+#define TSM_TIMESTAMP_HI_TIME (9433L)\n+#define TSM_TIMESTAMP_LO (9434L)\n+#define TSM_TIMESTAMP_LO_TIME (9435L)\n+#define TSM_TIME_HARDSET_HI (9436L)\n+#define TSM_TIME_HARDSET_HI_TIME (9437L)\n+#define TSM_TIME_HARDSET_LO (9438L)\n+#define TSM_TIME_HARDSET_LO_TIME (9439L)\n+#define TSM_TIME_HI (9440L)\n+#define TSM_TIME_HI_SEC (9441L)\n+#define TSM_TIME_HI_TIME (9442L)\n+#define TSM_TIME_LO (9443L)\n+#define TSM_TIME_LO_NS (9444L)\n+#define TSM_TIME_RATE_ADJ (9445L)\n+#define TSM_TIME_RATE_ADJ_FRACTION (9446L)\n+#define TSM_TS_HI (9447L)\n+#define TSM_TS_HI_TIME (9448L)\n+#define TSM_TS_LO (9449L)\n+#define TSM_TS_LO_TIME (9450L)\n+#define TSM_TS_OFFSET (9451L)\n+#define TSM_TS_OFFSET_NS (9452L)\n+#define TSM_TS_STAT (9453L)\n+#define TSM_TS_STAT_OVERRUN (9454L)\n+#define TSM_TS_STAT_SAMPLES (9455L)\n+#define TSM_TS_STAT_HI_OFFSET (9456L)\n+#define TSM_TS_STAT_HI_OFFSET_NS (9457L)\n+#define TSM_TS_STAT_LO_OFFSET (9458L)\n+#define TSM_TS_STAT_LO_OFFSET_NS (9459L)\n+#define TSM_TS_STAT_TAR_HI (9460L)\n+#define TSM_TS_STAT_TAR_HI_SEC (9461L)\n+#define TSM_TS_STAT_TAR_LO (9462L)\n+#define TSM_TS_STAT_TAR_LO_NS (9463L)\n+#define TSM_TS_STAT_X (9464L)\n+#define TSM_TS_STAT_X_NS (9465L)\n+#define TSM_TS_STAT_X2_HI (9466L)\n+#define TSM_TS_STAT_X2_HI_NS (9467L)\n+#define TSM_TS_STAT_X2_LO (9468L)\n+#define TSM_TS_STAT_X2_LO_NS (9469L)\n+#define TSM_UTC_OFFSET (9470L)\n+#define TSM_UTC_OFFSET_SEC (9471L)\n+\n+#endif /* _NTHW_FPGA_REGISTERS_DEFS_ */\n", "prefixes": [ "v13", "1/8" ] }