Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/131418/?format=api
{ "id": 131418, "url": "http://patchwork.dpdk.org/api/patches/131418/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230914123615.1705654-6-david.marchand@redhat.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230914123615.1705654-6-david.marchand@redhat.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230914123615.1705654-6-david.marchand@redhat.com", "date": "2023-09-14T12:36:04", "name": "[v3,05/15] pci: define some capability constants", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5e4d5635781cb4f2e96240166112e884e2825b81", "submitter": { "id": 1173, "url": "http://patchwork.dpdk.org/api/people/1173/?format=api", "name": "David Marchand", "email": "david.marchand@redhat.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230914123615.1705654-6-david.marchand@redhat.com/mbox/", "series": [ { "id": 29507, "url": "http://patchwork.dpdk.org/api/series/29507/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29507", "date": "2023-09-14T12:35:59", "name": "Cleanup PCI(e) drivers", "version": 3, "mbox": "http://patchwork.dpdk.org/series/29507/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131418/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/131418/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D760142597;\n\tThu, 14 Sep 2023 14:37:05 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 13474406FF;\n\tThu, 14 Sep 2023 14:36:52 +0200 (CEST)", "from us-smtp-delivery-124.mimecast.com\n (us-smtp-delivery-124.mimecast.com [170.10.129.124])\n by mails.dpdk.org (Postfix) with ESMTP id 783ED406FF\n for <dev@dpdk.org>; Thu, 14 Sep 2023 14:36:50 +0200 (CEST)", "from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com\n [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS\n (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n us-mta-599-E5wuUDXnORWUPcST2xd4gg-1; Thu, 14 Sep 2023 08:36:43 -0400", "from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com\n [10.11.54.6])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by mimecast-mx02.redhat.com (Postfix) with ESMTPS id ED707101FAA3;\n Thu, 14 Sep 2023 12:36:41 +0000 (UTC)", "from dmarchan.redhat.com (unknown [10.45.225.25])\n by smtp.corp.redhat.com (Postfix) with ESMTP id 9A44921B2413;\n Thu, 14 Sep 2023 12:36:38 +0000 (UTC)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1694695010;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=jRVNFr9PreRFFcAf2TR4k+BvH2uHmIaM2IPPDQcYgyw=;\n b=bPFAhZu/Usk8JQk/Kwha4BGi2ce/MYRH3AENNmm6jMxuIHsIJhaQQDflul1KsFOpgt7OnC\n EDXaz84uWT1ph9xaOcjdQFe9DShVG7v5hvXwP7rfBEABI6sLMby16SnKAEuFPXII91C9AQ\n lbjZ66V2BfHKsPWlKp9lSarLHhRvXQE=", "X-MC-Unique": "E5wuUDXnORWUPcST2xd4gg-1", "From": "David Marchand <david.marchand@redhat.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com,\n nipun.gupta@amd.com, bruce.richardson@intel.com,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Jay Zhou <jianjay.zhou@huawei.com>,\n Abdullah Sevincer <abdullah.sevincer@intel.com>,\n Julien Aube <julien_dpdk@jaube.fr>,\n Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>,\n Junfeng Guo <junfeng.guo@intel.com>, Jeroen de Borst <jeroendb@google.com>,\n Rushil Gupta <rushilg@google.com>, Joshua Washington <joshwash@google.com>,\n Dongdong Liu <liudongdong3@huawei.com>,\n Yisen Zhuang <yisen.zhuang@huawei.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Xiao Wang <xiao.w.wang@intel.com>, Gaetan Rivet <grive@u256.net>", "Subject": "[PATCH v3 05/15] pci: define some capability constants", "Date": "Thu, 14 Sep 2023 14:36:04 +0200", "Message-ID": "<20230914123615.1705654-6-david.marchand@redhat.com>", "In-Reply-To": "<20230914123615.1705654-1-david.marchand@redhat.com>", "References": "<20230803075038.307012-1-david.marchand@redhat.com>\n <20230914123615.1705654-1-david.marchand@redhat.com>", "MIME-Version": "1.0", "X-Scanned-By": "MIMEDefang 3.1 on 10.11.54.6", "X-Mimecast-Spam-Score": "0", "X-Mimecast-Originator": "redhat.com", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain; charset=\"US-ASCII\"; x-default=true", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Define some PCI capability constants and use them in existing drivers.\n\nAcked-by: Bruce Richardson <bruce.richardson@intel.com>\nReviewed-by: Chenbo Xia <chenbo.xia@intel.com>\nSigned-off-by: David Marchand <david.marchand@redhat.com>\n---\nChanges since v2:\n- adjusted virtio drivers after changes in previous patch,\n\n---\n drivers/bus/pci/linux/pci_vfio.c | 2 +-\n drivers/crypto/virtio/virtio_pci.c | 14 +++-----------\n drivers/event/dlb2/pf/dlb2_main.c | 6 ++----\n drivers/net/bnx2x/bnx2x.c | 16 ++++++++--------\n drivers/net/bnx2x/bnx2x.h | 4 ----\n drivers/net/cxgbe/base/adapter.h | 3 +--\n drivers/net/gve/gve_ethdev.c | 2 +-\n drivers/net/gve/gve_ethdev.h | 2 +-\n drivers/net/hns3/hns3_ethdev_vf.c | 2 +-\n drivers/net/virtio/virtio_pci.c | 14 +++-----------\n drivers/vdpa/ifc/base/ifcvf_osdep.h | 4 +++-\n lib/pci/rte_pci.h | 5 +++++\n 12 files changed, 29 insertions(+), 45 deletions(-)", "diff": "diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c\nindex 614ed5d696..bfedbc1bed 100644\n--- a/drivers/bus/pci/linux/pci_vfio.c\n+++ b/drivers/bus/pci/linux/pci_vfio.c\n@@ -112,7 +112,7 @@ pci_vfio_get_msix_bar(const struct rte_pci_device *dev,\n {\n \toff_t cap_offset;\n \n-\tcap_offset = rte_pci_find_capability(dev, PCI_CAP_ID_MSIX);\n+\tcap_offset = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);\n \tif (cap_offset < 0)\n \t\treturn -1;\n \ndiff --git a/drivers/crypto/virtio/virtio_pci.c b/drivers/crypto/virtio/virtio_pci.c\nindex 19afebdcad..8f4c6bddbe 100644\n--- a/drivers/crypto/virtio/virtio_pci.c\n+++ b/drivers/crypto/virtio/virtio_pci.c\n@@ -14,14 +14,6 @@\n #include \"virtio_pci.h\"\n #include \"virtqueue.h\"\n \n-/*\n- * Following macros are derived from linux/pci_regs.h, however,\n- * we can't simply include that header here, as there is no such\n- * file for non-Linux platform.\n- */\n-#define PCI_CAP_ID_VNDR\t\t0x09\n-#define PCI_CAP_ID_MSIX\t\t0x11\n-\n /*\n * The remaining space is defined by each driver as the per-driver\n * configuration space.\n@@ -356,7 +348,7 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw)\n \t * Transitional devices would also have this capability,\n \t * that's why we also check if msix is enabled.\n \t */\n-\tpos = rte_pci_find_capability(dev, PCI_CAP_ID_MSIX);\n+\tpos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);\n \tif (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags),\n \t\t\tpos + 2) == sizeof(flags)) {\n \t\tif (flags & PCI_MSIX_ENABLE)\n@@ -367,7 +359,7 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw)\n \t\thw->use_msix = VIRTIO_MSIX_NONE;\n \t}\n \n-\tpos = rte_pci_find_capability(dev, PCI_CAP_ID_VNDR);\n+\tpos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_VNDR);\n \twhile (pos > 0) {\n \t\tif (rte_pci_read_config(dev, &cap, sizeof(cap), pos) != sizeof(cap))\n \t\t\tbreak;\n@@ -396,7 +388,7 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw)\n \t\t\tbreak;\n \t\t}\n \n-\t\tpos = rte_pci_find_next_capability(dev, PCI_CAP_ID_VNDR, pos);\n+\t\tpos = rte_pci_find_next_capability(dev, RTE_PCI_CAP_ID_VNDR, pos);\n \t}\n \n \tif (hw->common_cfg == NULL || hw->notify_base == NULL ||\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex 40e5cb594f..1a229baee0 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -38,8 +38,6 @@\n #define DLB2_PCI_EXP_DEVSTA_TRPND 0x20\n #define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000\n \n-#define DLB2_PCI_CAP_ID_EXP 0x10\n-#define DLB2_PCI_CAP_ID_MSIX 0x11\n #define DLB2_PCI_EXT_CAP_ID_PRI 0x13\n #define DLB2_PCI_EXT_CAP_ID_ACS 0xD\n \n@@ -244,7 +242,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\treturn ret;\n \t}\n \n-\tpcie_cap_offset = rte_pci_find_capability(pdev, DLB2_PCI_CAP_ID_EXP);\n+\tpcie_cap_offset = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_EXP);\n \n \tif (pcie_cap_offset < 0) {\n \t\tDLB2_LOG_ERR(\"[%s()] failed to find the pcie capability\\n\",\n@@ -483,7 +481,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t}\n \t}\n \n-\tmsix_cap_offset = rte_pci_find_capability(pdev, DLB2_PCI_CAP_ID_MSIX);\n+\tmsix_cap_offset = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_MSIX);\n \tif (msix_cap_offset >= 0) {\n \t\toff = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;\n \t\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\ndiff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c\nindex 06f2949885..8a97de8806 100644\n--- a/drivers/net/bnx2x/bnx2x.c\n+++ b/drivers/net/bnx2x/bnx2x.c\n@@ -7613,7 +7613,7 @@ static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)\n \tstruct bnx2x_pci_cap *caps;\n \n \t/* ensure PCIe capability is enabled */\n-\tcaps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);\n+\tcaps = pci_find_cap(sc, RTE_PCI_CAP_ID_EXP, BNX2X_PCI_CAP);\n \tif (NULL != caps) {\n \t\tPMD_DRV_LOG(DEBUG, sc, \"Found PCIe capability: \"\n \t\t\t \"id=0x%04X type=0x%04X addr=0x%08X\",\n@@ -7647,7 +7647,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)\n \tint reg = 0;\n \n \t/* check if PCI Power Management is enabled */\n-\tcaps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);\n+\tcaps = pci_find_cap(sc, RTE_PCI_CAP_ID_PM, BNX2X_PCI_CAP);\n \tif (NULL != caps) {\n \t\tPMD_DRV_LOG(DEBUG, sc, \"Found PM capability: \"\n \t\t\t \"id=0x%04X type=0x%04X addr=0x%08X\",\n@@ -7669,7 +7669,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)\n \tsc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;\n \n \t/* check if MSI capability is enabled */\n-\tcaps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);\n+\tcaps = pci_find_cap(sc, RTE_PCI_CAP_ID_MSI, BNX2X_PCI_CAP);\n \tif (NULL != caps) {\n \t\tPMD_DRV_LOG(DEBUG, sc, \"Found MSI capability at 0x%04x\", reg);\n \n@@ -7678,7 +7678,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)\n \t}\n \n \t/* check if MSI-X capability is enabled */\n-\tcaps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);\n+\tcaps = pci_find_cap(sc, RTE_PCI_CAP_ID_MSIX, BNX2X_PCI_CAP);\n \tif (NULL != caps) {\n \t\tPMD_DRV_LOG(DEBUG, sc, \"Found MSI-X capability at 0x%04x\", reg);\n \n@@ -9587,10 +9587,10 @@ static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)\n }\n \n static uint8_t bnx2x_pci_capabilities[] = {\n-\tPCIY_EXPRESS,\n-\tPCIY_PMG,\n-\tPCIY_MSI,\n-\tPCIY_MSIX,\n+\tRTE_PCI_CAP_ID_EXP,\n+\tRTE_PCI_CAP_ID_PM,\n+\tRTE_PCI_CAP_ID_MSI,\n+\tRTE_PCI_CAP_ID_MSIX,\n };\n \n static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 89414ac88a..07ef0567c2 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -33,10 +33,6 @@\n #ifndef RTE_EXEC_ENV_FREEBSD\n #include <linux/pci_regs.h>\n \n-#define PCIY_PMG PCI_CAP_ID_PM\n-#define PCIY_MSI PCI_CAP_ID_MSI\n-#define PCIY_EXPRESS PCI_CAP_ID_EXP\n-#define PCIY_MSIX PCI_CAP_ID_MSIX\n #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC\n #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND\n #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA\ndiff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h\nindex 00d7591ea4..7bee5cf3a8 100644\n--- a/drivers/net/cxgbe/base/adapter.h\n+++ b/drivers/net/cxgbe/base/adapter.h\n@@ -511,8 +511,7 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,\n \tCXGBE_WRITE_REG64(adapter, reg_addr, val);\n }\n \n-/* Offset of first capability list entry */\n-#define PCI_CAP_ID_EXP 0x10 /* PCI Express */\n+#define PCI_CAP_ID_EXP RTE_PCI_CAP_ID_EXP\n #define PCI_EXP_DEVCTL 0x0008 /* Device control */\n #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */\n #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */\ndiff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex c276b9e68e..9ea5dbaeea 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -609,7 +609,7 @@ gve_teardown_device_resources(struct gve_priv *priv)\n static int\n pci_dev_msix_vec_count(struct rte_pci_device *pdev)\n {\n-\toff_t msix_pos = rte_pci_find_capability(pdev, PCI_CAP_ID_MSIX);\n+\toff_t msix_pos = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_MSIX);\n \tuint16_t control;\n \n \tif (msix_pos > 0 && rte_pci_read_config(pdev, &control, sizeof(control),\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex 8759b1c76e..d604a75b7f 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -8,6 +8,7 @@\n #include <ethdev_driver.h>\n #include <ethdev_pci.h>\n #include <rte_ether.h>\n+#include <rte_pci.h>\n \n #include \"base/gve.h\"\n \n@@ -19,7 +20,6 @@\n * we can't simply include that header here, as there is no such\n * file for non-Linux platform.\n */\n-#define PCI_CAP_ID_MSIX\t\t0x11\t/* MSI-X */\n #define PCI_MSIX_FLAGS\t\t2\t/* Message Control */\n #define PCI_MSIX_FLAGS_QSIZE\t0x07FF\t/* Table size */\n \ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex b731850b01..eab5c55f5e 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -61,7 +61,7 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op)\n \t\treturn 0;\n \t}\n \n-\tpos = rte_pci_find_capability(device, PCI_CAP_ID_MSIX);\n+\tpos = rte_pci_find_capability(device, RTE_PCI_CAP_ID_MSIX);\n \tif (pos > 0) {\n \t\tret = rte_pci_read_config(device, &control, sizeof(control),\n \t\t\tpos + PCI_MSIX_FLAGS);\ndiff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c\nindex 4c2a1911d1..ffdacecd6d 100644\n--- a/drivers/net/virtio/virtio_pci.c\n+++ b/drivers/net/virtio/virtio_pci.c\n@@ -15,14 +15,6 @@\n #include \"virtio_logs.h\"\n #include \"virtqueue.h\"\n \n-/*\n- * Following macros are derived from linux/pci_regs.h, however,\n- * we can't simply include that header here, as there is no such\n- * file for non-Linux platform.\n- */\n-#define PCI_CAP_ID_VNDR\t\t0x09\n-#define PCI_CAP_ID_MSIX\t\t0x11\n-\n /*\n * The remaining space is defined by each driver as the per-driver\n * configuration space.\n@@ -40,7 +32,7 @@ vtpci_msix_detect(struct rte_pci_device *dev)\n \tuint16_t flags;\n \toff_t pos;\n \n-\tpos = rte_pci_find_capability(dev, PCI_CAP_ID_MSIX);\n+\tpos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);\n \tif (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags),\n \t\t\tpos + 2) == sizeof(flags)) {\n \t\tif (flags & PCI_MSIX_ENABLE)\n@@ -607,7 +599,7 @@ virtio_read_caps(struct rte_pci_device *pci_dev, struct virtio_hw *hw)\n \t */\n \tdev->msix_status = vtpci_msix_detect(pci_dev);\n \n-\tpos = rte_pci_find_capability(pci_dev, PCI_CAP_ID_VNDR);\n+\tpos = rte_pci_find_capability(pci_dev, RTE_PCI_CAP_ID_VNDR);\n \twhile (pos > 0) {\n \t\tif (rte_pci_read_config(pci_dev, &cap, sizeof(cap), pos) != sizeof(cap))\n \t\t\tbreak;\n@@ -637,7 +629,7 @@ virtio_read_caps(struct rte_pci_device *pci_dev, struct virtio_hw *hw)\n \t\t\tbreak;\n \t\t}\n \n-\t\tpos = rte_pci_find_next_capability(pci_dev, PCI_CAP_ID_VNDR, pos);\n+\t\tpos = rte_pci_find_next_capability(pci_dev, RTE_PCI_CAP_ID_VNDR, pos);\n \t}\n \n \tif (dev->common_cfg == NULL || dev->notify_base == NULL ||\ndiff --git a/drivers/vdpa/ifc/base/ifcvf_osdep.h b/drivers/vdpa/ifc/base/ifcvf_osdep.h\nindex 6444d7f72c..dd2ff08f77 100644\n--- a/drivers/vdpa/ifc/base/ifcvf_osdep.h\n+++ b/drivers/vdpa/ifc/base/ifcvf_osdep.h\n@@ -6,7 +6,6 @@\n #define _IFCVF_OSDEP_H_\n \n #include <stdint.h>\n-#include <linux/pci_regs.h>\n \n #include <rte_cycles.h>\n #include <rte_pci.h>\n@@ -35,6 +34,9 @@ typedef struct rte_pci_device PCI_DEV;\n #define PCI_READ_CONFIG_DWORD(dev, val, where) \\\n \trte_pci_read_config(dev, val, 4, where)\n \n+#define PCI_CAPABILITY_LIST RTE_PCI_CAPABILITY_LIST\n+#define PCI_CAP_ID_VNDR RTE_PCI_CAP_ID_VNDR\n+\n typedef uint8_t u8;\n typedef int8_t s8;\n typedef uint16_t u16;\ndiff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h\nindex a6a38462cb..8e030caef2 100644\n--- a/lib/pci/rte_pci.h\n+++ b/lib/pci/rte_pci.h\n@@ -44,6 +44,11 @@ extern \"C\" {\n #define RTE_PCI_STATUS_CAP_LIST\t\t0x10\t/* Support Capability List */\n \n /* Capability registers (RTE_PCI_CAPABILITY_LIST) */\n+#define RTE_PCI_CAP_ID_PM\t\t0x01\t/* Power Management */\n+#define RTE_PCI_CAP_ID_MSI\t\t0x05\t/* Message Signalled Interrupts */\n+#define RTE_PCI_CAP_ID_VNDR\t\t0x09\t/* Vendor-Specific */\n+#define RTE_PCI_CAP_ID_EXP\t\t0x10\t/* PCI Express */\n+#define RTE_PCI_CAP_ID_MSIX\t\t0x11\t/* MSI-X */\n #define RTE_PCI_CAP_SIZEOF\t\t4\n #define RTE_PCI_CAP_NEXT\t\t1\n \n", "prefixes": [ "v3", "05/15" ] }