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GET /api/patches/131419/?format=api
{ "id": 131419, "url": "http://patchwork.dpdk.org/api/patches/131419/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230914123615.1705654-7-david.marchand@redhat.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230914123615.1705654-7-david.marchand@redhat.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230914123615.1705654-7-david.marchand@redhat.com", "date": "2023-09-14T12:36:05", "name": "[v3,06/15] pci: define some MSIX constants", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "76d56efbe0909bc5f531d2bcff1a16afd9918a50", "submitter": { "id": 1173, "url": "http://patchwork.dpdk.org/api/people/1173/?format=api", "name": "David Marchand", "email": "david.marchand@redhat.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230914123615.1705654-7-david.marchand@redhat.com/mbox/", "series": [ { "id": 29507, "url": "http://patchwork.dpdk.org/api/series/29507/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29507", "date": "2023-09-14T12:35:59", "name": "Cleanup PCI(e) drivers", "version": 3, "mbox": "http://patchwork.dpdk.org/series/29507/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131419/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/131419/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AE6E742597;\n\tThu, 14 Sep 2023 14:37:13 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2FBBA40A76;\n\tThu, 14 Sep 2023 14:36:54 +0200 (CEST)", "from us-smtp-delivery-124.mimecast.com\n (us-smtp-delivery-124.mimecast.com [170.10.129.124])\n by mails.dpdk.org (Postfix) with ESMTP id 6BDDD40395\n for <dev@dpdk.org>; Thu, 14 Sep 2023 14:36:51 +0200 (CEST)", "from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com\n [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS\n (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n us-mta-665-s4us6c3tPOCUCzrIZkO3Qw-1; Thu, 14 Sep 2023 08:36:48 -0400", "from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com\n [10.11.54.2])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by mimecast-mx02.redhat.com (Postfix) with ESMTPS id EF24218056AA;\n Thu, 14 Sep 2023 12:36:46 +0000 (UTC)", "from dmarchan.redhat.com (unknown [10.45.225.25])\n by smtp.corp.redhat.com (Postfix) with ESMTP id 0D58140C6EA8;\n Thu, 14 Sep 2023 12:36:43 +0000 (UTC)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1694695011;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=HiB3UMAZ6f4hIdtX0iC5S6OJ5BtSqpjLesrstmUAKSw=;\n b=UsleCi0cvO8uJIvQJsviO0qeLBBQI/O1D2gT10Wz6unCfVqUAJdJHBwcLWvRJ1+/ZV+sd9\n GartHzZPktb80EwLvdjpZ8tpwJsCWZB0CqMiITctRRE/UiCWAvfKA1gJoRBvJu1Q6wrEtZ\n b6jpXesam3JcwYWam1ShqCZUNC2Utl8=", "X-MC-Unique": "s4us6c3tPOCUCzrIZkO3Qw-1", "From": "David Marchand <david.marchand@redhat.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com,\n nipun.gupta@amd.com, bruce.richardson@intel.com,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Jay Zhou <jianjay.zhou@huawei.com>,\n Abdullah Sevincer <abdullah.sevincer@intel.com>,\n Julien Aube <julien_dpdk@jaube.fr>, Junfeng Guo <junfeng.guo@intel.com>,\n Jeroen de Borst <jeroendb@google.com>, Rushil Gupta <rushilg@google.com>,\n Joshua Washington <joshwash@google.com>,\n Dongdong Liu <liudongdong3@huawei.com>,\n Yisen Zhuang <yisen.zhuang@huawei.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>, Gaetan Rivet <grive@u256.net>", "Subject": "[PATCH v3 06/15] pci: define some MSIX constants", "Date": "Thu, 14 Sep 2023 14:36:05 +0200", "Message-ID": "<20230914123615.1705654-7-david.marchand@redhat.com>", "In-Reply-To": "<20230914123615.1705654-1-david.marchand@redhat.com>", "References": "<20230803075038.307012-1-david.marchand@redhat.com>\n <20230914123615.1705654-1-david.marchand@redhat.com>", "MIME-Version": "1.0", "X-Scanned-By": "MIMEDefang 3.1 on 10.11.54.2", "X-Mimecast-Spam-Score": "0", "X-Mimecast-Originator": "redhat.com", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain; charset=\"US-ASCII\"; x-default=true", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Define some PCI MSIX constants and use them in existing drivers.\n\nSigned-off-by: David Marchand <david.marchand@redhat.com>\nAcked-by: Bruce Richardson <bruce.richardson@intel.com>\nReviewed-by: Chenbo Xia <chenbo.xia@intel.com>\n---\n drivers/bus/pci/linux/pci_init.h | 18 ------------------\n drivers/bus/pci/linux/pci_vfio.c | 7 ++++---\n drivers/crypto/virtio/virtio_pci.c | 6 ++----\n drivers/event/dlb2/pf/dlb2_main.c | 13 +++++--------\n drivers/net/bnx2x/bnx2x.c | 4 ++--\n drivers/net/bnx2x/bnx2x.h | 2 --\n drivers/net/gve/gve_ethdev.c | 4 ++--\n drivers/net/gve/gve_ethdev.h | 8 --------\n drivers/net/hns3/hns3_ethdev_vf.c | 9 ++++-----\n drivers/net/virtio/virtio_pci.c | 6 ++----\n lib/pci/rte_pci.h | 10 ++++++++++\n 11 files changed, 31 insertions(+), 56 deletions(-)", "diff": "diff --git a/drivers/bus/pci/linux/pci_init.h b/drivers/bus/pci/linux/pci_init.h\nindex d842809ccd..a4d37c0d0a 100644\n--- a/drivers/bus/pci/linux/pci_init.h\n+++ b/drivers/bus/pci/linux/pci_init.h\n@@ -52,24 +52,6 @@ int pci_uio_ioport_unmap(struct rte_pci_ioport *p);\n \n #ifdef VFIO_PRESENT\n \n-#ifdef PCI_MSIX_TABLE_BIR\n-#define RTE_PCI_MSIX_TABLE_BIR PCI_MSIX_TABLE_BIR\n-#else\n-#define RTE_PCI_MSIX_TABLE_BIR 0x7\n-#endif\n-\n-#ifdef PCI_MSIX_TABLE_OFFSET\n-#define RTE_PCI_MSIX_TABLE_OFFSET PCI_MSIX_TABLE_OFFSET\n-#else\n-#define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8\n-#endif\n-\n-#ifdef PCI_MSIX_FLAGS_QSIZE\n-#define RTE_PCI_MSIX_FLAGS_QSIZE PCI_MSIX_FLAGS_QSIZE\n-#else\n-#define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff\n-#endif\n-\n /* access config space */\n int pci_vfio_read_config(const struct rte_pci_device *dev,\n \t\t\t void *buf, size_t len, off_t offs);\ndiff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c\nindex bfedbc1bed..7881b7a946 100644\n--- a/drivers/bus/pci/linux/pci_vfio.c\n+++ b/drivers/bus/pci/linux/pci_vfio.c\n@@ -120,14 +120,15 @@ pci_vfio_get_msix_bar(const struct rte_pci_device *dev,\n \t\tuint16_t flags;\n \t\tuint32_t reg;\n \n-\t\t/* table offset resides in the next 4 bytes */\n-\t\tif (rte_pci_read_config(dev, ®, sizeof(reg), cap_offset + 4) < 0) {\n+\t\tif (rte_pci_read_config(dev, ®, sizeof(reg), cap_offset +\n+\t\t\t\tRTE_PCI_MSIX_TABLE) < 0) {\n \t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\"Cannot read MSIX table from PCI config space!\\n\");\n \t\t\treturn -1;\n \t\t}\n \n-\t\tif (rte_pci_read_config(dev, &flags, sizeof(flags), cap_offset + 2) < 0) {\n+\t\tif (rte_pci_read_config(dev, &flags, sizeof(flags), cap_offset +\n+\t\t\t\tRTE_PCI_MSIX_FLAGS) < 0) {\n \t\t\tRTE_LOG(ERR, EAL,\n \t\t\t\t\"Cannot read MSIX flags from PCI config space!\\n\");\n \t\t\treturn -1;\ndiff --git a/drivers/crypto/virtio/virtio_pci.c b/drivers/crypto/virtio/virtio_pci.c\nindex 8f4c6bddbe..eca8a2a69d 100644\n--- a/drivers/crypto/virtio/virtio_pci.c\n+++ b/drivers/crypto/virtio/virtio_pci.c\n@@ -329,8 +329,6 @@ get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)\n \treturn base + offset;\n }\n \n-#define PCI_MSIX_ENABLE 0x8000\n-\n static int\n virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw)\n {\n@@ -350,8 +348,8 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw)\n \t */\n \tpos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);\n \tif (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags),\n-\t\t\tpos + 2) == sizeof(flags)) {\n-\t\tif (flags & PCI_MSIX_ENABLE)\n+\t\t\tpos + RTE_PCI_MSIX_FLAGS) == sizeof(flags)) {\n+\t\tif (flags & RTE_PCI_MSIX_FLAGS_ENABLE)\n \t\t\thw->use_msix = VIRTIO_MSIX_ENABLED;\n \t\telse\n \t\t\thw->use_msix = VIRTIO_MSIX_DISABLED;\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex 1a229baee0..c6606a9bee 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -44,9 +44,6 @@\n #define DLB2_PCI_PRI_CTRL_ENABLE 0x1\n #define DLB2_PCI_PRI_ALLOC_REQ 0xC\n #define DLB2_PCI_PRI_CTRL 0x4\n-#define DLB2_PCI_MSIX_FLAGS 0x2\n-#define DLB2_PCI_MSIX_FLAGS_ENABLE 0x8000\n-#define DLB2_PCI_MSIX_FLAGS_MASKALL 0x4000\n #define DLB2_PCI_ERR_ROOT_STATUS 0x30\n #define DLB2_PCI_ERR_COR_STATUS 0x10\n #define DLB2_PCI_ERR_UNCOR_STATUS 0x4\n@@ -483,10 +480,10 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \n \tmsix_cap_offset = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_MSIX);\n \tif (msix_cap_offset >= 0) {\n-\t\toff = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;\n+\t\toff = msix_cap_offset + RTE_PCI_MSIX_FLAGS;\n \t\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\n-\t\t\tcmd |= DLB2_PCI_MSIX_FLAGS_ENABLE;\n-\t\t\tcmd |= DLB2_PCI_MSIX_FLAGS_MASKALL;\n+\t\t\tcmd |= RTE_PCI_MSIX_FLAGS_ENABLE;\n+\t\t\tcmd |= RTE_PCI_MSIX_FLAGS_MASKALL;\n \t\t\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n \t\t\t\tDLB2_LOG_ERR(\"[%s()] failed to write msix flags\\n\",\n \t\t\t\t __func__);\n@@ -494,9 +491,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t\t\t}\n \t\t}\n \n-\t\toff = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;\n+\t\toff = msix_cap_offset + RTE_PCI_MSIX_FLAGS;\n \t\tif (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {\n-\t\t\tcmd &= ~DLB2_PCI_MSIX_FLAGS_MASKALL;\n+\t\t\tcmd &= ~RTE_PCI_MSIX_FLAGS_MASKALL;\n \t\t\tif (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {\n \t\t\t\tDLB2_LOG_ERR(\"[%s()] failed to write msix flags\\n\",\n \t\t\t\t __func__);\ndiff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c\nindex 8a97de8806..e3f14400cc 100644\n--- a/drivers/net/bnx2x/bnx2x.c\n+++ b/drivers/net/bnx2x/bnx2x.c\n@@ -9766,9 +9766,9 @@ int bnx2x_attach(struct bnx2x_softc *sc)\n \tif (sc->devinfo.pcie_msix_cap_reg != 0) {\n \t\tuint32_t val;\n \t\tpci_read(sc,\n-\t\t\t (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,\n+\t\t\t (sc->devinfo.pcie_msix_cap_reg + RTE_PCI_MSIX_FLAGS), &val,\n \t\t\t 2);\n-\t\tsc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;\n+\t\tsc->igu_sb_cnt = (val & RTE_PCI_MSIX_FLAGS_QSIZE) + 1;\n \t} else {\n \t\tsc->igu_sb_cnt = 1;\n \t}\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 07ef0567c2..60af75d336 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -46,8 +46,6 @@\n #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS\n #define PCIM_PSTAT_D3 0x3\n #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE\n-#define PCIR_MSIX_CTRL PCI_MSIX_FLAGS\n-#define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE\n #else\n #include <dev/pci/pcireg.h>\n #endif\ndiff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex 9ea5dbaeea..9b25f3036b 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -613,8 +613,8 @@ pci_dev_msix_vec_count(struct rte_pci_device *pdev)\n \tuint16_t control;\n \n \tif (msix_pos > 0 && rte_pci_read_config(pdev, &control, sizeof(control),\n-\t\t\tmsix_pos + PCI_MSIX_FLAGS) == sizeof(control))\n-\t\treturn (control & PCI_MSIX_FLAGS_QSIZE) + 1;\n+\t\t\tmsix_pos + RTE_PCI_MSIX_FLAGS) == sizeof(control))\n+\t\treturn (control & RTE_PCI_MSIX_FLAGS_QSIZE) + 1;\n \n \treturn 0;\n }\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex d604a75b7f..c47b4d454d 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -15,14 +15,6 @@\n /* TODO: this is a workaround to ensure that Tx complq is enough */\n #define DQO_TX_MULTIPLIER 4\n \n-/*\n- * Following macros are derived from linux/pci_regs.h, however,\n- * we can't simply include that header here, as there is no such\n- * file for non-Linux platform.\n- */\n-#define PCI_MSIX_FLAGS\t\t2\t/* Message Control */\n-#define PCI_MSIX_FLAGS_QSIZE\t0x07FF\t/* Table size */\n-\n #define GVE_DEFAULT_RX_FREE_THRESH 512\n #define GVE_DEFAULT_TX_FREE_THRESH 32\n #define GVE_DEFAULT_TX_RS_THRESH 32\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex eab5c55f5e..3729615159 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -2,7 +2,6 @@\n * Copyright(c) 2018-2021 HiSilicon Limited.\n */\n \n-#include <linux/pci_regs.h>\n #include <rte_alarm.h>\n #include <ethdev_pci.h>\n #include <rte_io.h>\n@@ -64,18 +63,18 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op)\n \tpos = rte_pci_find_capability(device, RTE_PCI_CAP_ID_MSIX);\n \tif (pos > 0) {\n \t\tret = rte_pci_read_config(device, &control, sizeof(control),\n-\t\t\tpos + PCI_MSIX_FLAGS);\n+\t\t\tpos + RTE_PCI_MSIX_FLAGS);\n \t\tif (ret < 0) {\n \t\t\tPMD_INIT_LOG(ERR, \"Failed to read MSIX flags\");\n \t\t\treturn -ENXIO;\n \t\t}\n \n \t\tif (op)\n-\t\t\tcontrol |= PCI_MSIX_FLAGS_ENABLE;\n+\t\t\tcontrol |= RTE_PCI_MSIX_FLAGS_ENABLE;\n \t\telse\n-\t\t\tcontrol &= ~PCI_MSIX_FLAGS_ENABLE;\n+\t\t\tcontrol &= ~RTE_PCI_MSIX_FLAGS_ENABLE;\n \t\tret = rte_pci_write_config(device, &control, sizeof(control),\n-\t\t\tpos + PCI_MSIX_FLAGS);\n+\t\t\tpos + RTE_PCI_MSIX_FLAGS);\n \t\tif (ret < 0) {\n \t\t\tPMD_INIT_LOG(ERR, \"failed to write MSIX flags\");\n \t\t\treturn -ENXIO;\ndiff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c\nindex ffdacecd6d..90bbb53502 100644\n--- a/drivers/net/virtio/virtio_pci.c\n+++ b/drivers/net/virtio/virtio_pci.c\n@@ -24,8 +24,6 @@\n \n struct virtio_pci_internal virtio_pci_internal[RTE_MAX_ETHPORTS];\n \n-#define PCI_MSIX_ENABLE 0x8000\n-\n static enum virtio_msix_status\n vtpci_msix_detect(struct rte_pci_device *dev)\n {\n@@ -34,8 +32,8 @@ vtpci_msix_detect(struct rte_pci_device *dev)\n \n \tpos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);\n \tif (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags),\n-\t\t\tpos + 2) == sizeof(flags)) {\n-\t\tif (flags & PCI_MSIX_ENABLE)\n+\t\t\tpos + RTE_PCI_MSIX_FLAGS) == sizeof(flags)) {\n+\t\tif (flags & RTE_PCI_MSIX_FLAGS_ENABLE)\n \t\t\treturn VIRTIO_MSIX_ENABLED;\n \t\telse\n \t\t\treturn VIRTIO_MSIX_DISABLED;\ndiff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h\nindex 8e030caef2..650dbb7645 100644\n--- a/lib/pci/rte_pci.h\n+++ b/lib/pci/rte_pci.h\n@@ -52,6 +52,16 @@ extern \"C\" {\n #define RTE_PCI_CAP_SIZEOF\t\t4\n #define RTE_PCI_CAP_NEXT\t\t1\n \n+/* MSI-X registers (RTE_PCI_CAP_ID_MSIX) */\n+#define RTE_PCI_MSIX_FLAGS\t\t2\t/* Message Control */\n+#define RTE_PCI_MSIX_FLAGS_QSIZE\t0x07ff\t/* Table size */\n+#define RTE_PCI_MSIX_FLAGS_MASKALL\t0x4000\t/* Mask all vectors for this function */\n+#define RTE_PCI_MSIX_FLAGS_ENABLE\t0x8000\t/* MSI-X enable */\n+\n+#define RTE_PCI_MSIX_TABLE\t\t4\t/* Table offset */\n+#define RTE_PCI_MSIX_TABLE_BIR\t\t0x00000007 /* BAR index */\n+#define RTE_PCI_MSIX_TABLE_OFFSET\t0xfffffff8 /* Offset into specified BAR */\n+\n /* PCI Express capability registers */\n #define RTE_PCI_EXP_DEVCTL\t8\t/* Device Control */\n \n", "prefixes": [ "v3", "06/15" ] }