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GET /api/patches/131502/?format=api
{ "id": 131502, "url": "http://patchwork.dpdk.org/api/patches/131502/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230915091551.1459606-28-chaoyong.he@corigine.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230915091551.1459606-28-chaoyong.he@corigine.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230915091551.1459606-28-chaoyong.he@corigine.com", "date": "2023-09-15T09:15:51", "name": "[v3,27/27] net/nfp: extend the usage of nfp BAR from 8 to 24", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9b3825a14460bb81afae7240f752a569b6a4d9b1", "submitter": { "id": 2554, "url": "http://patchwork.dpdk.org/api/people/2554/?format=api", "name": "Chaoyong He", "email": "chaoyong.he@corigine.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230915091551.1459606-28-chaoyong.he@corigine.com/mbox/", "series": [ { "id": 29520, "url": "http://patchwork.dpdk.org/api/series/29520/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29520", "date": "2023-09-15T09:15:24", "name": "refact the nfpcore module", "version": 3, "mbox": "http://patchwork.dpdk.org/series/29520/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131502/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/131502/checks/", "tags": {}, "related": [], "headers": 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"Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=corigine.com;", "From": "Chaoyong He <chaoyong.he@corigine.com>", "To": "dev@dpdk.org", "Cc": "oss-drivers@corigine.com, Chaoyong He <chaoyong.he@corigine.com>,\n\t=?utf-8?q?Niklas_S=C3=B6derlund?= <niklas.soderlund@corigine.com>", "Subject": "[PATCH v3 27/27] net/nfp: extend the usage of nfp BAR from 8 to 24", "Date": "Fri, 15 Sep 2023 17:15:51 +0800", "Message-Id": "<20230915091551.1459606-28-chaoyong.he@corigine.com>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20230915091551.1459606-1-chaoyong.he@corigine.com>", "References": "<20230830021457.2064750-1-chaoyong.he@corigine.com>\n <20230915091551.1459606-1-chaoyong.he@corigine.com>", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-ClientProxiedBy": "PH7PR10CA0017.namprd10.prod.outlook.com\n (2603:10b6:510:23d::10) To SJ0PR13MB5545.namprd13.prod.outlook.com\n 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"=?utf-8?q?nnro/0hbCBCAUDphYB9ffry7Kuq/?=\n\t=?utf-8?q?bQfhNmfv4XPVdmlakhPAYEJezcJWY2Si+FSFpR0g/61DxxDSUnnEh2Ko+M5mGUqSY?=\n\t=?utf-8?q?wJXG28EAcGb8O06jfUIk85zAI5+EqfcJcRQGluPxe28H16aySrTpdyK2sMlKodcRW?=\n\t=?utf-8?q?CYK1iEjez/czgaYM06F4Kfux/9DY+LF04xZGoji0OdyY8VutYNYkMj19k54yxp+2z?=\n\t=?utf-8?q?dfuQ4HN52y4Qu/x7zrannzzmeowj0tPRzy8/1X+wgA0XcjKOBQV3i90bJXf96PDNt?=\n\t=?utf-8?q?ATmd9YEmrEplzKpjj2HJnnJU/tkyKD3S361T3bleEgiKBAVol5Bgy7MZ3P1ZgtprN?=\n\t=?utf-8?q?0Dwdr12280zRZfOmVNdPPDTh3tY2zQOkiomvFXcpIuiM7HNoaxDZh+cQhOX3w5Yi/?=\n\t=?utf-8?q?I21WQCO/8CMy2kx+bbr7CawTlOtu9aM2s4N3KTcmNC7zvFGwc+WwZM8BB1Ggz7IqA?=\n\t=?utf-8?q?pekGvLqtNgTMyRxtW1bnl3EGE3A3+SKHRlimkqsLnVikEE6u3vxSQmVVGkPjmSwiF?=\n\t=?utf-8?q?e3/XeijxMIMVv0kkypyQ4DnpywBSZ44nf5u6KppuG2SFesoKARnlFC1qyhPUdqu5H?=\n\t=?utf-8?q?Eyxq/2jFLATCMcq3M8Z7dLcaTDXo8/5CN/Vo52gH+kf0HiIt8nRf6cuZXNxyxM5Of?=\n\t=?utf-8?q?vfRigbgxwfAniQsKcUf49UjPJ6aHgJn0nAXl+QbAvG0YrJ8YKKB9CSgy3ZzM+M/fX?=\n\t=?utf-8?q?sZjloQ/UOXNwoJ266GDUwnFZZGdiFphi3uiG4kPy4TRU2cGE6U3pi+ZuK3rVxqZ1D?=\n\t=?utf-8?q?MbE2PJvW+WmoWVbePlETfpmVTtlj2xnI7Ial5Mt7s7uMXZlx8F9rJ9LNXigagDTYW?=\n\t=?utf-8?q?pMkBLcDObyff0jvoj5vwrLl9cAULbDVaHZ1agqKAm9zGTzB8pmdgHue5y9y0GKZfK?=\n\t=?utf-8?q?Umg26HEiUo8riIIU2hLuZ71pvjq86QPpJCU5he+boye3aRVPCgLMN6y9d55FK4aVp?=\n\t=?utf-8?q?JubjfYm3pHG4Lr1Eh+KYAvxdtiDDG+9SWUmvWH7Zfjg8Db/0u0DxPxuOyssPbKSqG?=\n\t=?utf-8?q?R7Pv/NthTrl/e20oXF9OfUKcfhgOv0jBW90AZushbqxYCqcJIfIBmxjyOBCTBSKNP?=\n\t=?utf-8?q?5pP/lVWwddSwDwJUJ7xs0DLbf60OFhBzvzBBjwKm31DqPZVT9gpd+z/i5Q1DYmbJv?=\n\t=?utf-8?q?uJbKUEJNoyc1AN3X1IhwsXPrwyvDcS/T8V4eO2Hi+wbQCrUdBE5WybMWKyeJr2EyG?=\n\t=?utf-8?q?C9c2graQZq2XrXlabWWL6BcBkY3bh2iCD15/HALInyfe/dZlKo3geG4dbqhqMSq/k?=\n\t=?utf-8?q?95DTSbXfbAlmXK0w22+aMrI1LPIGEqAD4V78tEOoFTx7v13Vp41U9sdDfU4LSjOWr?=\n\t=?utf-8?q?CivnRMFqTeeeC1h72AC6SEr4sTURW131YJNI8IiLRCUrHsO1KI1GSWz6uM5k6C8gE?=\n\t=?utf-8?q?xtFCyw7yDth0hre1H7vm1h+d+Iip7R8Wd2CTXIW4M3WqvOcq1dCCn2CGqQp0g/H5s?=\n\t=?utf-8?q?Z22B4fT0g46MEdUNGhPLj73U254Bz721j/wqfJI2Kno6trTQeH97Y+cmLKItENfNB?=\n\t=?utf-8?q?PJ5pd5V1E5NCWSxC7jG/ZqY1mz2jnvPCLw=3D=3D?=", "X-OriginatorOrg": "corigine.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 77566d6e-6eee-4b20-075e-08dbb5cc8b0d", "X-MS-Exchange-CrossTenant-AuthSource": "SJ0PR13MB5545.namprd13.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Sep 2023 09:17:11.6845 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "fe128f2c-073b-4c20-818e-7246a585940c", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n CyWjOd3xpiYxO8xpd/pwKVvm04t0EG0jBReCV6WHz/Rr8oatVLwhR+b8/n3PwnU4l0ksO5E5zbDrF7vnAg2oOEk/biGqbj9DpaTwvOydnuk=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR13MB6387", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Sync the logic from kernel driver, adjust the definition of structure,\nand extend the usage of nfp BAR from 8 to 24.\n\nThis will greatly enhance the scalability of nfp PMD.\n\nSigned-off-by: Chaoyong He <chaoyong.he@corigine.com>\nReviewed-by: Niklas Söderlund <niklas.soderlund@corigine.com>\n---\n drivers/net/nfp/nfp_ethdev.c | 8 +-\n drivers/net/nfp/nfpcore/nfp6000_pcie.c | 478 ++++++++++++++++++-------\n drivers/net/nfp/nfpcore/nfp6000_pcie.h | 1 +\n drivers/net/nfp/nfpcore/nfp_cpp.h | 5 +-\n drivers/net/nfp/nfpcore/nfp_cppcore.c | 2 +-\n 5 files changed, 349 insertions(+), 145 deletions(-)", "diff": "diff --git a/drivers/net/nfp/nfp_ethdev.c b/drivers/net/nfp/nfp_ethdev.c\nindex 6eefec3836..d6454d8964 100644\n--- a/drivers/net/nfp/nfp_ethdev.c\n+++ b/drivers/net/nfp/nfp_ethdev.c\n@@ -918,9 +918,9 @@ nfp_pf_init(struct rte_pci_device *pci_dev)\n \t * use a lock file if UIO is being used.\n \t */\n \tif (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)\n-\t\tcpp = nfp_cpp_from_nfp6000_pcie(pci_dev, false);\n+\t\tcpp = nfp_cpp_from_nfp6000_pcie(pci_dev, dev_info, false);\n \telse\n-\t\tcpp = nfp_cpp_from_nfp6000_pcie(pci_dev, true);\n+\t\tcpp = nfp_cpp_from_nfp6000_pcie(pci_dev, dev_info, true);\n \n \tif (cpp == NULL) {\n \t\tPMD_INIT_LOG(ERR, \"A CPP handle can not be obtained\");\n@@ -1121,9 +1121,9 @@ nfp_pf_secondary_init(struct rte_pci_device *pci_dev)\n \t * use a lock file if UIO is being used.\n \t */\n \tif (pci_dev->kdrv == RTE_PCI_KDRV_VFIO)\n-\t\tcpp = nfp_cpp_from_nfp6000_pcie(pci_dev, false);\n+\t\tcpp = nfp_cpp_from_nfp6000_pcie(pci_dev, dev_info, false);\n \telse\n-\t\tcpp = nfp_cpp_from_nfp6000_pcie(pci_dev, true);\n+\t\tcpp = nfp_cpp_from_nfp6000_pcie(pci_dev, dev_info, true);\n \n \tif (cpp == NULL) {\n \t\tPMD_INIT_LOG(ERR, \"A CPP handle can not be obtained\");\ndiff --git a/drivers/net/nfp/nfpcore/nfp6000_pcie.c b/drivers/net/nfp/nfpcore/nfp6000_pcie.c\nindex e32ac1107c..709177a80e 100644\n--- a/drivers/net/nfp/nfpcore/nfp6000_pcie.c\n+++ b/drivers/net/nfp/nfpcore/nfp6000_pcie.c\n@@ -19,6 +19,8 @@\n #include <unistd.h>\n #include <fcntl.h>\n \n+#include <rte_io.h>\n+\n #include \"nfp_cpp.h\"\n #include \"nfp_logs.h\"\n #include \"nfp_target.h\"\n@@ -59,20 +61,12 @@\n #define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4))\n #define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4))\n \n-#define NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(id, bar, slot) \\\n-\t(NFP_PCIE_BAR(id) + ((bar) * 8 + (slot)) * 4)\n-\n-#define NFP_PCIE_CPP_BAR_PCIETOCPPEXPBAR(bar, slot) \\\n-\t(((bar) * 8 + (slot)) * 4)\n+#define NFP_PCIE_P2C_EXPBAR_OFFSET(bar_index) ((bar_index) * 4)\n \n struct nfp_pcie_user;\n struct nfp6000_area_priv;\n \n /* Describes BAR configuration and usage */\n-#define NFP_BAR_MIN 1\n-#define NFP_BAR_MID 5\n-#define NFP_BAR_MAX 7\n-\n struct nfp_bar {\n \tstruct nfp_pcie_user *nfp; /**< Backlink to owner */\n \tuint32_t barcfg; /**< BAR config CSR */\n@@ -80,22 +74,26 @@ struct nfp_bar {\n \tuint64_t mask; /**< Mask of the BAR aperture (read only) */\n \tuint32_t bitsize; /**< Bit size of the BAR aperture (read only) */\n \tuint32_t index; /**< Index of the BAR */\n-\tint lock; /**< If the BAR has been locked */\n+\tbool lock; /**< If the BAR has been locked */\n \n-\tchar *csr;\n \tchar *iomem; /**< mapped IO memory */\n+\tstruct rte_mem_resource *resource; /**< IOMEM resource window */\n };\n \n-#define BUSDEV_SZ 13\n+#define NFP_PCI_BAR_MAX (PCI_64BIT_BAR_COUNT * 8)\n+\n struct nfp_pcie_user {\n-\tstruct nfp_bar bar[NFP_BAR_MAX];\n+\tstruct rte_pci_device *pci_dev;\n+\tconst struct nfp_dev_info *dev_info;\n \n-\tint device;\n \tint lock;\n-\tchar busdev[BUSDEV_SZ];\n-\tint barsz;\n-\tint dev_id;\n-\tchar *cfg;\n+\n+\t/* PCI BAR management */\n+\tuint32_t bars;\n+\tstruct nfp_bar bar[NFP_PCI_BAR_MAX];\n+\n+\t/* Reserved BAR access */\n+\tchar *csr;\n };\n \n /* Generic CPP bus access interface. */\n@@ -206,19 +204,19 @@ nfp_bar_write(struct nfp_pcie_user *nfp,\n \t\tstruct nfp_bar *bar,\n \t\tuint32_t newcfg)\n {\n-\tint base;\n-\tint slot;\n-\n-\tbase = bar->index >> 3;\n-\tslot = bar->index & 7;\n+\tuint32_t xbar;\n \n-\tif (nfp->cfg == NULL)\n-\t\treturn (-ENOMEM);\n+\txbar = NFP_PCIE_P2C_EXPBAR_OFFSET(bar->index);\n \n-\tbar->csr = nfp->cfg +\n-\t\t\tNFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(nfp->dev_id, base, slot);\n-\n-\t*(uint32_t *)(bar->csr) = newcfg;\n+\tif (nfp->csr != NULL) {\n+\t\trte_write32(newcfg, nfp->csr + xbar);\n+\t\t/* Readback to ensure BAR is flushed */\n+\t\trte_read32(nfp->csr + xbar);\n+\t} else {\n+\t\txbar += nfp->dev_info->pcie_cfg_expbar_offset;\n+\t\trte_pci_write_config(nfp->pci_dev, &newcfg, sizeof(uint32_t),\n+\t\t\t\txbar);\n+\t}\n \n \tbar->barcfg = newcfg;\n \n@@ -249,105 +247,323 @@ nfp_reconfigure_bar(struct nfp_pcie_user *nfp,\n \treturn nfp_bar_write(nfp, bar, newcfg);\n }\n \n-/*\n- * Map all PCI bars. We assume that the BAR with the PCIe config block is\n- * already mapped.\n+static uint32_t\n+nfp_bitsize_calc(uint64_t mask)\n+{\n+\tuint64_t tmp = mask;\n+\tuint32_t bit_size = 0;\n+\n+\tif (tmp == 0)\n+\t\treturn 0;\n+\n+\tfor (; tmp != 0; tmp >>= 1)\n+\t\tbit_size++;\n+\n+\treturn bit_size;\n+}\n+\n+static int\n+nfp_cmp_bars(const void *ptr_a,\n+\t\tconst void *ptr_b)\n+{\n+\tconst struct nfp_bar *a = ptr_a;\n+\tconst struct nfp_bar *b = ptr_b;\n+\n+\tif (a->bitsize == b->bitsize)\n+\t\treturn a->index - b->index;\n+\telse\n+\t\treturn a->bitsize - b->bitsize;\n+}\n+\n+static bool\n+nfp_bars_for_secondary(uint32_t index)\n+{\n+\tuint8_t tmp = index & 0x07;\n+\n+\tif (tmp == 0x06 || tmp == 0x07)\n+\t\treturn true;\n+\telse\n+\t\treturn false;\n+}\n+\n+/**\n+ * Map all PCI bars and fetch the actual BAR configurations from the board.\n+ * We assume that the BAR with the PCIe config block is already mapped.\n *\n * BAR0.0: Reserved for General Mapping (for MSI-X access to PCIe SRAM)\n+ * BAR0.1: --\n+ * BAR0.2: --\n+ * BAR0.3: --\n+ * BAR0.4: --\n+ * BAR0.5: --\n+ * BAR0.6: --\n+ * BAR0.7: --\n *\n- * Halving PCItoCPPBars for primary and secondary processes.\n- * For CoreNIC firmware:\n- * NFP PMD just requires two fixed slots, one for configuration BAR,\n- * and another for accessing the hw queues. Another slot is needed\n- * for setting the link up or down. Secondary processes do not need\n- * to map the first two slots again, but it requires one slot for\n- * accessing the link, even if it is not likely the secondary process\n- * starting the port.\n- * For Flower firmware:\n- * NFP PMD need another fixed slots, used as the configureation BAR\n- * for ctrl vNIC.\n+ * BAR1.0-BAR1.7: --\n+ * BAR2.0-BAR2.7: --\n */\n static int\n nfp_enable_bars(struct nfp_pcie_user *nfp)\n {\n-\tint x;\n-\tint end;\n-\tint start;\n+\tint pf;\n+\tuint32_t i;\n+\tuint8_t min_bars;\n \tstruct nfp_bar *bar;\n+\tenum rte_proc_type_t type;\n+\tstruct rte_mem_resource *res;\n+\tconst uint32_t barcfg_msix_general = NFP_PCIE_BAR_PCIE2CPP_MAPTYPE\n+\t\t\t(NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_GENERAL) |\n+\t\t\tNFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_32BIT;\n+\n+\ttype = rte_eal_process_type();\n+\tif (type == RTE_PROC_PRIMARY)\n+\t\tmin_bars = 12;\n+\telse\n+\t\tmin_bars = 4;\n+\n+\tfor (i = 0; i < RTE_DIM(nfp->bar); i++) {\n+\t\tif (i != 0) {\n+\t\t\tif (type == RTE_PROC_PRIMARY) {\n+\t\t\t\tif (nfp_bars_for_secondary(i))\n+\t\t\t\t\tcontinue;\n+\t\t\t} else {\n+\t\t\t\tif (!nfp_bars_for_secondary(i))\n+\t\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t}\n \n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\tstart = NFP_BAR_MID;\n-\t\tend = NFP_BAR_MIN;\n-\t} else {\n-\t\tstart = NFP_BAR_MAX;\n-\t\tend = NFP_BAR_MID;\n+\t\t/* 24 NFP bars mapping into BAR0, BAR2 and BAR4 */\n+\t\tres = &nfp->pci_dev->mem_resource[(i >> 3) * 2];\n+\n+\t\t/* Skip over BARs that are not mapped */\n+\t\tif (res->addr != NULL) {\n+\t\t\tbar = &nfp->bar[i];\n+\t\t\tbar->resource = res;\n+\t\t\tbar->barcfg = 0;\n+\n+\t\t\tbar->nfp = nfp;\n+\t\t\tbar->index = i;\n+\t\t\t/* The resource shared by 8 bars */\n+\t\t\tbar->mask = (res->len >> 3) - 1;\n+\t\t\tbar->bitsize = nfp_bitsize_calc(bar->mask);\n+\t\t\tbar->base = 0;\n+\t\t\tbar->lock = false;\n+\t\t\tbar->iomem = (char *)res->addr +\n+\t\t\t\t\t((bar->index & 7) << bar->bitsize);\n+\n+\t\t\tnfp->bars++;\n+\t\t}\n+\t}\n+\n+\tif (nfp->bars < min_bars) {\n+\t\tPMD_DRV_LOG(ERR, \"Not enough usable BARs found.\");\n+\t\treturn -EINVAL;\n \t}\n \n-\tfor (x = start; x > end; x--) {\n-\t\tbar = &nfp->bar[x - 1];\n-\t\tbar->barcfg = 0;\n-\t\tbar->nfp = nfp;\n-\t\tbar->index = x;\n-\t\tbar->mask = (1 << (nfp->barsz - 3)) - 1;\n-\t\tbar->bitsize = nfp->barsz - 3;\n-\t\tbar->base = 0;\n-\t\tbar->iomem = NULL;\n-\t\tbar->lock = 0;\n-\t\tbar->csr = nfp->cfg + NFP_PCIE_CFG_BAR_PCIETOCPPEXPBAR(nfp->dev_id,\n-\t\t\t\tbar->index >> 3, bar->index & 7);\n-\t\tbar->iomem = nfp->cfg + (bar->index << bar->bitsize);\n+\tswitch (nfp->pci_dev->id.device_id) {\n+\tcase PCI_DEVICE_ID_NFP3800_PF_NIC:\n+\t\tpf = nfp->pci_dev->addr.function & 0x07;\n+\t\tnfp->csr = nfp->bar[0].iomem + NFP_PCIE_BAR(pf);\n+\t\tbreak;\n+\tcase PCI_DEVICE_ID_NFP4000_PF_NIC:\n+\tcase PCI_DEVICE_ID_NFP6000_PF_NIC:\n+\t\tnfp->csr = nfp->bar[0].iomem + NFP_PCIE_BAR(0);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Unsupported device ID: %04hx!\",\n+\t\t\t\tnfp->pci_dev->id.device_id);\n+\t\treturn -EINVAL;\n \t}\n+\n+\t/* Configure, and lock, BAR0.0 for General Target use (MSI-X SRAM) */\n+\tbar = &nfp->bar[0];\n+\tbar->lock = true;\n+\n+\tnfp_bar_write(nfp, bar, barcfg_msix_general);\n+\n+\t/* Sort bars by bit size - use the smallest possible first. */\n+\tqsort(&nfp->bar[0], nfp->bars, sizeof(nfp->bar[0]), nfp_cmp_bars);\n+\n \treturn 0;\n }\n \n-static struct nfp_bar *\n-nfp_alloc_bar(struct nfp_pcie_user *nfp)\n+/* Check if BAR can be used with the given parameters. */\n+static bool\n+matching_bar_exist(struct nfp_bar *bar,\n+\t\tint target,\n+\t\tint action,\n+\t\tint token,\n+\t\tuint64_t offset,\n+\t\tsize_t size,\n+\t\tint width)\n {\n-\tint x;\n-\tint end;\n-\tint start;\n-\tstruct nfp_bar *bar;\n+\tint bar_width;\n+\tint bar_token;\n+\tint bar_target;\n+\tint bar_action;\n+\tuint32_t map_type;\n+\n+\tbar_width = NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_OF(bar->barcfg);\n+\tswitch (bar_width) {\n+\tcase NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_32BIT:\n+\t\tbar_width = 4;\n+\t\tbreak;\n+\tcase NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_64BIT:\n+\t\tbar_width = 8;\n+\t\tbreak;\n+\tcase NFP_PCIE_BAR_PCIE2CPP_LENGTHSELECT_0BYTE:\n+\t\tbar_width = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\tbar_width = -1;\n+\t\tbreak;\n+\t}\n \n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\tstart = NFP_BAR_MID;\n-\t\tend = NFP_BAR_MIN;\n-\t} else {\n-\t\tstart = NFP_BAR_MAX;\n-\t\tend = NFP_BAR_MID;\n+\t/* Make sure to match up the width */\n+\tif (bar_width != width)\n+\t\treturn false;\n+\n+\tbar_token = NFP_PCIE_BAR_PCIE2CPP_TOKEN_BASEADDRESS_OF(bar->barcfg);\n+\tbar_action = NFP_PCIE_BAR_PCIE2CPP_ACTION_BASEADDRESS_OF(bar->barcfg);\n+\tmap_type = NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_OF(bar->barcfg);\n+\tswitch (map_type) {\n+\tcase NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_TARGET:\n+\t\tbar_token = -1;\n+\t\t/* FALLTHROUGH */\n+\tcase NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_BULK:\n+\t\tbar_action = NFP_CPP_ACTION_RW;\n+\t\tif (action == 0)\n+\t\t\taction = NFP_CPP_ACTION_RW;\n+\t\t/* FALLTHROUGH */\n+\tcase NFP_PCIE_BAR_PCIE2CPP_MAPTYPE_FIXED:\n+\t\tbreak;\n+\tdefault:\n+\t\t/* We don't match explicit bars through the area interface */\n+\t\treturn false;\n \t}\n \n-\tfor (x = start; x > end; x--) {\n-\t\tbar = &nfp->bar[x - 1];\n-\t\tif (bar->lock == 0) {\n-\t\t\tbar->lock = 1;\n-\t\t\treturn bar;\n-\t\t}\n+\tbar_target = NFP_PCIE_BAR_PCIE2CPP_TARGET_BASEADDRESS_OF(bar->barcfg);\n+\tif ((bar_target < 0 || bar_target == target) &&\n+\t\t\t(bar_token < 0 || bar_token == token) &&\n+\t\t\tbar_action == action &&\n+\t\t\tbar->base <= offset &&\n+\t\t\t(bar->base + (1 << bar->bitsize)) >= (offset + size))\n+\t\treturn true;\n+\n+\t/* No match */\n+\treturn false;\n+}\n+\n+static int\n+find_matching_bar(struct nfp_pcie_user *nfp,\n+\t\tint target,\n+\t\tint action,\n+\t\tint token,\n+\t\tuint64_t offset,\n+\t\tsize_t size,\n+\t\tint width)\n+{\n+\tuint32_t n;\n+\n+\tfor (n = 0; n < nfp->bars; n++) {\n+\t\tstruct nfp_bar *bar = &nfp->bar[n];\n+\n+\t\tif (bar->lock)\n+\t\t\tcontinue;\n+\n+\t\tif (matching_bar_exist(bar, target, action, token,\n+\t\t\t\toffset, size, width))\n+\t\t\treturn n;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+/* Return EAGAIN if no resource is available */\n+static int\n+find_unused_bar_noblock(struct nfp_pcie_user *nfp,\n+\t\tint target,\n+\t\tint action,\n+\t\tint token,\n+\t\tuint64_t offset,\n+\t\tsize_t size,\n+\t\tint width)\n+{\n+\tint ret;\n+\tuint32_t n;\n+\tconst struct nfp_bar *bar;\n+\n+\tfor (n = 0; n < nfp->bars; n++) {\n+\t\tbar = &nfp->bar[n];\n+\n+\t\tif (bar->bitsize == 0)\n+\t\t\tcontinue;\n+\n+\t\t/* Just check to see if we can make it fit... */\n+\t\tret = nfp_compute_bar(bar, NULL, NULL, target, action,\n+\t\t\t\ttoken, offset, size, width);\n+\t\tif (ret != 0)\n+\t\t\tcontinue;\n+\n+\t\tif (!bar->lock)\n+\t\t\treturn n;\n+\t}\n+\n+\treturn -EAGAIN;\n+}\n+\n+static int\n+nfp_alloc_bar(struct nfp_pcie_user *nfp,\n+\t\tstruct nfp6000_area_priv *priv)\n+{\n+\tint ret;\n+\tint bar_num;\n+\tsize_t size = priv->size;\n+\tint token = priv->token;\n+\tint target = priv->target;\n+\tint action = priv->action;\n+\tint width = priv->width.bar;\n+\tuint64_t offset = priv->offset;\n+\n+\t/* Bar size should small than 16MB */\n+\tif (size > (1 << 24))\n+\t\treturn -EINVAL;\n+\n+\tbar_num = find_matching_bar(nfp, target, action, token,\n+\t\t\toffset, size, width);\n+\tif (bar_num >= 0) {\n+\t\t/* Found a perfect match. */\n+\t\tnfp->bar[bar_num].lock = true;\n+\t\treturn bar_num;\n \t}\n \n-\treturn NULL;\n+\tbar_num = find_unused_bar_noblock(nfp, target, action, token,\n+\t\t\toffset, size, width);\n+\tif (bar_num < 0)\n+\t\treturn bar_num;\n+\n+\tnfp->bar[bar_num].lock = true;\n+\tret = nfp_reconfigure_bar(nfp, &nfp->bar[bar_num],\n+\t\t\ttarget, action, token, offset, size, width);\n+\tif (ret < 0) {\n+\t\tnfp->bar[bar_num].lock = false;\n+\t\treturn ret;\n+\t}\n+\n+\treturn bar_num;\n }\n \n static void\n nfp_disable_bars(struct nfp_pcie_user *nfp)\n {\n-\tint x;\n-\tint end;\n-\tint start;\n+\tuint32_t i;\n \tstruct nfp_bar *bar;\n \n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\tstart = NFP_BAR_MID;\n-\t\tend = NFP_BAR_MIN;\n-\t} else {\n-\t\tstart = NFP_BAR_MAX;\n-\t\tend = NFP_BAR_MID;\n-\t}\n-\n-\tfor (x = start; x > end; x--) {\n-\t\tbar = &nfp->bar[x - 1];\n-\t\tif (bar->iomem) {\n+\tfor (i = 0; i < nfp->bars; i++) {\n+\t\tbar = &nfp->bar[i];\n+\t\tif (bar->iomem != NULL) {\n \t\t\tbar->iomem = NULL;\n-\t\t\tbar->lock = 0;\n+\t\t\tbar->lock = false;\n \t\t}\n \t}\n }\n@@ -364,7 +580,6 @@ nfp6000_area_init(struct nfp_cpp_area *area,\n \tuint32_t target = NFP_CPP_ID_TARGET_of(dest);\n \tuint32_t action = NFP_CPP_ID_ACTION_of(dest);\n \tstruct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);\n-\tstruct nfp_pcie_user *nfp = nfp_cpp_priv(nfp_cpp_area_cpp(area));\n \n \tpp = nfp_target_pushpull(NFP_CPP_ID(target, action, token), address);\n \tif (pp < 0)\n@@ -383,9 +598,7 @@ nfp6000_area_init(struct nfp_cpp_area *area,\n \telse\n \t\tpriv->width.bar = priv->width.write;\n \n-\tpriv->bar = nfp_alloc_bar(nfp);\n-\tif (priv->bar == NULL)\n-\t\treturn -ENOMEM;\n+\tpriv->bar = NULL;\n \n \tpriv->target = target;\n \tpriv->action = action;\n@@ -393,17 +606,29 @@ nfp6000_area_init(struct nfp_cpp_area *area,\n \tpriv->offset = address;\n \tpriv->size = size;\n \n-\tret = nfp_reconfigure_bar(nfp, priv->bar, priv->target, priv->action,\n-\t\t\tpriv->token, priv->offset, priv->size,\n-\t\t\tpriv->width.bar);\n-\n \treturn ret;\n }\n \n static int\n nfp6000_area_acquire(struct nfp_cpp_area *area)\n {\n+\tint bar_num;\n \tstruct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);\n+\tstruct nfp_pcie_user *nfp = nfp_cpp_priv(nfp_cpp_area_cpp(area));\n+\n+\t/* Already allocated. */\n+\tif (priv->bar != NULL)\n+\t\treturn 0;\n+\n+\tbar_num = nfp_alloc_bar(nfp, priv);\n+\tif (bar_num < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate bar %d:%d:%d:%#lx: %d\",\n+\t\t\t\tpriv->target, priv->action, priv->token,\n+\t\t\t\tpriv->offset, bar_num);\n+\t\treturn bar_num;\n+\t}\n+\n+\tpriv->bar = &nfp->bar[bar_num];\n \n \t/* Calculate offset into BAR. */\n \tif (nfp_bar_maptype(priv->bar) ==\n@@ -432,7 +657,7 @@ nfp6000_area_release(struct nfp_cpp_area *area)\n {\n \tstruct nfp6000_area_priv *priv = nfp_cpp_area_priv(area);\n \n-\tpriv->bar->lock = 0;\n+\tpriv->bar->lock = false;\n \tpriv->bar = NULL;\n \tpriv->iomem = NULL;\n }\n@@ -603,7 +828,8 @@ nfp_acquire_process_lock(struct nfp_pcie_user *desc)\n \n \tmemset(&lock, 0, sizeof(lock));\n \n-\tsnprintf(lockname, sizeof(lockname), \"/var/lock/nfp_%s\", desc->busdev);\n+\tsnprintf(lockname, sizeof(lockname), \"/var/lock/nfp_%s\",\n+\t\t\tdesc->pci_dev->device.name);\n \tdesc->lock = open(lockname, O_RDWR | O_CREAT, 0666);\n \tif (desc->lock < 0)\n \t\treturn desc->lock;\n@@ -693,32 +919,11 @@ nfp6000_get_serial(struct rte_pci_device *dev,\n }\n \n static int\n-nfp6000_set_barsz(struct rte_pci_device *dev,\n-\t\tstruct nfp_pcie_user *desc)\n-{\n-\tint i = 0;\n-\tuint64_t tmp;\n-\n-\ttmp = dev->mem_resource[0].len;\n-\n-\twhile (tmp >>= 1)\n-\t\ti++;\n-\n-\tdesc->barsz = i;\n-\n-\treturn 0;\n-}\n-\n-static int\n-nfp6000_init(struct nfp_cpp *cpp,\n-\t\tstruct rte_pci_device *dev)\n+nfp6000_init(struct nfp_cpp *cpp)\n {\n \tint ret = 0;\n \tstruct nfp_pcie_user *desc = nfp_cpp_priv(cpp);\n \n-\tmemset(desc->busdev, 0, BUSDEV_SZ);\n-\tstrlcpy(desc->busdev, dev->device.name, sizeof(desc->busdev));\n-\n \tif (rte_eal_process_type() == RTE_PROC_PRIMARY &&\n \t\t\tnfp_cpp_driver_need_lock(cpp)) {\n \t\tret = nfp_acquire_process_lock(desc);\n@@ -726,12 +931,6 @@ nfp6000_init(struct nfp_cpp *cpp,\n \t\t\treturn -1;\n \t}\n \n-\tif (nfp6000_set_barsz(dev, desc) < 0)\n-\t\treturn -1;\n-\n-\tdesc->cfg = dev->mem_resource[0].addr;\n-\tdesc->dev_id = dev->addr.function & 0x7;\n-\n \tret = nfp_enable_bars(desc);\n \tif (ret != 0) {\n \t\tPMD_DRV_LOG(ERR, \"Enable bars failed\");\n@@ -749,7 +948,6 @@ nfp6000_free(struct nfp_cpp *cpp)\n \tnfp_disable_bars(desc);\n \tif (nfp_cpp_driver_need_lock(cpp))\n \t\tclose(desc->lock);\n-\tclose(desc->device);\n \trte_free(desc);\n }\n \n@@ -789,6 +987,7 @@ nfp_cpp_operations *nfp_cpp_transport_operations(void)\n */\n struct nfp_cpp *\n nfp_cpp_from_nfp6000_pcie(struct rte_pci_device *pci_dev,\n+\t\tconst struct nfp_dev_info *dev_info,\n \t\tbool driver_lock_needed)\n {\n \tint ret;\n@@ -800,6 +999,9 @@ nfp_cpp_from_nfp6000_pcie(struct rte_pci_device *pci_dev,\n \tif (nfp == NULL)\n \t\treturn NULL;\n \n+\tnfp->pci_dev = pci_dev;\n+\tnfp->dev_info = dev_info;\n+\n \tret = nfp6000_get_interface(pci_dev, &interface);\n \tif (ret != 0) {\n \t\tPMD_DRV_LOG(ERR, \"Get interface failed.\");\ndiff --git a/drivers/net/nfp/nfpcore/nfp6000_pcie.h b/drivers/net/nfp/nfpcore/nfp6000_pcie.h\nindex 8847f6f946..8e2cfb69e6 100644\n--- a/drivers/net/nfp/nfpcore/nfp6000_pcie.h\n+++ b/drivers/net/nfp/nfpcore/nfp6000_pcie.h\n@@ -14,6 +14,7 @@\n const struct nfp_cpp_operations *nfp_cpp_transport_operations(void);\n \n struct nfp_cpp *nfp_cpp_from_nfp6000_pcie(struct rte_pci_device *pci_dev,\n+\t\tconst struct nfp_dev_info *dev_info,\n \t\tbool driver_lock_needed);\n \n #endif /* __NFP6000_PCIE_H__ */\ndiff --git a/drivers/net/nfp/nfpcore/nfp_cpp.h b/drivers/net/nfp/nfpcore/nfp_cpp.h\nindex e879c7c920..2defc4fa16 100644\n--- a/drivers/net/nfp/nfpcore/nfp_cpp.h\n+++ b/drivers/net/nfp/nfpcore/nfp_cpp.h\n@@ -18,6 +18,8 @@ struct nfp_cpp_area;\n \n #define NFP_CPP_NUM_TARGETS 16\n \n+#define PCI_64BIT_BAR_COUNT 3\n+\n /*\n * NFP CPP operations structure\n */\n@@ -26,8 +28,7 @@ struct nfp_cpp_operations {\n \tsize_t area_priv_size;\n \n \t/* Instance an NFP CPP */\n-\tint (*init)(struct nfp_cpp *cpp,\n-\t\t\tstruct rte_pci_device *dev);\n+\tint (*init)(struct nfp_cpp *cpp);\n \n \t/*\n \t * Free the bus.\ndiff --git a/drivers/net/nfp/nfpcore/nfp_cppcore.c b/drivers/net/nfp/nfpcore/nfp_cppcore.c\nindex d70c8cd44a..92250c150a 100644\n--- a/drivers/net/nfp/nfpcore/nfp_cppcore.c\n+++ b/drivers/net/nfp/nfpcore/nfp_cppcore.c\n@@ -947,7 +947,7 @@ nfp_cpp_alloc(struct rte_pci_device *pci_dev,\n \t * NOTE: cpp_lock is NOT locked for op->init,\n \t * since it may call NFP CPP API operations\n \t */\n-\terr = cpp->op->init(cpp, pci_dev);\n+\terr = cpp->op->init(cpp);\n \tif (err < 0) {\n \t\tPMD_DRV_LOG(ERR, \"NFP interface initialization failed\");\n \t\trte_free(cpp);\n", "prefixes": [ "v3", "27/27" ] }