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GET /api/patches/131563/?format=api
{ "id": 131563, "url": "http://patchwork.dpdk.org/api/patches/131563/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230918120705.265025-2-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230918120705.265025-2-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230918120705.265025-2-igozlan@nvidia.com", "date": "2023-09-18T12:07:02", "name": "[2/5] net/mlx5/hws: support additional 4 C registers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3b3aee7f79ee117824bbd72cff40c4336c63202b", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230918120705.265025-2-igozlan@nvidia.com/mbox/", "series": [ { "id": 29534, "url": "http://patchwork.dpdk.org/api/series/29534/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29534", "date": "2023-09-18T12:07:02", "name": "[1/5] net/mlx5/hws: add support for matching on bth_a bit", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29534/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131563/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/131563/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 06ED3425D1;\n\tMon, 18 Sep 2023 14:07:32 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C4402402E2;\n\tMon, 18 Sep 2023 14:07:31 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id C75034021F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Itamar Gozlan <igozlan@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>, Ori Kam\n <orika@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 2/5] net/mlx5/hws: support additional 4 C registers", "Date": "Mon, 18 Sep 2023 15:07:02 +0300", "Message-ID": "<20230918120705.265025-2-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.38.1", "In-Reply-To": "<20230918120705.265025-1-igozlan@nvidia.com>", "References": "<20230918120705.265025-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9CD:EE_|DS7PR12MB5720:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6caee545-eaa4-4c26-2212-08dbb83fd45e", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n LWnd8gi+tgxW3djiULydC9SmnBJcsASi0OWGwsyiOMXadWG/dHRcCGDopRW9W1Hh+vrDLq2m18sL9xSGMWvhL+RrG+FPjGZxzK06vm7Yg0aIvMptLfyiLtRV7ny4nrWR7vP2ZVsGZOWdGDXj9/jVTiLIXv5ldtXD/ZSc7K2+8OERVFs1WuMfS+bApT2d9dYktTFvTFEdCzC/DkisFSWi8zB1IeriXNcddoPARJ0GgjPzX/o2Jknn2DTsJPixUYmRKZvQvJxeryjqd9PtjumSsUNuBHwP4MU5j+XiJa2LV4/B9rPnnMRBQgelC7MJDPoOCdtYmH/hqayx1OWMJupXjE58s4qQ+WaiShx1zSPEldNL0gLO2T0+Tje3KfomHguyP1LE9kCf1rRhLmu5jAH27oDId/T0MRsUvnOaVK5ai81dL2dpj4JibVMkyq1KxYREA4Lcm8zOvL/urLm3lXvIbN9+rDQhDhF4h7aErd8zwBZTT+qtT6ARi0hK4pfMtNTXHIDFFu5VGykku4dTYEcaMoFfLDtUjdEQnSTats1S2JeF/o5AG7zWA4Wn24nla6vcvJHth+TKddNkXZo4OM0s1LTD9E7Ok5RVCUCEGaDNiw27UwdxiS0dB7b7DocWgxhrddy/eyQ2WMAjp7XOakgDBANNKAo65kAqVWPo6id4HneK+FIW44I91+Qytf+0jVkAAGO+Z5i5nzu3HY/mJzsOt3CAjZ5AbGt6aAEOLTcsG4UDCfGbAOGNmKVe3z82bZ1z", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(136003)(346002)(396003)(376002)(39860400002)(82310400011)(1800799009)(186009)(451199024)(46966006)(36840700001)(40470700004)(7636003)(356005)(26005)(6286002)(82740400003)(2616005)(8936002)(8676002)(4326008)(1076003)(40460700003)(36860700001)(2906002)(36756003)(47076005)(426003)(336012)(40480700001)(55016003)(5660300002)(86362001)(7696005)(478600001)(6666004)(6636002)(316002)(70206006)(70586007)(110136005)(41300700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Sep 2023 12:07:28.7040 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6caee545-eaa4-4c26-2212-08dbb83fd45e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000E9CD.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB5720", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "New connectX devices have 4 additional registers which can be\nused by the application. This support will allow matching on\nthese new registers.\n\nSigned-off-by: Itamar Gozlan <igozlan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 4 ++++\n drivers/net/mlx5/hws/mlx5dr_definer.c | 16 ++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 4 ++++\n 3 files changed, 24 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 51f426c614..4ead9ba2c7 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -857,6 +857,10 @@ enum modify_reg {\n \tREG_C_5,\n \tREG_C_6,\n \tREG_C_7,\n+\tREG_C_8,\n+\tREG_C_9,\n+\tREG_C_10,\n+\tREG_C_11,\n };\n \n /* Modification sub command. */\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex b82af9d102..2f6f91892b 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -1412,6 +1412,22 @@ mlx5dr_definer_get_register_fc(struct mlx5dr_definer_conv_data *cd, int reg)\n \t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_7];\n \t\tDR_CALC_SET_HDR(fc, registers, register_c_7);\n \t\tbreak;\n+\tcase REG_C_8:\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_8];\n+\t\tDR_CALC_SET_HDR(fc, registers, register_c_8);\n+\t\tbreak;\n+\tcase REG_C_9:\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_9];\n+\t\tDR_CALC_SET_HDR(fc, registers, register_c_9);\n+\t\tbreak;\n+\tcase REG_C_10:\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_10];\n+\t\tDR_CALC_SET_HDR(fc, registers, register_c_10);\n+\t\tbreak;\n+\tcase REG_C_11:\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_11];\n+\t\tDR_CALC_SET_HDR(fc, registers, register_c_11);\n+\t\tbreak;\n \tcase REG_A:\n \t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_A];\n \t\tDR_CALC_SET_HDR(fc, metadata, general_purpose);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex bf026fa6bb..f5a541bc17 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -100,6 +100,10 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_REG_5,\n \tMLX5DR_DEFINER_FNAME_REG_6,\n \tMLX5DR_DEFINER_FNAME_REG_7,\n+\tMLX5DR_DEFINER_FNAME_REG_8,\n+\tMLX5DR_DEFINER_FNAME_REG_9,\n+\tMLX5DR_DEFINER_FNAME_REG_10,\n+\tMLX5DR_DEFINER_FNAME_REG_11,\n \tMLX5DR_DEFINER_FNAME_REG_A,\n \tMLX5DR_DEFINER_FNAME_REG_B,\n \tMLX5DR_DEFINER_FNAME_GRE_KEY_PRESENT,\n", "prefixes": [ "2/5" ] }