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GET /api/patches/131741/?format=api
{ "id": 131741, "url": "http://patchwork.dpdk.org/api/patches/131741/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230920133403.6420-8-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230920133403.6420-8-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230920133403.6420-8-hemant.agrawal@nxp.com", "date": "2023-09-20T13:33:57", "name": "[v2,07/13] crypto/dpaa2_sec: enhance dpaa FD FL FMT offset set", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6b40e5ed9ee861c10a21e34edc704db5b6b424c3", "submitter": { "id": 477, "url": "http://patchwork.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230920133403.6420-8-hemant.agrawal@nxp.com/mbox/", "series": [ { "id": 29574, "url": "http://patchwork.dpdk.org/api/series/29574/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29574", "date": "2023-09-20T13:33:50", "name": "crypto/dpaax_sec: misc enhancements", "version": 2, "mbox": "http://patchwork.dpdk.org/series/29574/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131741/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/131741/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2AC70425EA;\n\tWed, 20 Sep 2023 15:36:48 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 239AB42E01;\n\tWed, 20 Sep 2023 15:34:47 +0200 (CEST)", "from EUR03-DBA-obe.outbound.protection.outlook.com\n (mail-dbaeur03on2041.outbound.protection.outlook.com [40.107.104.41])\n by mails.dpdk.org (Postfix) with ESMTP id 7361342DFA\n for <dev@dpdk.org>; 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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=QW2ZvzLgl/C920MdLFKKuHKMvzM+0lbBpgp8tIRB1QE=;\n b=hybSOAGy/lDGOd5g2iesDPpb8e3Cz+oiXJJl/fZilICxQ28P6AIpBSC8AoP46Z75L8Q6Hfx1SjKGepYG6fFRyD/sJ21BEA06fo0ODaQvAJ5deRUZkntopWdexAV2T230e6IMQAABScvt/Kx/ujP2sulI5tl9PTqYJ9TltqEK8QFU3nL7YGOgXK68jWK6uGriU6Mx6t8Y13vT1fdr7KzrRJezPWY7UJ1aLoDP2MNwzKre0kWizJtBF3ntewxHUEba3qCZWhdx0V+YEJemMYLXUHrU+OfKayVdyPp/BigmHhSTRCJd9fuH0kqP90lRmJN8nvQTRaBEea8wDkW/ZKyW7Q==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=QW2ZvzLgl/C920MdLFKKuHKMvzM+0lbBpgp8tIRB1QE=;\n b=GlsFMPVKeefrGjyRR4Wfjkh/Y6u7uQvOFhjgWaNnzyAMo4efTopXqtlUUV2Sj9OowoAmBJPxD2AEkMFWThtjTOTWzNtirkNVJp20oN8UtBQoQxXQmQYyrumFQxFLMaG7/kp4uWfug+XLRWlmxJ0aKallE/X/UJkUc0zBly90L70=", "Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nxp.com;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "gakhil@marvell.com", "Cc": "dev@dpdk.org,\n\tApeksha Gupta <apeksha.gupta@nxp.com>", "Subject": "[PATCH v2 07/13] crypto/dpaa2_sec: enhance dpaa FD FL FMT offset set", "Date": "Wed, 20 Sep 2023 19:03:57 +0530", "Message-Id": "<20230920133403.6420-8-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230920133403.6420-1-hemant.agrawal@nxp.com>", "References": "<20230823070855.27532-1-hemant.agrawal@nxp.com>\n <20230920133403.6420-1-hemant.agrawal@nxp.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "SI2PR01CA0015.apcprd01.prod.exchangelabs.com\n (2603:1096:4:191::15) To PAXPR04MB9328.eurprd04.prod.outlook.com\n (2603:10a6:102:2b6::15)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PAXPR04MB9328:EE_|AS8PR04MB7606:EE_", "X-MS-Office365-Filtering-Correlation-Id": "eb40682b-c026-4ce7-0d9d-08dbb9de51aa", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n EE48ivqb+/hXKl18YTJHimodprQcYRaf0cV2PDCYUk4o20dnELCrCFCw9EW/PN8luGkNZ/r9uUlf7GT707bgwFPAO2e5Cf/+OIBN5+/IiZ1raSR4FkqiOr9S6v8G/cXT17QWknalPCdhwtbzHZM3FZQR3oCv3kIKM4PHTEc/D4RVb3TkhVdqHQ0GInPqs8Abs4U2SYu3/ktaTFv6j7iVUuxD6QTaq+t6AoQM1Pe3opRrmMl4VAwa/UHMe+1qNwUEmGvH9ojexFodPMywywk8qujZRDvvu7gJD9kxlhgSYtY0IP5XHt6yQx7FxfXJsA2swzgb4MmHKD0kbXUMCd8FzJ9x3C8GApbz09ajnRIXwPxJXiLISwf/FaNQM/8+YzvXKguI+yGRzxiOEi2TYIIDhM9z+IceOSaT2VdFQ8GChZ1iVUmqNorEMAKFF+R7vhijfjurFBVeUiQYNBDMVRva+ogBpnn36REgu8JyOv9Siv3mrvzwU8CkgsAsdGuaq+0Vtfj90N0yNNBENUIqnqWnSlLJwc01IVYd/sG3GWJp1Dk+5JlfKJcBpJrqeex9WV3PTRlMlCDlenUW3X8xx8ND3yqqhWMbmI2FcRsxkaOsETWocdk0ekHhGSFRTngogLt8", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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When the offset value is more that 12 bits,\nthis macro may over writing the FMT/SL/F bits which are beyond the\noffset bits.\nThe FLE_ADDR is modified to FLE_ADDR + OFFSET, and the FLE_OFFSET\nis made to 0.\n\nSigned-off-by: Apeksha Gupta <apeksha.gupta@nxp.com>\n---\n drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 87 +++++++--------------\n drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c | 47 +++--------\n drivers/net/dpaa2/dpaa2_rxtx.c | 3 +-\n 3 files changed, 38 insertions(+), 99 deletions(-)", "diff": "diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\nindex 1fc0d2e7cc..daa6a71360 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n@@ -138,16 +138,14 @@ build_proto_compound_sg_fd(dpaa2_sec_session *sess,\n \tDPAA2_SET_FLE_ADDR(op_fle, DPAA2_VADDR_TO_IOVA(sge));\n \n \t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t/* o/p segs */\n \twhile (mbuf->next) {\n \t\tsge->length = mbuf->data_len;\n \t\tout_len += sge->length;\n \t\tsge++;\n \t\tmbuf = mbuf->next;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t}\n \t/* using buf_len for last buf - so that extra data can be added */\n \tsge->length = mbuf->buf_len - mbuf->data_off;\n@@ -165,8 +163,7 @@ build_proto_compound_sg_fd(dpaa2_sec_session *sess,\n \tDPAA2_SET_FLE_FIN(ip_fle);\n \n \t/* Configure input SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \tsge->length = mbuf->data_len;\n \tin_len += sge->length;\n \n@@ -174,8 +171,7 @@ build_proto_compound_sg_fd(dpaa2_sec_session *sess,\n \t/* i/p segs */\n \twhile (mbuf) {\n \t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t\tsge->length = mbuf->data_len;\n \t\tin_len += sge->length;\n \t\tmbuf = mbuf->next;\n@@ -247,13 +243,11 @@ build_proto_compound_fd(dpaa2_sec_session *sess,\n \tDPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));\n \n \t/* Configure Output FLE with dst mbuf data */\n-\tDPAA2_SET_FLE_ADDR(op_fle, DPAA2_MBUF_VADDR_TO_IOVA(dst_mbuf));\n-\tDPAA2_SET_FLE_OFFSET(op_fle, dst_mbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(op_fle, rte_pktmbuf_iova(dst_mbuf));\n \tDPAA2_SET_FLE_LEN(op_fle, dst_mbuf->buf_len);\n \n \t/* Configure Input FLE with src mbuf data */\n-\tDPAA2_SET_FLE_ADDR(ip_fle, DPAA2_MBUF_VADDR_TO_IOVA(src_mbuf));\n-\tDPAA2_SET_FLE_OFFSET(ip_fle, src_mbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(ip_fle, rte_pktmbuf_iova(src_mbuf));\n \tDPAA2_SET_FLE_LEN(ip_fle, src_mbuf->pkt_len);\n \n \tDPAA2_SET_FD_LEN(fd, ip_fle->length);\n@@ -373,16 +367,14 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess,\n \t\t\tsym_op->aead.data.length;\n \n \t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off + sym_op->aead.data.offset);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf) + sym_op->aead.data.offset);\n \tsge->length = mbuf->data_len - sym_op->aead.data.offset;\n \n \tmbuf = mbuf->next;\n \t/* o/p segs */\n \twhile (mbuf) {\n \t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t\tsge->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -420,17 +412,14 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess,\n \t\tsge++;\n \t}\n \n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, sym_op->aead.data.offset +\n-\t\t\t\tmbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf) + sym_op->aead.data.offset);\n \tsge->length = mbuf->data_len - sym_op->aead.data.offset;\n \n \tmbuf = mbuf->next;\n \t/* i/p segs */\n \twhile (mbuf) {\n \t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t\tsge->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -535,8 +524,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,\n \tDPAA2_SET_FLE_SG_EXT(fle);\n \n \t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(dst));\n-\tDPAA2_SET_FLE_OFFSET(sge, dst->data_off + sym_op->aead.data.offset);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(dst) + sym_op->aead.data.offset);\n \tsge->length = sym_op->aead.data.length;\n \n \tif (sess->dir == DIR_ENC) {\n@@ -571,9 +559,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,\n \t\tsge++;\n \t}\n \n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n-\tDPAA2_SET_FLE_OFFSET(sge, sym_op->aead.data.offset +\n-\t\t\t\tsym_op->m_src->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(sym_op->m_src) + sym_op->aead.data.offset);\n \tsge->length = sym_op->aead.data.length;\n \tif (sess->dir == DIR_DEC) {\n \t\tsge++;\n@@ -666,16 +652,14 @@ build_authenc_sg_fd(dpaa2_sec_session *sess,\n \t\t\tsym_op->cipher.data.length;\n \n \t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off + sym_op->auth.data.offset);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf) + sym_op->auth.data.offset);\n \tsge->length = mbuf->data_len - sym_op->auth.data.offset;\n \n \tmbuf = mbuf->next;\n \t/* o/p segs */\n \twhile (mbuf) {\n \t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t\tsge->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -706,17 +690,14 @@ build_authenc_sg_fd(dpaa2_sec_session *sess,\n \tsge->length = sess->iv.length;\n \n \tsge++;\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, sym_op->auth.data.offset +\n-\t\t\t\tmbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf) + sym_op->auth.data.offset);\n \tsge->length = mbuf->data_len - sym_op->auth.data.offset;\n \n \tmbuf = mbuf->next;\n \t/* i/p segs */\n \twhile (mbuf) {\n \t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t\tsge->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -830,9 +811,7 @@ build_authenc_fd(dpaa2_sec_session *sess,\n \tDPAA2_SET_FLE_SG_EXT(fle);\n \n \t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(dst));\n-\tDPAA2_SET_FLE_OFFSET(sge, sym_op->cipher.data.offset +\n-\t\t\t\tdst->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(dst) + sym_op->cipher.data.offset);\n \tsge->length = sym_op->cipher.data.length;\n \n \tif (sess->dir == DIR_ENC) {\n@@ -862,9 +841,7 @@ build_authenc_fd(dpaa2_sec_session *sess,\n \tsge->length = sess->iv.length;\n \tsge++;\n \n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n-\tDPAA2_SET_FLE_OFFSET(sge, sym_op->auth.data.offset +\n-\t\t\t\tsym_op->m_src->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(sym_op->m_src) + sym_op->auth.data.offset);\n \tsge->length = sym_op->auth.data.length;\n \tif (sess->dir == DIR_DEC) {\n \t\tsge++;\n@@ -965,8 +942,7 @@ static inline int build_auth_sg_fd(\n \t\tsge++;\n \t}\n \t/* i/p 1st seg */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset + mbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf) + data_offset);\n \n \tif (data_len <= (mbuf->data_len - data_offset)) {\n \t\tsge->length = data_len;\n@@ -978,8 +954,7 @@ static inline int build_auth_sg_fd(\n \t\twhile ((data_len = data_len - sge->length) &&\n \t\t (mbuf = mbuf->next)) {\n \t\t\tsge++;\n-\t\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t\t\tif (data_len > mbuf->data_len)\n \t\t\t\tsge->length = mbuf->data_len;\n \t\t\telse\n@@ -1097,8 +1072,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,\n \t}\n \n \t/* Setting data to authenticate */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset + sym_op->m_src->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(sym_op->m_src) + data_offset);\n \tsge->length = data_len;\n \n \tif (sess->dir == DIR_DEC) {\n@@ -1183,16 +1157,14 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,\n \tDPAA2_SET_FLE_SG_EXT(op_fle);\n \n \t/* o/p 1st seg */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset + mbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf) + data_offset);\n \tsge->length = mbuf->data_len - data_offset;\n \n \tmbuf = mbuf->next;\n \t/* o/p segs */\n \twhile (mbuf) {\n \t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t\tsge->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -1212,22 +1184,19 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,\n \n \t/* i/p IV */\n \tDPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(iv_ptr));\n-\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \tsge->length = sess->iv.length;\n \n \tsge++;\n \n \t/* i/p 1st seg */\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset + mbuf->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf) + data_offset);\n \tsge->length = mbuf->data_len - data_offset;\n \n \tmbuf = mbuf->next;\n \t/* i/p segs */\n \twhile (mbuf) {\n \t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, mbuf->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(mbuf));\n \t\tsge->length = mbuf->data_len;\n \t\tmbuf = mbuf->next;\n \t}\n@@ -1328,8 +1297,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,\n \t\tsess->iv.length,\n \t\tsym_op->m_src->data_off);\n \n-\tDPAA2_SET_FLE_ADDR(fle, DPAA2_MBUF_VADDR_TO_IOVA(dst));\n-\tDPAA2_SET_FLE_OFFSET(fle, data_offset + dst->data_off);\n+\tDPAA2_SET_FLE_ADDR(fle, rte_pktmbuf_iova(dst) + data_offset);\n \n \tfle->length = data_len + sess->iv.length;\n \n@@ -1349,8 +1317,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,\n \tsge->length = sess->iv.length;\n \n \tsge++;\n-\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset + sym_op->m_src->data_off);\n+\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(sym_op->m_src) + data_offset);\n \n \tsge->length = data_len;\n \tDPAA2_SET_FLE_FIN(sge);\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\nindex 36c79e450a..4754b9d6f8 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n@@ -95,29 +95,25 @@ build_raw_dp_chain_fd(uint8_t *drv_ctx,\n \t/* OOP */\n \tif (dest_sgl) {\n \t\t/* Configure Output SGE for Encap/Decap */\n-\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova + ofs.ofs.cipher.head);\n \t\tsge->length = dest_sgl->vec[0].len - ofs.ofs.cipher.head;\n \n \t\t/* o/p segs */\n \t\tfor (i = 1; i < dest_sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = dest_sgl->vec[i].len;\n \t\t}\n \t\tsge->length -= ofs.ofs.cipher.tail;\n \t} else {\n \t\t/* Configure Output SGE for Encap/Decap */\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova + ofs.ofs.cipher.head);\n \t\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n \n \t\t/* o/p segs */\n \t\tfor (i = 1; i < sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = sgl->vec[i].len;\n \t\t}\n \t\tsge->length -= ofs.ofs.cipher.tail;\n@@ -148,14 +144,12 @@ build_raw_dp_chain_fd(uint8_t *drv_ctx,\n \tsge->length = sess->iv.length;\n \n \tsge++;\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.auth.head);\n+\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova + ofs.ofs.auth.head);\n \tsge->length = sgl->vec[0].len - ofs.ofs.auth.head;\n \n \tfor (i = 1; i < sgl->num; i++) {\n \t\tsge++;\n \t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\tsge->length = sgl->vec[i].len;\n \t}\n \n@@ -244,28 +238,24 @@ build_raw_dp_aead_fd(uint8_t *drv_ctx,\n \t/* OOP */\n \tif (dest_sgl) {\n \t\t/* Configure Output SGE for Encap/Decap */\n-\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova + ofs.ofs.cipher.head);\n \t\tsge->length = dest_sgl->vec[0].len - ofs.ofs.cipher.head;\n \n \t\t/* o/p segs */\n \t\tfor (i = 1; i < dest_sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = dest_sgl->vec[i].len;\n \t\t}\n \t} else {\n \t\t/* Configure Output SGE for Encap/Decap */\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova + ofs.ofs.cipher.head);\n \t\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n \n \t\t/* o/p segs */\n \t\tfor (i = 1; i < sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = sgl->vec[i].len;\n \t\t}\n \t}\n@@ -299,15 +289,13 @@ build_raw_dp_aead_fd(uint8_t *drv_ctx,\n \t\tsge++;\n \t}\n \n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova + ofs.ofs.cipher.head);\n \tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n \n \t/* i/p segs */\n \tfor (i = 1; i < sgl->num; i++) {\n \t\tsge++;\n \t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\tsge->length = sgl->vec[i].len;\n \t}\n \n@@ -412,8 +400,7 @@ build_raw_dp_auth_fd(uint8_t *drv_ctx,\n \t\tsge++;\n \t}\n \t/* i/p 1st seg */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova + data_offset);\n \n \tif (data_len <= (int)(sgl->vec[0].len - data_offset)) {\n \t\tsge->length = data_len;\n@@ -423,7 +410,6 @@ build_raw_dp_auth_fd(uint8_t *drv_ctx,\n \t\tfor (i = 1; i < sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = sgl->vec[i].len;\n \t\t}\n \t}\n@@ -502,14 +488,12 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \tif (dest_sgl) {\n \t\t/* Configure Output SGE for Encap/Decap */\n \t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\tsge->length = dest_sgl->vec[0].len;\n \t\tout_len += sge->length;\n \t\t/* o/p segs */\n \t\tfor (i = 1; i < dest_sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = dest_sgl->vec[i].len;\n \t\t\tout_len += sge->length;\n \t\t}\n@@ -518,14 +502,12 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \t} else {\n \t\t/* Configure Output SGE for Encap/Decap */\n \t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\tsge->length = sgl->vec[0].len;\n \t\tout_len += sge->length;\n \t\t/* o/p segs */\n \t\tfor (i = 1; i < sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = sgl->vec[i].len;\n \t\t\tout_len += sge->length;\n \t\t}\n@@ -545,14 +527,12 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \n \t/* Configure input SGE for Encap/Decap */\n \tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \tsge->length = sgl->vec[0].len;\n \tin_len += sge->length;\n \t/* i/p segs */\n \tfor (i = 1; i < sgl->num; i++) {\n \t\tsge++;\n \t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\tsge->length = sgl->vec[i].len;\n \t\tin_len += sge->length;\n \t}\n@@ -638,28 +618,24 @@ build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n \t/* OOP */\n \tif (dest_sgl) {\n \t\t/* o/p 1st seg */\n-\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova + data_offset);\n \t\tsge->length = dest_sgl->vec[0].len - data_offset;\n \n \t\t/* o/p segs */\n \t\tfor (i = 1; i < dest_sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = dest_sgl->vec[i].len;\n \t\t}\n \t} else {\n \t\t/* o/p 1st seg */\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova + data_offset);\n \t\tsge->length = sgl->vec[0].len - data_offset;\n \n \t\t/* o/p segs */\n \t\tfor (i = 1; i < sgl->num; i++) {\n \t\t\tsge++;\n \t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\t\tsge->length = sgl->vec[i].len;\n \t\t}\n \t}\n@@ -678,21 +654,18 @@ build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n \n \t/* i/p IV */\n \tDPAA2_SET_FLE_ADDR(sge, iv->iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \tsge->length = sess->iv.length;\n \n \tsge++;\n \n \t/* i/p 1st seg */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova + data_offset);\n \tsge->length = sgl->vec[0].len - data_offset;\n \n \t/* i/p segs */\n \tfor (i = 1; i < sgl->num; i++) {\n \t\tsge++;\n \t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n \t\tsge->length = sgl->vec[i].len;\n \t}\n \tDPAA2_SET_FLE_FIN(sge);\ndiff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c\nindex 85910bbd8f..23f7c4132d 100644\n--- a/drivers/net/dpaa2/dpaa2_rxtx.c\n+++ b/drivers/net/dpaa2/dpaa2_rxtx.c\n@@ -471,8 +471,7 @@ eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,\n \t\tsge = &sgt[i];\n \t\t/*Resetting the buffer pool id and offset field*/\n \t\tsge->fin_bpid_offset = 0;\n-\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(cur_seg));\n-\t\tDPAA2_SET_FLE_OFFSET(sge, cur_seg->data_off);\n+\t\tDPAA2_SET_FLE_ADDR(sge, rte_pktmbuf_iova(cur_seg));\n \t\tsge->length = cur_seg->data_len;\n \t\tif (RTE_MBUF_DIRECT(cur_seg)) {\n \t\t\t/* if we are using inline SGT in same buffers\n", "prefixes": [ "v2", "07/13" ] }