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GET /api/patches/131812/?format=api
{ "id": 131812, "url": "http://patchwork.dpdk.org/api/patches/131812/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230921204349.3285318-6-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230921204349.3285318-6-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230921204349.3285318-6-nicolas.chautru@intel.com", "date": "2023-09-21T20:43:47", "name": "[v2,5/7] baseband/acc: add support for MLD operation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7adb7ee4edc6264e02a122878ea77df3f186ef9d", "submitter": { "id": 1314, "url": "http://patchwork.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "http://patchwork.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230921204349.3285318-6-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 29596, "url": "http://patchwork.dpdk.org/api/series/29596/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29596", "date": "2023-09-21T20:43:42", "name": "VRB2 bbdev PMD introduction", "version": 2, "mbox": "http://patchwork.dpdk.org/series/29596/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131812/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/131812/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6FAD14260E;\n\tThu, 21 Sep 2023 22:47:32 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A2B1240A6C;\n\tThu, 21 Sep 2023 22:47:05 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id C46C5402D3\n for <dev@dpdk.org>; Thu, 21 Sep 2023 22:47:00 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Sep 2023 13:47:00 -0700", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by orsmga003.jf.intel.com with ESMTP; 21 Sep 2023 13:46:59 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695329221; x=1726865221;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=qm5yLMMNjZxSruETh7e5tseVxAJwOVeJb1YdtoTzxd0=;\n b=SoCsuEIfY/ikvjzKzXCyfLJ24ViPBOWIvD5Z1krWLeMIxo8zJsNHksj8\n jn3QNyrGgNYE2SIItMvz4qRNpf8dBetPJJj36dDB6uIwXo2jrUI+RdprS\n ZPEBI5YYoJOe9dTtnkqba14Fg2Rf9yCde0Qa1vsSrMc5LQrIcyqPcHyIJ\n 0F+/EONLBysEVVkrIBKi1Yl/ibdpRbkUXMeIz64xqDXQ+hiJhQvwBt4km\n GBd0944y+xQ9Exo19L1xysE0MN7oaY5d4OLZNA20pO/CuAs1C2NJMhi4+\n XH657bhKXU/AUpil9la6qxLrF3fRoAdaAU9hwbaV8rBLKhHbXV4ivkVwA A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10840\"; a=\"447138118\"", "E=Sophos;i=\"6.03,166,1694761200\"; d=\"scan'208\";a=\"447138118\"", "E=McAfee;i=\"6600,9927,10840\"; a=\"696907257\"", "E=Sophos;i=\"6.03,166,1694761200\"; d=\"scan'208\";a=\"696907257\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hemant.agrawal@nxp.com, david.marchand@redhat.com,\n hernan.vargas@intel.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v2 5/7] baseband/acc: add support for MLD operation", "Date": "Thu, 21 Sep 2023 20:43:47 +0000", "Message-Id": "<20230921204349.3285318-6-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230921204349.3285318-1-nicolas.chautru@intel.com>", "References": "<20230921204349.3285318-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "There is no functionality related to the MLD operation\nbut allows the unified PMD to support the operation\nbeing added moving forward.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc/acc_common.h | 1 +\n drivers/baseband/acc/rte_vrb_pmd.c | 39 ++++++++++++++++++++++++------\n drivers/baseband/acc/vrb_pmd.h | 12 +++++++++\n 3 files changed, 45 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h\nindex b5ee113faf..5de58dbe36 100644\n--- a/drivers/baseband/acc/acc_common.h\n+++ b/drivers/baseband/acc/acc_common.h\n@@ -87,6 +87,7 @@\n #define ACC_FCW_LE_BLEN 32\n #define ACC_FCW_LD_BLEN 36\n #define ACC_FCW_FFT_BLEN 28\n+#define ACC_FCW_MLDTS_BLEN 32\n #define ACC_5GUL_SIZE_0 16\n #define ACC_5GUL_SIZE_1 40\n #define ACC_5GUL_OFFSET_0 36\ndiff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c\nindex f460e9ea2a..e82ed55ca7 100644\n--- a/drivers/baseband/acc/rte_vrb_pmd.c\n+++ b/drivers/baseband/acc/rte_vrb_pmd.c\n@@ -37,7 +37,7 @@ vrb1_queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id\n \t\treturn ((qgrp_id << 7) + (aq_id << 3) + VRB1_VfQmgrIngressAq);\n }\n \n-enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, NUM_ACC};\n+enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, MLD, NUM_ACC};\n \n /* Return the accelerator enum for a Queue Group Index. */\n static inline int\n@@ -53,6 +53,7 @@ accFromQgid(int qg_idx, const struct rte_acc_conf *acc_conf)\n \tNumQGroupsPerFn[DL_4G] = acc_conf->q_dl_4g.num_qgroups;\n \tNumQGroupsPerFn[DL_5G] = acc_conf->q_dl_5g.num_qgroups;\n \tNumQGroupsPerFn[FFT] = acc_conf->q_fft.num_qgroups;\n+\tNumQGroupsPerFn[MLD] = acc_conf->q_mld.num_qgroups;\n \tfor (acc = UL_4G; acc < NUM_ACC; acc++)\n \t\tfor (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)\n \t\t\taccQg[qgIndex++] = acc;\n@@ -83,6 +84,9 @@ qtopFromAcc(struct rte_acc_queue_topology **qtop, int acc_enum, struct rte_acc_c\n \tcase FFT:\n \t\tp_qtop = &(acc_conf->q_fft);\n \t\tbreak;\n+\tcase MLD:\n+\t\tp_qtop = &(acc_conf->q_mld);\n+\t\tbreak;\n \tdefault:\n \t\t/* NOTREACHED. */\n \t\trte_bbdev_log(ERR, \"Unexpected error evaluating %s using %d\", __func__, acc_enum);\n@@ -139,6 +143,9 @@ initQTop(struct rte_acc_conf *acc_conf)\n \tacc_conf->q_fft.num_aqs_per_groups = 0;\n \tacc_conf->q_fft.num_qgroups = 0;\n \tacc_conf->q_fft.first_qgroup_index = -1;\n+\tacc_conf->q_mld.num_aqs_per_groups = 0;\n+\tacc_conf->q_mld.num_qgroups = 0;\n+\tacc_conf->q_mld.first_qgroup_index = -1;\n }\n \n static inline void\n@@ -250,7 +257,7 @@ fetch_acc_config(struct rte_bbdev *dev)\n \t}\n \n \trte_bbdev_log_debug(\n-\t\t\t\"%s Config LLR SIGN IN/OUT %s %s QG %u %u %u %u %u AQ %u %u %u %u %u Len %u %u %u %u %u\\n\",\n+\t\t\t\"%s Config LLR SIGN IN/OUT %s %s QG %u %u %u %u %u %u AQ %u %u %u %u %u %u Len %u %u %u %u %u %u\\n\",\n \t\t\t(d->pf_device) ? \"PF\" : \"VF\",\n \t\t\t(acc_conf->input_pos_llr_1_bit) ? \"POS\" : \"NEG\",\n \t\t\t(acc_conf->output_pos_llr_1_bit) ? \"POS\" : \"NEG\",\n@@ -259,16 +266,19 @@ fetch_acc_config(struct rte_bbdev *dev)\n \t\t\tacc_conf->q_ul_5g.num_qgroups,\n \t\t\tacc_conf->q_dl_5g.num_qgroups,\n \t\t\tacc_conf->q_fft.num_qgroups,\n+\t\t\tacc_conf->q_mld.num_qgroups,\n \t\t\tacc_conf->q_ul_4g.num_aqs_per_groups,\n \t\t\tacc_conf->q_dl_4g.num_aqs_per_groups,\n \t\t\tacc_conf->q_ul_5g.num_aqs_per_groups,\n \t\t\tacc_conf->q_dl_5g.num_aqs_per_groups,\n \t\t\tacc_conf->q_fft.num_aqs_per_groups,\n+\t\t\tacc_conf->q_mld.num_aqs_per_groups,\n \t\t\tacc_conf->q_ul_4g.aq_depth_log2,\n \t\t\tacc_conf->q_dl_4g.aq_depth_log2,\n \t\t\tacc_conf->q_ul_5g.aq_depth_log2,\n \t\t\tacc_conf->q_dl_5g.aq_depth_log2,\n-\t\t\tacc_conf->q_fft.aq_depth_log2);\n+\t\t\tacc_conf->q_fft.aq_depth_log2,\n+\t\t\tacc_conf->q_mld.aq_depth_log2);\n }\n \n static inline void\n@@ -332,7 +342,7 @@ vrb_check_ir(struct acc_device *acc_dev)\n \n \twhile (ring_data->valid) {\n \t\tif ((ring_data->int_nb < ACC_PF_INT_DMA_DL_DESC_IRQ) || (\n-\t\t\t\tring_data->int_nb > ACC_PF_INT_DMA_DL5G_DESC_IRQ)) {\n+\t\t\t\tring_data->int_nb > ACC_PF_INT_DMA_MLD_DESC_IRQ)) {\n \t\t\trte_bbdev_log(WARNING, \"InfoRing: ITR:%d Info:0x%x\",\n \t\t\t\t\tring_data->int_nb, ring_data->detailed_info);\n \t\t\t/* Initialize Info Ring entry and move forward. */\n@@ -366,6 +376,7 @@ vrb_dev_interrupt_handler(void *cb_arg)\n \t\t\tcase ACC_PF_INT_DMA_FFT_DESC_IRQ:\n \t\t\tcase ACC_PF_INT_DMA_UL5G_DESC_IRQ:\n \t\t\tcase ACC_PF_INT_DMA_DL5G_DESC_IRQ:\n+\t\t\tcase ACC_PF_INT_DMA_MLD_DESC_IRQ:\n \t\t\t\tdeq_intr_det.queue_id = get_queue_id_from_ring_info(\n \t\t\t\t\t\tdev->data, *ring_data);\n \t\t\t\tif (deq_intr_det.queue_id == UINT16_MAX) {\n@@ -393,6 +404,7 @@ vrb_dev_interrupt_handler(void *cb_arg)\n \t\t\tcase ACC_VF_INT_DMA_FFT_DESC_IRQ:\n \t\t\tcase ACC_VF_INT_DMA_UL5G_DESC_IRQ:\n \t\t\tcase ACC_VF_INT_DMA_DL5G_DESC_IRQ:\n+\t\t\tcase ACC_VF_INT_DMA_MLD_DESC_IRQ:\n \t\t\t\t/* VFs are not aware of their vf_id - it's set to 0. */\n \t\t\t\tring_data->vf_id = 0;\n \t\t\t\tdeq_intr_det.queue_id = get_queue_id_from_ring_info(\n@@ -741,7 +753,7 @@ vrb_find_free_queue_idx(struct rte_bbdev *dev,\n \t\tconst struct rte_bbdev_queue_conf *conf)\n {\n \tstruct acc_device *d = dev->data->dev_private;\n-\tint op_2_acc[6] = {0, UL_4G, DL_4G, UL_5G, DL_5G, FFT};\n+\tint op_2_acc[7] = {0, UL_4G, DL_4G, UL_5G, DL_5G, FFT, MLD};\n \tint acc = op_2_acc[conf->op_type];\n \tstruct rte_acc_queue_topology *qtop = NULL;\n \tuint16_t group_idx;\n@@ -804,7 +816,8 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \tint fcw_len = (conf->op_type == RTE_BBDEV_OP_LDPC_ENC ?\n \t\t\tACC_FCW_LE_BLEN : (conf->op_type == RTE_BBDEV_OP_TURBO_DEC ?\n \t\t\tACC_FCW_TD_BLEN : (conf->op_type == RTE_BBDEV_OP_LDPC_DEC ?\n-\t\t\tACC_FCW_LD_BLEN : ACC_FCW_FFT_BLEN)));\n+\t\t\tACC_FCW_LD_BLEN : (conf->op_type == RTE_BBDEV_OP_FFT ?\n+\t\t\tACC_FCW_FFT_BLEN : ACC_FCW_MLDTS_BLEN))));\n \n \tfor (desc_idx = 0; desc_idx < d->sw_ring_max_depth; desc_idx++) {\n \t\tdesc = q->ring_addr + desc_idx;\n@@ -916,6 +929,8 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \t\tq->aq_depth = (1 << d->acc_conf.q_dl_5g.aq_depth_log2);\n \telse if (conf->op_type == RTE_BBDEV_OP_FFT)\n \t\tq->aq_depth = (1 << d->acc_conf.q_fft.aq_depth_log2);\n+\telse if (conf->op_type == RTE_BBDEV_OP_MLDTS)\n+\t\tq->aq_depth = (1 << d->acc_conf.q_mld.aq_depth_log2);\n \n \tq->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base,\n \t\t\td->queue_offset(d->pf_device, q->vf_id, q->qgrp_id, q->aq_id));\n@@ -972,6 +987,13 @@ vrb_print_op(struct rte_bbdev_dec_op *op, enum rte_bbdev_op_type op_type,\n \t\t\top_dl->ldpc_enc.n_filler, op_dl->ldpc_enc.cb_params.e,\n \t\t\top_dl->ldpc_enc.op_flags, op_dl->ldpc_enc.rv_index\n \t\t\t);\n+\t} else if (op_type == RTE_BBDEV_OP_MLDTS) {\n+\t\tstruct rte_bbdev_mldts_op *op_mldts = (struct rte_bbdev_mldts_op *) op;\n+\t\trte_bbdev_log(INFO, \" Op MLD %d RBs %d NL %d Rp %d %d %x\\n\",\n+\t\t\t\tindex,\n+\t\t\t\top_mldts->mldts.num_rbs, op_mldts->mldts.num_layers,\n+\t\t\t\top_mldts->mldts.r_rep,\n+\t\t\t\top_mldts->mldts.c_rep, op_mldts->mldts.op_flags);\n \t}\n }\n \n@@ -1151,13 +1173,16 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info)\n \t\t\td->acc_conf.q_dl_5g.num_qgroups;\n \tdev_info->num_queues[RTE_BBDEV_OP_FFT] = d->acc_conf.q_fft.num_aqs_per_groups *\n \t\t\td->acc_conf.q_fft.num_qgroups;\n+\tdev_info->num_queues[RTE_BBDEV_OP_MLDTS] = d->acc_conf.q_mld.num_aqs_per_groups *\n+\t\t\td->acc_conf.q_mld.num_qgroups;\n \tdev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = d->acc_conf.q_ul_4g.num_qgroups;\n \tdev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = d->acc_conf.q_dl_4g.num_qgroups;\n \tdev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = d->acc_conf.q_ul_5g.num_qgroups;\n \tdev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = d->acc_conf.q_dl_5g.num_qgroups;\n \tdev_info->queue_priority[RTE_BBDEV_OP_FFT] = d->acc_conf.q_fft.num_qgroups;\n+\tdev_info->queue_priority[RTE_BBDEV_OP_MLDTS] = d->acc_conf.q_mld.num_qgroups;\n \tdev_info->max_num_queues = 0;\n-\tfor (i = RTE_BBDEV_OP_NONE; i <= RTE_BBDEV_OP_FFT; i++)\n+\tfor (i = RTE_BBDEV_OP_NONE; i <= RTE_BBDEV_OP_MLDTS; i++)\n \t\tdev_info->max_num_queues += dev_info->num_queues[i];\n \tdev_info->queue_size_lim = ACC_MAX_QUEUE_DEPTH;\n \tdev_info->hardware_accelerated = true;\ndiff --git a/drivers/baseband/acc/vrb_pmd.h b/drivers/baseband/acc/vrb_pmd.h\nindex 01028273e7..1cabc0b7f4 100644\n--- a/drivers/baseband/acc/vrb_pmd.h\n+++ b/drivers/baseband/acc/vrb_pmd.h\n@@ -101,6 +101,8 @@ struct acc_registry_addr {\n \tunsigned int dma_ring_ul4g_lo;\n \tunsigned int dma_ring_fft_hi;\n \tunsigned int dma_ring_fft_lo;\n+\tunsigned int dma_ring_mld_hi;\n+\tunsigned int dma_ring_mld_lo;\n \tunsigned int ring_size;\n \tunsigned int info_ring_hi;\n \tunsigned int info_ring_lo;\n@@ -116,6 +118,8 @@ struct acc_registry_addr {\n \tunsigned int tail_ptrs_ul4g_lo;\n \tunsigned int tail_ptrs_fft_hi;\n \tunsigned int tail_ptrs_fft_lo;\n+\tunsigned int tail_ptrs_mld_hi;\n+\tunsigned int tail_ptrs_mld_lo;\n \tunsigned int depth_log0_offset;\n \tunsigned int depth_log1_offset;\n \tunsigned int qman_group_func;\n@@ -140,6 +144,8 @@ static const struct acc_registry_addr vrb1_pf_reg_addr = {\n \t.dma_ring_ul4g_lo = VRB1_PfDmaFec4GulDescBaseLoRegVf,\n \t.dma_ring_fft_hi = VRB1_PfDmaFftDescBaseHiRegVf,\n \t.dma_ring_fft_lo = VRB1_PfDmaFftDescBaseLoRegVf,\n+\t.dma_ring_mld_hi = 0,\n+\t.dma_ring_mld_lo = 0,\n \t.ring_size = VRB1_PfQmgrRingSizeVf,\n \t.info_ring_hi = VRB1_PfHiInfoRingBaseHiRegPf,\n \t.info_ring_lo = VRB1_PfHiInfoRingBaseLoRegPf,\n@@ -155,6 +161,8 @@ static const struct acc_registry_addr vrb1_pf_reg_addr = {\n \t.tail_ptrs_ul4g_lo = VRB1_PfDmaFec4GulRespPtrLoRegVf,\n \t.tail_ptrs_fft_hi = VRB1_PfDmaFftRespPtrHiRegVf,\n \t.tail_ptrs_fft_lo = VRB1_PfDmaFftRespPtrLoRegVf,\n+\t.tail_ptrs_mld_hi = 0,\n+\t.tail_ptrs_mld_lo = 0,\n \t.depth_log0_offset = VRB1_PfQmgrGrpDepthLog20Vf,\n \t.depth_log1_offset = VRB1_PfQmgrGrpDepthLog21Vf,\n \t.qman_group_func = VRB1_PfQmgrGrpFunction0,\n@@ -179,6 +187,8 @@ static const struct acc_registry_addr vrb1_vf_reg_addr = {\n \t.dma_ring_ul4g_lo = VRB1_VfDmaFec4GulDescBaseLoRegVf,\n \t.dma_ring_fft_hi = VRB1_VfDmaFftDescBaseHiRegVf,\n \t.dma_ring_fft_lo = VRB1_VfDmaFftDescBaseLoRegVf,\n+\t.dma_ring_mld_hi = 0,\n+\t.dma_ring_mld_lo = 0,\n \t.ring_size = VRB1_VfQmgrRingSizeVf,\n \t.info_ring_hi = VRB1_VfHiInfoRingBaseHiVf,\n \t.info_ring_lo = VRB1_VfHiInfoRingBaseLoVf,\n@@ -194,6 +204,8 @@ static const struct acc_registry_addr vrb1_vf_reg_addr = {\n \t.tail_ptrs_ul4g_lo = VRB1_VfDmaFec4GulRespPtrLoRegVf,\n \t.tail_ptrs_fft_hi = VRB1_VfDmaFftRespPtrHiRegVf,\n \t.tail_ptrs_fft_lo = VRB1_VfDmaFftRespPtrLoRegVf,\n+\t.tail_ptrs_mld_hi = 0,\n+\t.tail_ptrs_mld_lo = 0,\n \t.depth_log0_offset = VRB1_VfQmgrGrpDepthLog20Vf,\n \t.depth_log1_offset = VRB1_VfQmgrGrpDepthLog21Vf,\n \t.qman_group_func = VRB1_VfQmgrGrpFunction0Vf,\n", "prefixes": [ "v2", "5/7" ] }