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GET /api/patches/131822/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 131822,
    "url": "http://patchwork.dpdk.org/api/patches/131822/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230922081912.7090-2-bruce.richardson@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20230922081912.7090-2-bruce.richardson@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20230922081912.7090-2-bruce.richardson@intel.com",
    "date": "2023-09-22T08:19:08",
    "name": "[RFC,1/5] bus: new driver to accept shared memory over unix socket",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "8662c5fb1ad9c5e3079bd0a6498db7715f29fc93",
    "submitter": {
        "id": 20,
        "url": "http://patchwork.dpdk.org/api/people/20/?format=api",
        "name": "Bruce Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230922081912.7090-2-bruce.richardson@intel.com/mbox/",
    "series": [
        {
            "id": 29602,
            "url": "http://patchwork.dpdk.org/api/series/29602/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29602",
            "date": "2023-09-22T08:19:07",
            "name": "Using shared mempools for zero-copy IO proxying",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/29602/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/131822/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/131822/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 07A3E42612;\n\tFri, 22 Sep 2023 10:19:51 +0200 (CEST)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8ECB44069F;\n\tFri, 22 Sep 2023 10:19:44 +0200 (CEST)",
            "from mgamail.intel.com (mgamail.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 5A6E34013F\n for <dev@dpdk.org>; Fri, 22 Sep 2023 10:19:42 +0200 (CEST)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 22 Sep 2023 01:19:26 -0700",
            "from silpixa00401385.ir.intel.com ([10.237.214.14])\n by fmsmga005.fm.intel.com with ESMTP; 22 Sep 2023 01:19:25 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695370782; x=1726906782;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=WZGvEfsLQKzFS2xLHU26+BEKsHj9/5wvqj2KWW9VElw=;\n b=WNsXNPe/NvnFxHfcVLyW2tAgdNZLXq4LMceInvx+exRF9gGN6FoYgZGk\n gbSrNuFekbU4LfjTTq04Pe97IhNnPrfQe3YHENvgWqfkbj9bRICD10Mr9\n h4Kika4fSfanPYXQ0m0cm6nCK2BI1eFs/kl8upnil2Tzc15tQK4sj/d/A\n Sg0TgbwsZ9w6kZswwceb0e9uaAS2NfiEPFxNcICNOlV9fyjKE/L8vLCZW\n Ojf6pyIBIpFJFGZ6gxJuYNJguW6Gh87da1WQI+49kjMRdFAyeeciZeOeF\n 24Z8wL+DoILcwpGE4zSjQIkFQqYuD4GxE0ebkbx0+tMQKvavSu+S1t3Kk A==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10840\"; a=\"378063962\"",
            "E=Sophos;i=\"6.03,167,1694761200\"; d=\"scan'208\";a=\"378063962\"",
            "E=McAfee;i=\"6600,9927,10840\"; a=\"1078281116\"",
            "E=Sophos;i=\"6.03,167,1694761200\"; d=\"scan'208\";a=\"1078281116\""
        ],
        "X-ExtLoop1": "1",
        "From": "Bruce Richardson <bruce.richardson@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Bruce Richardson <bruce.richardson@intel.com>",
        "Subject": "[RFC PATCH 1/5] bus: new driver to accept shared memory over unix\n socket",
        "Date": "Fri, 22 Sep 2023 09:19:08 +0100",
        "Message-Id": "<20230922081912.7090-2-bruce.richardson@intel.com>",
        "X-Mailer": "git-send-email 2.39.2",
        "In-Reply-To": "<20230922081912.7090-1-bruce.richardson@intel.com>",
        "References": "<20230922081912.7090-1-bruce.richardson@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Add a new driver to DPDK which supports taking in memory e.g. hugepage\nmemory via a unix socket connection and maps it into the DPDK process\nreplacing the current socket memory as the default memory for use by\nfuture requests.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n drivers/bus/meson.build                 |   1 +\n drivers/bus/shared_mem/meson.build      |  11 +\n drivers/bus/shared_mem/shared_mem_bus.c | 323 ++++++++++++++++++++++++\n drivers/bus/shared_mem/shared_mem_bus.h |  75 ++++++\n drivers/bus/shared_mem/version.map      |  11 +\n 5 files changed, 421 insertions(+)\n create mode 100644 drivers/bus/shared_mem/meson.build\n create mode 100644 drivers/bus/shared_mem/shared_mem_bus.c\n create mode 100644 drivers/bus/shared_mem/shared_mem_bus.h\n create mode 100644 drivers/bus/shared_mem/version.map",
    "diff": "diff --git a/drivers/bus/meson.build b/drivers/bus/meson.build\nindex a78b4283bf..0e64959d1a 100644\n--- a/drivers/bus/meson.build\n+++ b/drivers/bus/meson.build\n@@ -9,6 +9,7 @@ drivers = [\n         'ifpga',\n         'pci',\n         'platform',\n+        'shared_mem',\n         'vdev',\n         'vmbus',\n ]\ndiff --git a/drivers/bus/shared_mem/meson.build b/drivers/bus/shared_mem/meson.build\nnew file mode 100644\nindex 0000000000..1fa21f3a09\n--- /dev/null\n+++ b/drivers/bus/shared_mem/meson.build\n@@ -0,0 +1,11 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2023 Intel Corporation\n+\n+if is_windows\n+    build = false\n+    reason = 'not supported on Windows'\n+endif\n+\n+sources = files('shared_mem_bus.c')\n+require_iova_in_mbuf = false\n+deps += ['mbuf', 'net']\ndiff --git a/drivers/bus/shared_mem/shared_mem_bus.c b/drivers/bus/shared_mem/shared_mem_bus.c\nnew file mode 100644\nindex 0000000000..e0369ed416\n--- /dev/null\n+++ b/drivers/bus/shared_mem/shared_mem_bus.c\n@@ -0,0 +1,323 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+#include <errno.h>\n+#include <malloc.h>\n+#include <inttypes.h>\n+#include <sys/un.h>\n+#include <sys/stat.h>\n+#include <sys/mman.h>\n+#include <sys/socket.h>\n+\n+#include <rte_log.h>\n+#include <rte_lcore.h>\n+#include <rte_errno.h>\n+#include <rte_malloc.h>\n+#include <rte_devargs.h>\n+#include <rte_mbuf_pool_ops.h>\n+\n+#include <bus_driver.h>\n+#include <dev_driver.h>\n+#include \"shared_mem_bus.h\"\n+\n+RTE_LOG_REGISTER_DEFAULT(shared_mem_bus_logtype, DEBUG);\n+#define BUS_LOG(level, fmt, args...) rte_log(RTE_LOG_ ## level, \\\n+\t\tshared_mem_bus_logtype, \"## SHARED MEM BUS: %s(): \" fmt \"\\n\", __func__, ##args)\n+#define BUS_ERR(fmt, args...)  BUS_LOG(ERR, fmt, ## args)\n+#define BUS_INFO(fmt, args...)  BUS_LOG(INFO, fmt, ## args)\n+#define BUS_DEBUG(fmt, args...)  BUS_LOG(DEBUG, fmt, ## args)\n+\n+static int dev_scan(void);\n+static int dev_probe(void);\n+static struct rte_device *find_device(const struct rte_device *start, rte_dev_cmp_t cmp,\n+\t\t const void *data);\n+static enum rte_iova_mode get_iommu_class(void);\n+static int addr_parse(const char *, void *);\n+\n+struct socket_device {\n+\tstruct rte_device rte_device;\n+\tTAILQ_ENTRY(socket_device) next;\n+\tint fd;\n+\tuintptr_t membase;\n+\tuintptr_t memlen;\n+};\n+\n+/** List of devices */\n+TAILQ_HEAD(socket_list, socket_device);\n+TAILQ_HEAD(device_list, rte_device);\n+\n+struct shared_mem_bus {\n+\tstruct rte_bus bus;\n+\tstruct socket_list socket_list;\n+\tstruct shared_mem_drv *ethdrv;\n+\tstruct device_list device_list;\n+};\n+\n+static struct shared_mem_bus shared_mem_bus = {\n+\t.bus = {\n+\t\t.scan = dev_scan,\n+\t\t.probe = dev_probe,\n+\t\t.find_device = find_device,\n+\t\t.get_iommu_class = get_iommu_class,\n+\t\t.parse = addr_parse,\n+\t},\n+\n+\t.socket_list = TAILQ_HEAD_INITIALIZER(shared_mem_bus.socket_list),\n+\t.device_list = TAILQ_HEAD_INITIALIZER(shared_mem_bus.device_list),\n+};\n+\n+RTE_REGISTER_BUS(shared_mem, shared_mem_bus.bus);\n+\n+int\n+rte_shm_bus_send_message(void *msg, size_t msglen)\n+{\n+\treturn send(shared_mem_bus.socket_list.tqh_first->fd, msg, msglen, 0);\n+}\n+\n+int\n+rte_shm_bus_recv_message(void *msg, size_t msglen)\n+{\n+\treturn recv(shared_mem_bus.socket_list.tqh_first->fd, msg, msglen, 0);\n+}\n+\n+uintptr_t\n+rte_shm_bus_get_mem_offset(void *ptr)\n+{\n+\tstruct socket_device *dev;\n+\tuintptr_t pval = (uintptr_t)ptr;\n+\n+\tTAILQ_FOREACH(dev, &shared_mem_bus.socket_list, next) {\n+\t\tif (dev->membase < pval && dev->membase + dev->memlen > pval)\n+\t\t\treturn pval - dev->membase;\n+\t}\n+\treturn (uintptr_t)-1;\n+}\n+\n+void *\n+rte_shm_bus_get_mem_ptr(uintptr_t offset)\n+{\n+\tstruct socket_device *dev;\n+\n+\tTAILQ_FOREACH(dev, &shared_mem_bus.socket_list, next) {\n+\t\tif (offset < dev->memlen)\n+\t\t\treturn RTE_PTR_ADD(dev->membase, offset);\n+\t}\n+\treturn (void *)-1;\n+}\n+\n+static int\n+dev_scan(void)\n+{\n+\tif (shared_mem_bus.bus.conf.scan_mode != RTE_BUS_SCAN_ALLOWLIST)\n+\t\treturn 0;\n+\n+\tstruct rte_devargs *devargs;\n+\tRTE_EAL_DEVARGS_FOREACH(shared_mem_bus.bus.name, devargs) {\n+\n+\t\tint fd = socket(AF_UNIX, SOCK_SEQPACKET, 0);\n+\t\tif (fd < 0) {\n+\t\t\tBUS_ERR(\"Error creating socket\");\n+\t\t\treturn -errno;\n+\t\t}\n+\n+\t\tstruct sockaddr_un sun = {.sun_family = AF_UNIX};\n+\t\tif (strlen(devargs->name) - 5 >= sizeof(sun.sun_path) ||\n+\t\t\t\taddr_parse(devargs->name, sun.sun_path) != 0) {\n+\t\t\tBUS_ERR(\"Error parsing device address\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tif (connect(fd, (void *)&sun, sizeof(sun)) != 0) {\n+\t\t\tBUS_ERR(\"Error connecting to socket\");\n+\t\t\treturn -errno;\n+\t\t}\n+\n+\t\tstruct socket_device *sdev = malloc(sizeof(*sdev));\n+\t\tif (sdev == NULL) {\n+\t\t\tBUS_ERR(\"Error with malloc\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tBUS_INFO(\"Allocating dev for %s\", devargs->name);\n+\t\tsdev->rte_device.name = devargs->name;\n+\t\tsdev->rte_device.numa_node = rte_socket_id();\n+\t\tsdev->rte_device.bus = &shared_mem_bus.bus;\n+\t\tsdev->fd = fd;\n+\t\tTAILQ_INSERT_TAIL(&shared_mem_bus.socket_list, sdev, next);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+recv_fd(int from, uint64_t *memsize, rte_iova_t *iova, uint64_t *pg_size)\n+{\n+\tint fd = 0;\n+\tstruct {\n+\t\tuint64_t fd_size;\n+\t\trte_iova_t iova;\n+\t\tuint64_t pg_size;\n+\t} data_message;\n+\n+\tsize_t cmsglen = CMSG_LEN(sizeof(fd));\n+\tstruct cmsghdr *cmhdr = malloc(cmsglen);\n+\tif (cmhdr == NULL) {\n+\t\tBUS_ERR(\"Malloc error\");\n+\t\treturn -1;\n+\t}\n+\n+\tstruct iovec iov = {\n+\t\t\t.iov_base = (void *)&data_message,\n+\t\t\t.iov_len = sizeof(data_message)\n+\t};\n+\tstruct msghdr msg = {\n+\t\t\t.msg_iov = &iov,\n+\t\t\t.msg_iovlen = 1,\n+\t\t\t.msg_control = cmhdr,\n+\t\t\t.msg_controllen = cmsglen,\n+\t};\n+\tif (recvmsg(from, &msg, 0) != (int)iov.iov_len) {\n+\t\tBUS_ERR(\"recvmsg error %s\", strerror(errno));\n+\t\treturn -1;\n+\t}\n+\tif (msg.msg_controllen != cmsglen) {\n+\t\tBUS_ERR(\"Error with fd on message received\");\n+\t\treturn -1;\n+\t}\n+\tfd = *(int *)CMSG_DATA(cmhdr);\n+\n+\tfree(cmhdr);\n+\n+\t*memsize = data_message.fd_size;\n+\t*iova = data_message.iova;\n+\t*pg_size = data_message.pg_size;\n+\treturn fd;\n+}\n+\n+static int\n+dev_probe(void)\n+{\n+\tif (TAILQ_EMPTY(&shared_mem_bus.socket_list))\n+\t\treturn 0;\n+\n+\tif (rte_mbuf_set_platform_mempool_ops(\"shared_mem\") != 0) {\n+\t\tBUS_ERR(\"Error setting default mempool ops\\n\");\n+\t\treturn -1;\n+\t}\n+\tBUS_INFO(\"Set default mempool ops to 'shared_mem'\");\n+\n+\tstruct socket_device *dev;\n+\tTAILQ_FOREACH(dev, &shared_mem_bus.socket_list, next) {\n+\t\tuint64_t memsize = 0;\n+\t\tuint64_t pgsize = 0;\n+\t\trte_iova_t iova = 0;\n+\t\tint memfd = recv_fd(dev->fd, &memsize, &iova, &pgsize);\n+\t\t/* check memfd is valid, the size is non-zero and multiple of 2MB */\n+\t\tif (memfd < 0 || memsize <= 0 || memsize % (1 << 21) != 0) {\n+\t\t\tBUS_ERR(\"Error getting memfd and size\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tBUS_DEBUG(\"Received fd %d with memsize %\"PRIu64\" and pgsize %\"PRIu64,\n+\t\t\t\tmemfd, memsize, pgsize);\n+\n+\t\tvoid *mem = mmap(NULL, memsize, PROT_READ|PROT_WRITE, MAP_SHARED, memfd, 0);\n+\t\tif (mem == MAP_FAILED) {\n+\t\t\tBUS_ERR(\"Error mmapping the received fd\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tBUS_DEBUG(\"%u MB of memory mapped at %p\\n\", (unsigned int)(memsize >> 20), mem);\n+\t\tdev->membase = (uintptr_t)mem;\n+\t\tdev->memlen = memsize;\n+\n+\t\tstruct eth_shared_mem_msg msg = {\n+\t\t\t\t.type = MSG_TYPE_MMAP_BASE_ADDR,\n+\t\t\t\t.offset = dev->membase,\n+\t\t};\n+\t\trte_shm_bus_send_message(&msg, sizeof(msg));\n+\n+\t\tchar malloc_heap_name[32];\n+\t\tsnprintf(malloc_heap_name, sizeof(malloc_heap_name),\n+\t\t\t\t\"socket_%d_ext\", rte_socket_id());\n+\t\tif (rte_malloc_heap_create(malloc_heap_name) != 0) {\n+\t\t\tBUS_ERR(\"Error creating heap %s\\n\", malloc_heap_name);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tint nb_pages = (memsize / pgsize);\n+\t\trte_iova_t *iovas = malloc(sizeof(iovas[0]) * nb_pages);\n+\t\tiovas[0] = iova;\n+\t\tfor (int i = 1; i < nb_pages; i++)\n+\t\t\tiovas[i] = iovas[i - 1] + pgsize;\n+\t\tBUS_DEBUG(\"Attempting to add memory to heap: %s\", malloc_heap_name);\n+\t\tif (rte_malloc_heap_memory_add(malloc_heap_name, mem, memsize,\n+\t\t\t\tiovas, nb_pages, pgsize) < 0) {\n+\t\t\tBUS_ERR(\"Error adding to malloc heap: %s\", strerror(rte_errno));\n+\t\t\tfree(iovas);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tfree(iovas);\n+\t\tBUS_DEBUG(\"Added memory to heap\");\n+\t\trte_malloc_heap_swap_socket(rte_socket_id(),\n+\t\t\t\trte_malloc_heap_get_socket(malloc_heap_name));\n+\t\tBUS_DEBUG(\"Swapped in memory as socket %d memory\\n\", rte_socket_id());\n+\n+\t\tif (shared_mem_bus.ethdrv != NULL) {\n+\t\t\tstruct rte_device *dev = malloc(sizeof(*dev));\n+\t\t\tif (dev == NULL)\n+\t\t\t\treturn -1;\n+\t\t\t*dev = (struct rte_device){\n+\t\t\t\t.name = \"shared_mem_ethdev\",\n+\t\t\t\t.driver = &shared_mem_bus.ethdrv->driver,\n+\t\t\t\t.bus = &shared_mem_bus.bus,\n+\t\t\t\t.numa_node = SOCKET_ID_ANY,\n+\t\t\t};\n+\t\t\tshared_mem_bus.ethdrv->probe(shared_mem_bus.ethdrv, dev);\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+static struct rte_device *\n+find_device(const struct rte_device *start, rte_dev_cmp_t cmp,\n+\t\t\t const void *data)\n+{\n+\tRTE_SET_USED(start);\n+\tRTE_SET_USED(cmp);\n+\tRTE_SET_USED(data);\n+\treturn NULL;\n+}\n+\n+static enum rte_iova_mode\n+get_iommu_class(void)\n+{\n+\t/* if there are no devices, report don't care, otherwise VA mode */\n+\treturn TAILQ_EMPTY(&shared_mem_bus.socket_list) ?  RTE_IOVA_DC : RTE_IOVA_VA;\n+}\n+\n+static int\n+addr_parse(const char *name, void *addr)\n+{\n+\tif (strncmp(name, \"sock:\", 5) != 0) {\n+\t\tBUS_DEBUG(\"no sock: prefix on %s\", name);\n+\t\treturn -1;\n+\t}\n+\n+\tconst char *filename = &name[5];\n+\tstruct stat st;\n+\tif (stat(filename, &st) < 0 || (st.st_mode & S_IFMT) != S_IFSOCK) {\n+\t\tBUS_ERR(\"stat failed, or not a socket, %s\", filename);\n+\t\treturn -1;\n+\t}\n+\tif (addr != NULL)\n+\t\tstrcpy(addr, filename);\n+\tBUS_DEBUG(\"Matched filename: %s\", filename);\n+\treturn 0;\n+}\n+\n+int\n+shared_mem_register_driver(struct shared_mem_drv *drv)\n+{\n+\tif (drv->probe == NULL)\n+\t\treturn -1;\n+\tshared_mem_bus.ethdrv = drv;\n+\treturn 0;\n+}\n+\ndiff --git a/drivers/bus/shared_mem/shared_mem_bus.h b/drivers/bus/shared_mem/shared_mem_bus.h\nnew file mode 100644\nindex 0000000000..01a9a2a99a\n--- /dev/null\n+++ b/drivers/bus/shared_mem/shared_mem_bus.h\n@@ -0,0 +1,75 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef DRIVERS_BUS_SHARED_MEM_H_\n+#define DRIVERS_BUS_SHARED_MEM_H_\n+\n+#include <stdint.h>\n+#include <rte_common.h>\n+#include <rte_ether.h>\n+#include <dev_driver.h>\n+\n+enum shared_mem_msg_type {\n+\tMSG_TYPE_ACK = 0,\n+\tMSG_TYPE_MMAP_BASE_ADDR,\n+\tMSG_TYPE_MEMPOOL_OFFSET,\n+\tMSG_TYPE_RX_RING_OFFSET,\n+\tMSG_TYPE_TX_RING_OFFSET,\n+\tMSG_TYPE_START,\n+\tMSG_TYPE_GET_MAC,\n+\tMSG_TYPE_REPORT_MAC,\n+};\n+\n+struct eth_shared_mem_msg {\n+\tenum shared_mem_msg_type type;  /* type implicitly defines which union member is used */\n+\tunion {\n+\t\tuintptr_t offset;    /* for many messages, just pass an offset */\n+\t\tstruct rte_ether_addr ethaddr; /* allow passing mac address */\n+\t\tuintptr_t datalen;   /* for other messages, pass a data length after the data */\n+\t};\n+\tchar data[];\n+};\n+\n+struct shared_mem_drv;\n+\n+/**\n+ * Initialisation function for the driver\n+ */\n+typedef int (c_eth_probe_t)(struct shared_mem_drv *drv, struct rte_device *dev);\n+\n+struct shared_mem_drv {\n+\tstruct rte_driver driver;\n+\tc_eth_probe_t *probe;            /**< Device probe function. */\n+};\n+\n+/** Helper for PCI device registration from driver (eth, crypto) instance */\n+#define RTE_PMD_REGISTER_SHMEM_DRV(nm, c_drv) \\\n+RTE_INIT(shared_mem_initfn_ ##nm) \\\n+{\\\n+\t(c_drv).driver.name = RTE_STR(nm);\\\n+\tshared_mem_register_driver(&c_drv); \\\n+} \\\n+RTE_PMD_EXPORT_NAME(nm, __COUNTER__)\n+\n+__rte_internal\n+int\n+shared_mem_register_driver(struct shared_mem_drv *drv);\n+\n+__rte_internal\n+int\n+rte_shm_bus_send_message(void *msg, size_t msglen);\n+\n+__rte_internal\n+int\n+rte_shm_bus_recv_message(void *msg, size_t msglen);\n+\n+__rte_internal\n+uintptr_t\n+rte_shm_bus_get_mem_offset(void *ptr);\n+\n+__rte_internal\n+void *\n+rte_shm_bus_get_mem_ptr(uintptr_t offset);\n+\n+#endif /* DRIVERS_BUS_SHARED_MEM_H_ */\ndiff --git a/drivers/bus/shared_mem/version.map b/drivers/bus/shared_mem/version.map\nnew file mode 100644\nindex 0000000000..2af82689b1\n--- /dev/null\n+++ b/drivers/bus/shared_mem/version.map\n@@ -0,0 +1,11 @@\n+INTERNAL {\n+\tglobal:\n+\n+\tshared_mem_register_driver;\n+\trte_shm_bus_get_mem_offset;\n+\trte_shm_bus_get_mem_ptr;\n+\trte_shm_bus_recv_message;\n+\trte_shm_bus_send_message;\n+\n+\tlocal: *;\n+};\n",
    "prefixes": [
        "RFC",
        "1/5"
    ]
}