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GET /api/patches/131888/?format=api
{ "id": 131888, "url": "http://patchwork.dpdk.org/api/patches/131888/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230925080746.16438-6-haifeil@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230925080746.16438-6-haifeil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230925080746.16438-6-haifeil@nvidia.com", "date": "2023-09-25T08:07:46", "name": "[v3,5/5] net/mlx5: add support for item NSH", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "348d7ad31ea2d2dc71ea1a1444b32ae77eeae4cc", "submitter": { "id": 2131, "url": "http://patchwork.dpdk.org/api/people/2131/?format=api", "name": "Haifei Luo", "email": "haifeil@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230925080746.16438-6-haifeil@nvidia.com/mbox/", "series": [ { "id": 29616, "url": "http://patchwork.dpdk.org/api/series/29616/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29616", "date": "2023-09-25T08:07:41", "name": "support item NSH matching", "version": 3, "mbox": "http://patchwork.dpdk.org/series/29616/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/131888/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/131888/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 790D442635;\n\tMon, 25 Sep 2023 10:08:59 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E851D40DDC;\n\tMon, 25 Sep 2023 10:08:46 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2084.outbound.protection.outlook.com [40.107.92.84])\n by mails.dpdk.org (Postfix) with ESMTP id D3C1840A6F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Haifei Luo <haifeil@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <rasland@nvidia.com>,\n <xuemingl@nvidia.com>, <haifeil@nvidia.com>, Dariusz Sosnowski\n <dsosnowski@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>, Matan Azrad\n <matan@nvidia.com>", "Subject": "[PATCH v3 5/5] net/mlx5: add support for item NSH", "Date": "Mon, 25 Sep 2023 11:07:46 +0300", "Message-ID": "<20230925080746.16438-6-haifeil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230925080746.16438-1-haifeil@nvidia.com>", "References": "<20230925020921.4607-1-haifeil@nvidia.com>\n <20230925080746.16438-1-haifeil@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail202.nvidia.com (10.129.68.7)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MN1PEPF0000F0DF:EE_|DM6PR12MB4185:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9a2231aa-80ef-4dfb-bb8a-08dbbd9ea1bc", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n PoiSHavPNof48gDgafHviF/XO+b2U+EJPiI73kz7faSFB942IpmToJ3IlUk7JjP0VJQY1TPa0BqC0cEjRwk7Zym81LK10O3tAU4sD/XEs1BGyKWLn3WCPvWD5O6WsGxbYrs0oNSJuXkLDrJ3By1vNaEb9auIpJvMlDBUaswqSrTWQrlk35x03pXxhePQZwnXUJny/A9kUVcAOlmI8XB6YXdFbUeFkg4jQHxKTC8KI2kTJgpijPQUQtQgOIHAvyReORQtwaHdZcW5gU0w8F1Ksq3zkQgb+XteYQ5FnsNVhZn9KPB3v2uJ7v5VM1SzX3VwnsjmXU7vqXdug64JwBvxkD0vo6nslPInQI/dGYV0s1SjVl63+b6tAnePHcHfYxfHHe+VreErLL3J/Jtr0DieHtKxV4cU28TeWvjmS8xsuN/iRrrxhdGKLSCOgMEaOoEHm6evd7GiuVzt7pRgQsGel0CX96JZMZXaYwVraA7DBOnmizQxZDVb1Aww4EqfKUIgZDHKBB1+ANjAgfxlKdl8AjZ2LqfGnTpf5vmYFUzDQnSlTUSW+0N3zaQkCeQVUIWhPRIMxS2RqV3bf20LqRDudDHlJ83++IDYDLcBYzkSdPjBUdI84sWz4l8A5PlDXCcp5/8A9hZin7akMXSzTR835/cSqMt2qkohNKZ25JnOWYTJQb0TPKPeQDijuwk+GO/91+1wKYUdQXCJk4Xd9AWDR2nrlm5q3yiLeliEITPCqAytmD91/Epwtf5LknMF1FYs", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MN1PEPF0000F0DF.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4185", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "1. Add validation for item NSH.\n It will fail if HCA cap for NSH is false.\n2. Add item_flags for NSH.\n3. For vxlan-gpe if next header is NSH, set next_protocol as NSH.\n\nSigned-off-by: Haifei Luo <haifeil@nvidia.com>\nAcked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 39 +++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 6 +++++\n drivers/net/mlx5/mlx5_flow_dv.c | 13 ++++++++++-\n 3 files changed, 57 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 202e878ddf..8ad85e6027 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -3905,6 +3905,45 @@ mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,\n \t\t\t\t\t MLX5_ITEM_RANGE_NOT_ACCEPTED, error);\n }\n \n+/**\n+ * Validate the NSH item.\n+ *\n+ * @param[in] dev\n+ * Pointer to Ethernet device on which flow rule is being created on.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_flow_validate_item_nsh(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_item *item,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\n+\tif (item->mask) {\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"NSH fields matching is not supported\");\n+\t}\n+\n+\tif (!priv->sh->config.dv_flow_en) {\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n+\t\t\t\t\t NULL, \"NSH support requires DV flow interface\");\n+\t}\n+\n+\tif (!priv->sh->cdev->config.hca_attr.tunnel_stateless_vxlan_gpe_nsh) {\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"Current FW does not support matching on NSH\");\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n flow_null_validate(struct rte_eth_dev *dev __rte_unused,\n \t\t const struct rte_flow_attr *attr __rte_unused,\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 3a97975d69..ccb416e497 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -233,6 +233,9 @@ enum mlx5_feature_name {\n /* IB BTH ITEM. */\n #define MLX5_FLOW_ITEM_IB_BTH (1ull << 51)\n \n+/* NSH ITEM */\n+#define MLX5_FLOW_ITEM_NSH (1ull << 53)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n@@ -2453,6 +2456,9 @@ int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,\n \t\t\t\t uint16_t ether_type,\n \t\t\t\t const struct rte_flow_item_ecpri *acc_mask,\n \t\t\t\t struct rte_flow_error *error);\n+int mlx5_flow_validate_item_nsh(struct rte_eth_dev *dev,\n+\t\t\t\tconst struct rte_flow_item *item,\n+\t\t\t\tstruct rte_flow_error *error);\n int mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev,\n \t\t\t struct mlx5_flow_meter_info *fm,\n \t\t\t uint32_t mtr_idx,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 3f4325c5c8..5cd04b1d93 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -7815,6 +7815,12 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \n \t\t\tlast_item = MLX5_FLOW_ITEM_IB_BTH;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_NSH:\n+\t\t\tret = mlx5_flow_validate_item_nsh(dev, items, error);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\tlast_item = MLX5_FLOW_ITEM_NSH;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n@@ -9720,7 +9726,9 @@ flow_dv_translate_item_vxlan_gpe(void *key, const struct rte_flow_item *item,\n \tv_protocol = vxlan_v->hdr.protocol;\n \tif (!m_protocol) {\n \t\t/* Force next protocol to ensure next headers parsing. */\n-\t\tif (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)\n+\t\tif (pattern_flags & MLX5_FLOW_ITEM_NSH)\n+\t\t\tv_protocol = RTE_VXLAN_GPE_TYPE_NSH;\n+\t\telse if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)\n \t\t\tv_protocol = RTE_VXLAN_GPE_TYPE_ETH;\n \t\telse if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)\n \t\t\tv_protocol = RTE_VXLAN_GPE_TYPE_IPV4;\n@@ -13910,6 +13918,9 @@ flow_dv_translate_items(struct rte_eth_dev *dev,\n \t\tflow_dv_translate_item_ib_bth(key, items, tunnel, key_type);\n \t\tlast_item = MLX5_FLOW_ITEM_IB_BTH;\n \t\tbreak;\n+\tcase RTE_FLOW_ITEM_TYPE_NSH:\n+\t\tlast_item = MLX5_FLOW_ITEM_NSH;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n", "prefixes": [ "v3", "5/5" ] }