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GET /api/patches/132444/?format=api
{ "id": 132444, "url": "http://patchwork.dpdk.org/api/patches/132444/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231009163617.3999365-5-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231009163617.3999365-5-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231009163617.3999365-5-akozyrev@nvidia.com", "date": "2023-10-09T16:36:16", "name": "[4/5] net/mlx5/hws: remove csum check from L3 ok check", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4d8b34b6c030305efc65699e15f08eae1b4b18c5", "submitter": { "id": 1873, "url": "http://patchwork.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231009163617.3999365-5-akozyrev@nvidia.com/mbox/", "series": [ { "id": 29780, "url": "http://patchwork.dpdk.org/api/series/29780/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29780", "date": "2023-10-09T16:36:13", "name": "ptype matching support in mlx5", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29780/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132444/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132444/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C8BC94233F;\n\tMon, 9 Oct 2023 18:37:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2CBA340DF6;\n\tMon, 9 Oct 2023 18:37:06 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40])\n by mails.dpdk.org (Postfix) with ESMTP id 62A4840DF6\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,\n <valex@nvidia.com>, <suanmingm@nvidia.com>, <viacheslavo@nvidia.com>", "Subject": "[PATCH 4/5] net/mlx5/hws: remove csum check from L3 ok check", "Date": "Mon, 9 Oct 2023 19:36:16 +0300", "Message-ID": "<20231009163617.3999365-5-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20231009163617.3999365-1-akozyrev@nvidia.com>", "References": "<20231009163617.3999365-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF0000343E:EE_|BL1PR12MB5971:EE_", "X-MS-Office365-Filtering-Correlation-Id": "21efe41a-f908-4090-0986-08dbc8e5f76f", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n PFYLoBJJ9+MWUdDTVAPp06HcCQ/vTc5FgM3V00yBF7eaUM4Jf1ogu+VPBUNKeBG2At95iAVAqQSypscJu99zWDEBFNs1cfErQq1TJLqJ+6v+LI1IUVpVfTjsO/4T+1xkcbNcY6k0g/NWjJ/7wXQ1WgFb5rHaG2uhTXlhRjh7AxCumardYYvLBIBFPjNL8w3be5mic6exTw+ZSdKmLu2pc9XfRnFxN/Sn7103QLLQY18HbkbHoLMBZJ3I0elVzZFpbNXzNVHljdP9kOnQWn67+CAZzWpGHieYJOR6jKX0LkeJGk4gLfWNzg54NPk4iSeULbbyjpZVi4Zx70oViVRb4lt/wVLFUADZlrD+J9rxqEAlzULrG1iii01uTtpnQQJFCMoTPb0SsVGMj5BuVApsOSzaCQ4XHyLfemKnO/eBU1xW8TgLWKwPc7cKiHStBJPC+TioIIVC7fhhnZM6G+aNuu68vlTEGP0/6Pa0LvHftJ49KXpnM0mlrF2ozNQW3rIWB9EqG3HHJDM0ZMc3F7RyOsg79ZOrdHqfQ3Y2Y7ihxb1yZsCSXM80czxftY2JszjVxWuf44k9BO1wDF0uOhOOBYWpA6kciSW7Pnqh3EexEThy4nmk983OOY6qOa0tbQjhIwoXbUuvY1BEq64HBvMUNROBzh4OOpHDLU6qqUOktr7JM2e8up1PU0bvqX5rAFWoKWihuLQuoy9WzSkEwKr1ws3vqvcrj3D3QysHsC8dfdKyXI2ij1p/+wbdFUVlVmY8", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(39860400002)(396003)(136003)(376002)(230922051799003)(64100799003)(186009)(451199024)(1800799009)(82310400011)(40470700004)(36840700001)(46966006)(70586007)(8936002)(8676002)(5660300002)(4326008)(54906003)(316002)(6916009)(70206006)(41300700001)(40460700003)(2906002)(47076005)(83380400001)(82740400003)(7636003)(356005)(40480700001)(16526019)(336012)(2616005)(426003)(107886003)(86362001)(1076003)(26005)(36860700001)(36756003)(478600001)(6666004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Oct 2023 16:37:02.5653 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 21efe41a-f908-4090-0986-08dbc8e5f76f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS2PEPF0000343E.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5971", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michael Baum <michaelba@nvidia.com>\n\nThis patch changes the integrity item behavior for HW steering.\n\nOld behavior: the \"ipv4_csum_ok\" checks only IPv4 checksum and \"l3_ok\"\nchecks everything is ok including IPv4 checksum.\n\nNew behavior: the \"l3_ok\" checks everything is ok excluding IPv4\nchecksum.\n\nThis change enables matching \"l3_ok\" in IPv6 packets since for IPv6\npackets \"ipv4_csum_ok\" is always miss.\nFor SW steering the old behavior is kept as same as for L4 ok.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 19 ++++++++++++-------\n drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++----\n 2 files changed, 14 insertions(+), 11 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 26cf310e8e..ddec84a9bb 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -667,18 +667,23 @@ Limitations\n \n - Integrity:\n \n- - Integrity offload is enabled starting from **ConnectX-6 Dx**.\n - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.\n - ``level`` value 0 references outer headers.\n - Negative integrity item verification is not supported.\n- - Multiple integrity items not supported in a single flow rule.\n- - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.\n- For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,\n- TCP or UDP, must be in the rule pattern as well::\n+ - With SW steering (``dv_flow_en=1``)\n+ - Integrity offload is enabled starting from **ConnectX-6 Dx**.\n+ - Multiple integrity items not supported in a single flow rule.\n+ - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.\n+ For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,\n+ TCP or UDP, must be in the rule pattern as well::\n \n- flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …\n+ flow create 0 ingress pattern integrity level is 0 value mask l3_ok value spec l3_ok / eth / ipv6 / end …\n \n- flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end …\n+ flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end …\n+\n+ - With HW steering (``dv_flow_en=2``)\n+ - The ``l3_ok`` field represents all L3 checks, but nothing about whether IPv4 checksum ok.\n+ - The ``l4_ok`` field represents all L4 checks including L4 checksum ok.\n \n - Connection tracking:\n \ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex b2c0655790..84d15a41df 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -384,10 +384,8 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,\n \tuint32_t ok1_bits = 0;\n \n \tif (v->l3_ok)\n-\t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) |\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK) |\n-\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_IPV4_CSUM_OK);\n+\t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) :\n+\t\t\t\t BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK);\n \n \tif (v->ipv4_csum_ok)\n \t\tok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :\n", "prefixes": [ "4/5" ] }