Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/132468/?format=api
{ "id": 132468, "url": "http://patchwork.dpdk.org/api/patches/132468/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231010175434.249697-2-hernan.vargas@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231010175434.249697-2-hernan.vargas@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231010175434.249697-2-hernan.vargas@intel.com", "date": "2023-10-10T17:54:33", "name": "[v1,1/2] baseband/acc: support ACC100 deRM corner case SDK", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0e5424e89afbb6df061a52d9ae1a0350f9d7d3cc", "submitter": { "id": 2659, "url": "http://patchwork.dpdk.org/api/people/2659/?format=api", "name": "Hernan Vargas", "email": "hernan.vargas@intel.com" }, "delegate": { "id": 2642, "url": "http://patchwork.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231010175434.249697-2-hernan.vargas@intel.com/mbox/", "series": [ { "id": 29797, "url": "http://patchwork.dpdk.org/api/series/29797/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29797", "date": "2023-10-10T17:54:32", "name": "FlexRAN SDK update for 23.11", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29797/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132468/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132468/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E18A74234E;\n\tTue, 10 Oct 2023 19:55:22 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6B008406FF;\n\tTue, 10 Oct 2023 19:55:17 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id CCE34406FF\n for <dev@dpdk.org>; Tue, 10 Oct 2023 19:55:14 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 10 Oct 2023 10:55:11 -0700", "from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103])\n by fmsmga005.fm.intel.com with ESMTP; 10 Oct 2023 10:55:00 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1696960515; x=1728496515;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=C7XwnoeaTUX0e8v2vZjqeKx06STHttwJj2nweFi7ot0=;\n b=g0XpM/sX5KdVZhlSWZcyQvoIg2oTRusEsY2lbWqy/jEvQPP+D5zKomKM\n 9emaC876B64schwANzBvRM9yiUrnrqD/KoAwWCilGNLPEPnz3EWRw3+Di\n GGfd6ZDmNngJVyskabm2Ag+lwN4Wuqi5cPRYbPgu1VW+/aY1IusP0+3bA\n C7EIA9oVf5eV5fO3Uc7sj8YGWEETrG8H1yP8QNA4Qftr8XL5unq0Uw/pw\n hXrPEc1bvUJ4X7JGzS+1RnSt4nUqprFuxORqAlaUFUJ1rkbVRzEPtyM1E\n Kbj8HIxrbybHLGZoM5p4cO8SouLbJmIbwU7gr83HjVghMSHC4w2/GJSTj Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10859\"; a=\"415497127\"", "E=Sophos;i=\"6.03,213,1694761200\"; d=\"scan'208\";a=\"415497127\"", "E=McAfee;i=\"6600,9927,10859\"; a=\"1084896402\"", "E=Sophos;i=\"6.03,213,1694761200\"; d=\"scan'208\";a=\"1084896402\"" ], "X-ExtLoop1": "1", "From": "Hernan Vargas <hernan.vargas@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>", "Subject": "[PATCH v1 1/2] baseband/acc: support ACC100 deRM corner case SDK", "Date": "Tue, 10 Oct 2023 10:54:33 -0700", "Message-Id": "<20231010175434.249697-2-hernan.vargas@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20231010175434.249697-1-hernan.vargas@intel.com>", "References": "<20231010175434.249697-1-hernan.vargas@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Implement de-ratematch pre-processing for ACC100 SW corner cases.\nSome specific 5GUL FEC corner cases may cause unintended back pressure\nand in some cases a potential stability issue on the ACC100.\nThe PMD can detect such code block configuration and issue an info\nmessage to the user.\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\n---\n drivers/baseband/acc/meson.build | 23 ++++++++++-\n drivers/baseband/acc/rte_acc100_pmd.c | 59 +++++++++++++++++++++++++--\n 2 files changed, 77 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build\nindex 27a654b50153..84f4fea635ef 100644\n--- a/drivers/baseband/acc/meson.build\n+++ b/drivers/baseband/acc/meson.build\n@@ -1,7 +1,28 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2020 Intel Corporation\n \n-deps += ['bus_pci']\n+# check for FlexRAN SDK libraries\n+dep_dec5g = dependency('flexran_sdk_ldpc_decoder_5gnr', required: false)\n+\n+if dep_dec5g.found()\n+ ext_deps += cc.find_library('stdc++', required: true)\n+ ext_deps += cc.find_library('irc', required: true)\n+ ext_deps += cc.find_library('imf', required: true)\n+ ext_deps += cc.find_library('ipps', required: true)\n+ ext_deps += cc.find_library('svml', required: true)\n+ ext_deps += dep_dec5g\n+ ext_deps += dependency('flexran_sdk_ldpc_encoder_5gnr', required: true)\n+ ext_deps += dependency('flexran_sdk_LDPC_ratematch_5gnr', required: true)\n+ ext_deps += dependency('flexran_sdk_rate_dematching_5gnr', required: true)\n+ ext_deps += dependency('flexran_sdk_turbo', required: true)\n+ ext_deps += dependency('flexran_sdk_crc', required: true)\n+ ext_deps += dependency('flexran_sdk_rate_matching', required: true)\n+ ext_deps += dependency('flexran_sdk_common', required: true)\n+ cflags += ['-DRTE_BBDEV_SDK_AVX2']\n+ cflags += ['-DRTE_BBDEV_SDK_AVX512']\n+endif\n+\n+deps += ['bbdev', 'bus_pci']\n \n sources = files('rte_acc100_pmd.c', 'rte_vrb_pmd.c')\n \ndiff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c\nindex 5362d39c302f..e45137212f68 100644\n--- a/drivers/baseband/acc/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc/rte_acc100_pmd.c\n@@ -22,6 +22,10 @@\n #include \"acc101_pmd.h\"\n #include \"vrb_cfg.h\"\n \n+#ifdef RTE_BBDEV_SDK_AVX512\n+#include <phy_rate_dematching_5gnr.h>\n+#endif\n+\n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);\n #else\n@@ -3058,7 +3062,8 @@ derm_workaround_recommended(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct acc_q\n /** Enqueue one decode operations for ACC100 device in CB mode */\n static inline int\n enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n-\t\tuint16_t total_enqueued_cbs, bool same_op)\n+\t\tuint16_t total_enqueued_cbs, bool same_op,\n+\t\tstruct rte_bbdev_queue_data *q_data)\n {\n \tint ret;\n \tif (unlikely(check_bit(op->ldpc_dec.op_flags,\n@@ -3113,8 +3118,54 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,\n \t\tstruct acc_fcw_ld *fcw;\n \t\tuint32_t seg_total_left;\n \n-\t\tif (derm_workaround_recommended(&op->ldpc_dec, q))\n-\t\t\trte_bbdev_log(INFO, \"Corner case may require deRM pre-processing\");\n+\t\tif (derm_workaround_recommended(&op->ldpc_dec, q)) {\n+\t\t\t#ifdef RTE_BBDEV_SDK_AVX512\n+\t\t\tstruct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;\n+\t\t\tstruct bblib_rate_dematching_5gnr_request derm_req;\n+\t\t\tstruct bblib_rate_dematching_5gnr_response derm_resp;\n+\t\t\tuint8_t *in;\n+\n+\t\t\t/* Checking input size is matching with E */\n+\t\t\tif (dec->input.data->data_len < (dec->cb_params.e % 65536)) {\n+\t\t\t\trte_bbdev_log(ERR, \"deRM: Input size mismatch\");\n+\t\t\t\treturn -EFAULT;\n+\t\t\t}\n+\t\t\t/* Run first deRM processing in SW */\n+\t\t\tin = rte_pktmbuf_mtod_offset(dec->input.data, uint8_t *, in_offset);\n+\t\t\tderm_req.p_in = (int8_t *) in;\n+\t\t\tderm_req.p_harq = (int8_t *) q->derm_buffer;\n+\t\t\tderm_req.base_graph = dec->basegraph;\n+\t\t\tderm_req.zc = dec->z_c;\n+\t\t\tderm_req.ncb = dec->n_cb;\n+\t\t\tderm_req.e = dec->cb_params.e;\n+\t\t\tif (derm_req.e > ACC_MAX_E) {\n+\t\t\t\trte_bbdev_log(WARNING,\n+\t\t\t\t\t\t\"deRM: E %d > %d max\",\n+\t\t\t\t\t\tderm_req.e, ACC_MAX_E);\n+\t\t\t\tderm_req.e = ACC_MAX_E;\n+\t\t\t}\n+\t\t\tderm_req.k0 = 0; /* Actual output from SDK */\n+\t\t\tderm_req.isretx = false;\n+\t\t\tderm_req.rvid = dec->rv_index;\n+\t\t\tderm_req.modulation_order = dec->q_m;\n+\t\t\tderm_req.start_null_index =\n+\t\t\t\t\t(dec->basegraph == 1 ? 22 : 10)\n+\t\t\t\t\t* dec->z_c - 2 * dec->z_c\n+\t\t\t\t\t- dec->n_filler;\n+\t\t\tderm_req.num_of_null = dec->n_filler;\n+\t\t\tbblib_rate_dematching_5gnr(&derm_req, &derm_resp);\n+\t\t\t/* Force back the HW DeRM */\n+\t\t\tdec->q_m = 1;\n+\t\t\tdec->cb_params.e = dec->n_cb - dec->n_filler;\n+\t\t\tdec->rv_index = 0;\n+\t\t\trte_memcpy(in, q->derm_buffer, dec->cb_params.e);\n+\t\t\t/* Capture counter when pre-processing is used */\n+\t\t\tq_data->queue_stats.enqueue_warn_count++;\n+\t\t\t#else\n+\t\t\tRTE_SET_USED(q_data);\n+\t\t\trte_bbdev_log(INFO, \"Corner case may require deRM pre-processing in SDK\");\n+\t\t\t#endif\n+\t\t}\n \n \t\tfcw = &desc->req.fcw_ld;\n \t\tq->d->fcw_ld_fill(op, fcw, harq_layout);\n@@ -3647,7 +3698,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data,\n \t\t\tops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m,\n \t\t\tops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e,\n \t\t\tsame_op);\n-\t\tret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op);\n+\t\tret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data);\n \t\tif (ret < 0) {\n \t\t\tacc_enqueue_invalid(q_data);\n \t\t\tbreak;\n", "prefixes": [ "v1", "1/2" ] }